Sub-threshold single-cycle clock frequency reduction control circuit

Abstract

The invention relates to a sub-threshold single-cycle clock frequency reduction control circuit. The control circuit comprises two input ports; one output port, the input end port inputs a clock signal and an input pulse signal respectively; and the output port outputs the clock down-conversion signal after frequency reduction, and based on the sub-threshold single-cycle clock down-conversion control circuit provided by the invention, the clock down-conversion signal after frequency reduction is output by controlling the level states of the input pulse signal and the clock signal, so that single-cycle clock down-conversion control is realized. The sub-threshold single-cycle clock frequency reduction control circuit provided by the invention is simple in control signal and suitable for being applied to fault-tolerant design, error correction control and circuits with single-cycle clock frequency reduction requirements.

Description

technical field

[0001] The invention relates to the field of sub-threshold frequency reduction control, in particular to a sub-threshold single-cycle clock frequency reduction control circuit. Background technique

[0002] As the size of the process shrinks, errors caused by the process of random doping concentration changes and lithographic precision errors are more prominent at the sub-threshold voltage. Affected by process variation, the robustness of the circuit becomes poor. Latch-type pipelines may have errors in the case of time borrowing. Using a clock down-frequency circuit can effectively solve the problem of time borrowing. Although the traditional clock frequency reduction circuit can solve the problem of time borrowing, it has many frequency reduction cycles and complex control signals, which have a relatively large impact on the throughput of the circuit, resulting in a waste of performance. Contents of the invention

[0003] The purpose of the present inve...

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