High-speed decoder based on non-binary LDPC code and decoding method thereof

Abstract

The invention discloses a high-throughput and low-complexity hierarchy decoder suitable for a non-binary LDPC code and a decoding method of the decoder. The decoder comprises a relative addressing unit, a caching unit and a computing unit, wherein the relative addressing unit prestores an input address for each of the computing unit and the caching unit so that a redundant clock period is inexistent between tiers; the depth of the caching unit is 1 so that the delay is maximally lowered; the computing unit comprises 2p-1 basic computing units capable of accomplishing the updating of one tire in a clock unit and optimizing a key path of each module so as to improve the clock frequency. Furthermore, the decoding method disclosed by the invention is a hard decoding method based on majority logic so as to take a compromise on the decoding performance and the complexity; a most reliable message and a secondary reliable message are selected in the method, symbols and confidences thereof are input and output in a bit way, 2p messages are converted into the transmission of P messages, and the storage space is greatly lowered.

Description

Technical field [0001] The invention relates to a decoder and a decoding method in the field of communication technology; in particular, it relates to a high-speed decoder and a decoding method based on a multi-ary LDPC code in a communication system. Background technique [0002] In a communication system, the transmitted data source may be digital signals, such as computers, mobile devices, keyboards, etc. There are various noises in the digital channel. Therefore, in the process of data transmission, it is necessary to introduce forward error correction (FEC) or channel coding. The sending end performs error correction code coding and coding by adding redundant bits. After the signal arrives at the receiving end through the noisy channel, it is decoded, and a certain degree of error correction can be performed directly. [0003] Low-density parity check (LDPC) code, as a kind of forward error correction code, was proposed by Gallager in 1963. Its performance can theoretically b...

AI Technical Summary

Problems solved by technology

The full parallel scheme can achieve the fastest throughput, but consumes the largest area. In the communication system, due to the large area occupied, it is not practical; the serial scheme consumes the least area, but the delay is the largest, which seriously affects the data throughput. For today's high-speed communication systems, it is not very practical; the widely used scheme is a partial serial architecture, because it can take a good compromise between throughput and area consumption according to needs, quasi-cyclic multi-ary system The design of LDPC codes provides more favorable conditions for the hardware architecture design of partial parallel schemes

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