LDPC decoding method combining bit flipping (BF) and majority logic (MLG)

A large number logic and bit flip technology, which is applied in the field of LDPC decoding of mixed bit flip and large number logic, can solve the problems of complex calculation and poor decoding performance, and achieve simple calculation, reduced delay, and good decoding performance. Effect

Inactive Publication Date: 2010-05-12
TIANJIN BOWEI TECH
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[0020] In summary, in view of the problems of poor decoding performance and complex calculations in the existing BF decoding methods, there i

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  • LDPC decoding method combining bit flipping (BF) and majority logic (MLG)
  • LDPC decoding method combining bit flipping (BF) and majority logic (MLG)
  • LDPC decoding method combining bit flipping (BF) and majority logic (MLG)

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[0047] Specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0048] The present invention is a mixed decoding method using bit inversion and large number logic for FG-LDPC codes with orthogonal consistency check, now using the first type of Euclidean geometric low-density parity check code——(1023,781)EG - LDPC code as an example, where 781 represents the length of the input information bit, and 1023 represents the length of the code word output after error correction coding. Bit v participates in 32 checks, and each check contains 32 bits. Define U(v) to denote the number of invalid checksums containing bit v. The bipartite graph representation of the (1023, 781) EG-LDPC code is as follows figure 2 shown. Define D(a, b) to represent the distance between node a and node b in the bipartite graph, in figure 2 Among them, D(v, v 1.1 )=2,D(v,c 1 )=1.

[0049] According to the bipartite graph of the ...

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Abstract

The invention relates to a LDPC decoding method combining bit flipping (BF) and majority logic (MLG), belonging to the technical field of digital information transmission. The LDPC decoding method comprising the following steps of: (1) computing syndromes s of a check matrix of M rows and N columns, wherein s=(s1, s2, to sM), if the syndromes are all 0, and then carrying out step 4; (2) finding the most unreliable bit through a bit reliability measurement; (3) flipping and finding out the most unreliable bit; (4) when a largest iteration is achieved, carrying out step (5), and when all the syndromes are all 0, stopping decoding and outputting corresponding codons to complete decoding treatment, or else, repeating the steps of (1) to (3); and (5) sending the codons containing non 0 value in the syndromes to an MLG decoder for decoding, and finally outputting the codons decoded by the majority logic decoder to complete the decoding treatment. The invention utilizes the decoding method combining BF decoding and MLG without floating point arithmetic in the whole decoding process, reduces computation complexity and time delaying, and has favorable decoding performance.

Description

technical field [0001] The invention belongs to the technical field of digital information transmission, in particular to an LDPC decoding method combining bit flipping and large number logic. Background technique [0002] Low Density Parity Check (LDPC, Low Density Parity Check) code is a channel code widely used in the field of digital information transmission at present. As an ordinary linear block code, LDPC code is usually represented by generator matrix G and check matrix H, and its characteristic is that the number of non-zero elements in parity check matrix H is much smaller than the number of zero elements. In the process of information transmission, the receiving end needs to decode the LDPC code. The LDPC decoding methods mainly include tree decoding, probability decoding, sum product decoding, minimum sum decoding, bit flip decoding and large number logic decoding. All the above-mentioned decoding methods have certain limitations. The bit-flip decoding method i...

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Application Information

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IPC IPC(8): H03M13/11
Inventor 门爱东兰军唐光王洪湔华建军陈志欧阳书平
Owner TIANJIN BOWEI TECH
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