High speed turbo codes decoder for 3g using pipelined siso log-map decoders architecture

Abstract

A baseband processor is provided having Turbo Codes Decoders with Diversity processing for computing baseband signals from multiple separate antennas. The invention decodes multipath signals that have arrived at the terminal via different routes after being reflected from buildings, trees or hills. The Turbo Codes Decoder with Diversity processing increases the signal to noise ratio (SNR) more than 6 dB which enables the 3rd Generation Wireless system to deliver data rates from up to 2 Mbit / s. The invention provides several improved Turbo Codes Decoder methods and devices that provide a more suitable, practical and simpler method for implementation a Turbo Codes Decoder in ASIC (Application Specific Integrated Circuits) or DSP codes. A plurality of parallel Turbo Codes Decoder blocks is provided to compute baseband signals from multiple different receiver paths. Several pipelined max-Log-MAP decoders are used for iterative decoding of received data. A Sliding Window of Block N data is used for pipeline operations. In a pipeline mode, a first decoder A decodes block N data from a first source, while a second decoder B decodes block N data from a second source during the same clock cycle. Pipelined max-Log-MAP decoders provide high speed data throughput and one output per clock cycle.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]This application is a continuation-in-part of patent application Ser. No. 90 / 008,190 filed Aug. 25, 2006.BACKGROUND OF INVENTION[0002]1. Field of the Invention[0003]This invention relates to Wireless Baseband Processors (Baseband Decoder) and Forward Error-Correction (FEC) Codes for 3rd Generation (3G) Wireless Mobile Communications. More particularly, the invention relates to a very high speed Turbo Codes Decoder implementing diversity processing and pipelined Max Log-MAP decoders for 3G Code Division Multiple Access (CDMA2000) and 3G Wideband Code Division Multiple Access (WCDMA).[0004]2. Description of Prior Art[0005]Diversity processing computes signals from two or more separate antennas using so-called “multipath” signals that arrive at the terminal via different routes after being reflected from buildings, trees or hills. Diversity processing can increase the signal to noise ratio (SNR) more than 6 dB, which enables 3G systems to de...

AI Technical Summary

Benefits of technology

[0012]The present invention is directed to Baseband Processor using diversity processing to implement a more efficient, practical and suitable architecture and method to achieve the requirements for 3 G wireless systems, including the features of higher speed data throughput, lower power consumptions, lower costs, and suitable for implementation in ASIC or DSP codes. The present invention encompasses several improved and simplified Turbo Codes Decoder methods and devices to deliver higher speed and lower power consumption, especially for 3G applications. Diversity processing can increase the signal to noise ratio (SNR) more than 6 dB, which enables 3G systems to deliver data rates up to 2 Mbit / s. As shown in FIG. 3, an exemplary embodiment of the Turbo Codes Decoder utilizes two parallel Turbo Codes Decoders for diversity processing. Each Turbo Codes Decoder has serially concatenated Soft-input Soft-output logarithm maximum a posteriori (SISO Log-MAP) Decoders. The two decoders function in a pipelined scheme with delay latency N. While the first decoder is decoding data stored in the second-decoder-Memory, the second decoder performs decoding for data stored in the first-decoder-Memory, which produces a decoded output every clock cycle. As shown in FIG. 5, the Turbo Codes Decoder utilizes a Sliding Window of Block N on the input buffer memory to decode data per block N, which improves processing efficiency. Accordingly, several objects and advantages of the Turbo Codes Decoder are:

[0015]To utilize SISO Log-MAP decoders for best result and faster decoding and simplified implementation in ASIC circuits and DSP codes with the use of binary adders for computation.

[0017]To utilize a Sliding Window of Block N on the input buffer memory to decode data per block N for improved pipeline processing efficiency

[0018]To provide higher performance in term of symbol error probability and low BER (10−6) for 3G applications such as 3G WCDMA, and 3G CDMA2000 operating at very high bit-rate up to 100 Mbps, in a low power, noisy environment.

[0020]To reduce complexity of multiplier circuits in MAP algorithm by performing the entire MAP algorithm in Log Max approximation using binary adder circuits, which are more suitable for ASIC and DSP codes implementation, while still maintaining a high level of performance output.

Problems solved by technology

A drawback of the Viterbi Algorithm Decoder is that it requires a long wait for decisions until the whole sequence has been received.

The MAP algorithm is computationally complex, requiring many multiplications and additions per bit to compute the posteriori probability.

A major difficulty with the use of the MAP algorithm has been the implementation in semiconductor ASIC devices.

The complexity of the multiplications and additions slow down the decoding process and reduce the throughput data rates.

Furthermore, even under the best conditions, multiplication operations in the MAP algorithm require implementation using large circuits in the ASIC.

The result is costly design and low performance in bit rates throughput.

However, patents by Berrou et al., Divsalar et al., and others only describe the concept of parallel concatenated codes using mathematical equations which are good for research in deep space communications and other government projects, but are not feasible, economical, and suitable for consumer portable wireless devices.

But decoding the Turbo Codes is much more difficult to implement in ASIC or software.

All the prior art Turbo Codes fail to provide simple and suitable methods and architectures for a Turbo Codes Decoder as it is required and desired for 3G cellular phones and 3G personal communication devices, including the features of high speed data throughput, low power consumption, lower costs, limited bandwidth, and limited power transmitter in noisy environments.

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