Execution of data-parallel programs on coarse-grained reconfigurable architecture hardware

a data-parallax and reconfigurable architecture technology, applied in the direction of computation using denominational number representation, multi-programming arrangements, instruments, etc., can solve the problems of reducing the energy efficiency of modern gpgpus and general-purpose von-neumann processors, model power inefficiencies,

Inactive Publication Date: 2015-09-24
TECHNION RES & DEV FOUND LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0012]A Single Graph Multiple Flows (SGMF) execution model disclosed herein combines pipelining and dynamic dataflow to extract thread

Problems solved by technology

Nevertheless, existing GPGPUs employ a von-Neumann compute engine and, therefore, suffer from the model's power inefficiencies.
These

Method used

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  • Execution of data-parallel programs on coarse-grained reconfigurable architecture hardware
  • Execution of data-parallel programs on coarse-grained reconfigurable architecture hardware
  • Execution of data-parallel programs on coarse-grained reconfigurable architecture hardware

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Embodiment Construction

[0055]In the following description, numerous specific details are set forth in order to provide a thorough understanding of the various principles of the present invention. It will be apparent to one skilled in the art, however, that not all these details are necessarily always needed for practicing the present invention. In this instance, well-known circuits, control logic, and the details of computer program instructions for conventional algorithms and processes have not been shown in detail in order not to obscure the general concepts unnecessarily.

[0056]The various elements and embodiments of the invention can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment containing both hardware and software elements. The invention may be implemented in software, which includes but is not limited to firmware, resident software, microcode, etc.

[0057]Although the present invention is described in a particular hardware embodiment, those of ordin...

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Abstract

A GPGPU-compatible architecture combines a coarse-grain reconfigurable fabric (CGRF) with a dynamic dataflow execution model to accelerate execution throughput of massively thread-parallel code. The CGRF distributes computation across a fabric of functional units. The compute operations are statically mapped to functional units, and an interconnect is configured to transfer values between functional units.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application claims the benefit of U.S. Provisional Patent Application No. 61 / 969,184, filed Mar. 23, 2014, which is herein incorporated by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]This invention relates to administration of task execution in a digital data processing system. More particularly, this invention relates to transaction and job processing between multiple processors, computers, or digital data processing systems[0004]2. Description of the Related Art[0005]The meanings of certain acronyms and abbreviations used herein are given in Table 1.TABLE 1Acronyms and Abbreviations8-NNEight Nearest NeighborsALUArithmetical-Logical UnitCDFGControl Data Flow GraphCGRFCoarse Grain Reconfigurable FabricCUDACompute Unified Device ArchitectureDRAMDynamic Random Access MemoryFCFRFirst Come First ReadFIFOFirst-In-First-OutFLOPFloating Point OperationFPUfloating point unitFR-FCFSFirst Ready - First Come First ...

Claims

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Application Information

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IPC IPC(8): G06F9/38G06F9/48
CPCG06F9/3869G06F9/4881G06F9/3855G06F9/38G06F9/3851G06F9/448G06F9/4494
Inventor ETSION, YOAVVOITSECHOV, DANI
Owner TECHNION RES & DEV FOUND LTD
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