Image processing IP core based on Wishbone bus

An image processing and bus technology, applied in processor architecture/configuration, cathode ray tube indicators, instruments, etc., can solve the problems of slow equipment upgrade, long development cycle, low cost performance, etc., and achieve convenient and fast function expansion, Realize the effect of structure and function, and shorten the development cycle

Inactive Publication Date: 2009-12-30
黄以华
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This patented describes how we use wireless communication techniques (Wibber) to connect different types of electronic components together into systems that work together like computers or servers. These connections allow us to create more efficient ways of transmitting signals between them while maintaining their original functionality. It also allows users to tailor these networks by changing parameters such as signal timing or resolution levels depending upon specific applications they want to achieve. Overall, this new network architecture makes it easier than previous methods because there're no longer any limitations associated with current designs.

Problems solved by technology

The problem addressed in this patents relates to how fast images are processed without sacrificing their quality. Traditional imagers require external memory devices like RAM (Random Access Memory) which limits its functionality. This limitation makes them difficult to use outside these areas where they were designed specifically. Additionally, current hardware-based systems lacked flexible options such as customizable fuzzy logic circuits.

Method used

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  • Image processing IP core based on Wishbone bus
  • Image processing IP core based on Wishbone bus
  • Image processing IP core based on Wishbone bus

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Embodiment Construction

[0029] In order to explain the technical features of the present invention more deeply, the detailed description will be given below in conjunction with the accompanying drawings.

[0030] Such as figure 1 As shown, a kind of image processing IP core based on Wishbone bus, it mainly comprises main controller interface module, SDRAM control module, command explanation module, display control module and bus arbitration module; Described each module all passes through Wishbone interface, adopts The interconnection method of the shared bus realizes the connection of each module and the exchange of data. The main controller interface module, SDRAM control module, command interpretation module, and display control module all have a Wishbone bus interface and are connected with the shared bus mode in the Wishbone specification. They must submit a request to the bus arbitration module when competing for the right to use the bus. Apply. The bus arbitration module sorts the bus reques...

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Abstract

The invention discloses an image processing IP core based on a Wishbone bus, mainly comprising a host controller interface module, an SDRAM control module, a command interpretation module, a display control module and a bus arbitration module; wherein all the modules are connected and exchange data by Wishbone interfaces in a bus sharing interconnection manner. The host controller interface module, the SDRAM control module, the command interpretation module and the display control module are all provided with a Wishbone bus interface, are connected in the bus sharing manner in Wishbone specification and are all required to send a request to the bus arbitration module when fighting for bus use right. The IP core is specially applied to image processing, can realize multiple algorithms such as scaling, rotation and Alpha Blending and has strong function, simple structure and good expansibility.

Description

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Claims

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Application Information

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Owner 黄以华
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