Semiconductor device

Abstract

The present invention provides a novel semiconductor device. The present invention uses a comparison unit for comparing two current values, a control unit, and a current output type digital-analog conversion unit to convert an analog signal into a digital signal. The control unit has the function of generating a sign bit indicating the magnitude relation between the two current values, the function of converting, by successive approximation, the difference between the two current values into the digital signal, and the function of outputting the sign bit and the digital signal.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Or, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter.

[0003] More specifically, as the technical field of one aspect of the present invention disclosed in this specification, semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, storage devices, signal processing devices, processors, electronic devices, systems, their driving methods, their manufacturing methods, or their inspection methods can be cited as an example.

[0004] Note that in this specification and the like, the semiconductor device refers to all things that can function by utilizing semiconductor characteristics. Therefore, semiconductor elements such as transistors and diodes, and circuits including semiconductor elements are semiconductor devices. In addition, display devices, light-emitting devices, lighting devices, electro-optical devices, communication devices, and electronic devices may include semiconductor elements or semiconductor circuits. Therefore, display devices, light-emitting devices, lighting devices, electro-optical devices, imaging devices, communication devices, and electronic devices may also be called semiconductor devices.

Background Art

[0005] AD (Analog to Digital) conversion devices that convert analog signals into digital signals are known. As AD conversion devices, AD conversion devices with various conversion methods such as delta-sigma type, pipeline type, flash type, and successive approximation (SA) type have been developed.

[0006] A successive-approximation type AD converter can achieve a resolution of 16 bits, has low power consumption, and is often used in applications where the sampling frequency is 10 MHz or less. A successive-approximation type AD converter includes a comparison unit (comparator), a DA (Digital to Analog) conversion unit, and a successive approximation register (SAR: Successive Approximation Register). Patent Document 1 discloses an AD converter that converts the potential difference between two analog signals into a digital signal.

Prior Art Documents

Patent Documents

[0007]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0008] Since the AD converter disclosed in Patent Document 1 uses a capacitive array type DA conversion unit, a significant increase in the occupied area is inevitable in order to increase the resolution. In addition, when the input signal is an analog current, it is necessary to add a circuit for replacing the current signal with a voltage signal.

[0009] One aspect of the present invention aims to provide a semiconductor device with a reduced occupied area. Or, one aspect of the present invention aims to provide a semiconductor device with reduced power consumption. Or, one aspect of the present invention aims to provide a semiconductor device with improved operation speed. Or, one aspect of the present invention aims to provide a novel semiconductor device.

[0010] The problems of one aspect of the present invention are not limited to the problems listed above. The problems listed above do not prevent the existence of other problems. Other problems are those not mentioned in this item as described below. Problems not mentioned in this item can be derived from the descriptions in the specification, drawings, etc. by those skilled in the art and can be appropriately extracted from these descriptions. One aspect of the present invention solves at least one of the problems listed above and other problems. One aspect of the present invention does not necessarily solve all of the problems listed above and other problems.

Means for Solving the Problems

[0011] One aspect of the present invention is a semiconductor device including a comparison unit that compares the current value of a first signal and the current value of a second signal, a first digital-to-analog conversion unit, a second digital-to-analog conversion unit, and a control unit. The comparison unit has a function of comparing the first signal and the second signal and generating an output signal. The control unit has a function of generating a sign bit according to the output signal, a function of generating a digital signal, and a function of outputting the sign bit and the digital signal. The first digital-to-analog conversion unit has a function of adding a current having a current value corresponding to the digital signal to the first signal. The second digital-to-analog conversion unit has a function of adding a current having a current value corresponding to the digital signal to the second signal.

[0012] The sign bit is determined according to the magnitude relationship between the first signal and the second signal. For example, it may be set to “0” when the current value of the first signal is greater than the current value of the second signal, and “1” otherwise. The digital signal generated by the control unit can be determined according to the differential current between the first signal and the second signal. The digital signal may be, for example, a digital value of 8 bits or more and 16 bits or less.

[0013] The comparison unit functions as a current comparison type comparator. The semiconductor device according to one aspect of the present invention functions as a successive approximation type AD conversion device. Also, the semiconductor device according to one aspect of the present invention can also function as a ReLu function.

Effects of the Invention

[0014] According to one aspect of the present invention, a semiconductor device with a reduced occupied area can be provided. Or, a semiconductor device with reduced power consumption can be provided. Or, a semiconductor device with improved operation speed can be provided. Or, a novel semiconductor device can be provided.

[0015] Note that the effects of one aspect of the present invention are not limited to the effects listed above. The effects listed above do not prevent the existence of other effects. Other effects are the effects not mentioned in this item described below. The effects not mentioned in this item can be derived by those skilled in the art from the descriptions in the specification, drawings, etc., and can be appropriately extracted from these descriptions. Note that one aspect of the present invention has at least one of the effects listed above and other effects. Therefore, one aspect of the present invention may not have the effects listed above.

Brief Description of the Drawings

[0016] FIG. 1 is a diagram for explaining an AD conversion device. FIG. 2 is a flowchart for explaining an AD conversion device. FIG. 3 is a diagram for explaining a successive comparison operation. FIG. 4 is a diagram for explaining an AD conversion device. FIGS. 5A and 5B are diagrams for explaining a comparison unit. FIGS. 6A and 6B are diagrams for explaining a DA conversion unit. FIGS. 7A to 7E are diagrams for explaining the circuits included in the DA conversion unit. FIG. 8A is a diagram for explaining a DA conversion unit. FIGS. 8B to 8F are diagrams for explaining the circuits included in the DA conversion unit. FIGS. 9A and 9B are diagrams for explaining a hierarchical neural network. FIGS. 10A and 10B are diagrams for explaining a semiconductor device. FIGS. 11A and 11B are diagrams for explaining a semiconductor device. FIG. 12 is a diagram for explaining a semiconductor device. FIG. 13 is a flowchart for explaining an operation example of the AD conversion device. FIGS. 14A and 14B are diagrams for explaining an operation example of the AD conversion device. FIG. 15 is a diagram for explaining a configuration example of the display device. FIGS. 16A and 16B are diagrams for explaining a configuration example of the display device. FIGS. 17A and 17B are diagrams for explaining a configuration example of the pixel. FIGS. 18A to 18D are diagrams for explaining an operation example of the display element. FIGS. 19A and 19B are diagrams for explaining an operation example of the display element. FIG. 20 is a diagram for explaining a configuration example of the AD conversion circuit. FIG. 21 is a diagram for explaining an operation example of the AD conversion circuit. FIG. 22 is a diagram for explaining the semiconductor device. FIGS. 23A to 23C are diagrams showing a configuration example of the transistor. FIG. 24A is a diagram for explaining the classification of the crystal structure, FIG. 24B is a diagram for explaining the XRD spectrum of the crystalline IGZO, and FIG. 24C is a diagram for explaining the nanoelectron diffraction pattern of the crystalline IGZO. FIG. 25A is a flowchart showing an example of a method for manufacturing an electronic component, FIG. 25B is a top view of the semiconductor wafer, FIG. 25C is an enlarged view of a part of the semiconductor wafer, FIG. 25D is a schematic diagram of the chip, and FIG. 25E is a perspective schematic diagram showing a configuration example of the electronic component. FIGS. 26A to 26J are diagrams showing an example of the electronic device. FIGS. 27A to 27C are diagrams for explaining an example of the electronic device. FIG. 28 shows the measurement results of the input / output characteristics of the AD conversion device.

Embodiments for Carrying Out the Invention

[0017] Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not construed as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are commonly used among different drawings for the same part or parts having the same or similar functions, and repeated description thereof will be omitted.

[0018] Also, in the drawings and the like, the position, size, range, etc. of each component shown may not represent the actual position, size, range, etc. in order to facilitate understanding of the invention. For this reason, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings and the like. For example, in an actual manufacturing process, a resist mask or the like may be unintentionally reduced in size due to a process such as etching, but it may not be reflected in the drawing for the sake of easy understanding.

[0019] Also, in the drawings and the like, for the sake of easy understanding of the description, the description of some components may be omitted.

[0020] Also, in this specification and the like, the terms "electrode" and "wiring" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where a plurality of "electrodes" and "wirings" are integrally formed.

[0021] Also, in this specification and the like, the "terminal" in an electric circuit refers to a part where current input or output, voltage input or output, or signal reception or transmission is performed. Therefore, a part of a wiring or an electrode may function as a terminal.

[0022] In addition, in this specification and the like, the terms "upper" and "lower" do not limit the positional relationship of components to be directly above or below and in direct contact. For example, in the expression "electrode B on insulating layer A", it is not necessary for electrode B to be formed in direct contact on insulating layer A, and those including other components between insulating layer A and electrode B are not excluded.

[0023] In addition, in this specification and the like, "electrically connected" includes both the case of direct connection and the case of connection via "something having some electrical effect". Here, "something having some electrical effect" is not particularly limited as long as it enables the transfer of electrical signals between the connection targets. Therefore, even when expressed as "electrically connect", in an actual circuit, there may be a case where there is no physical connection part and only wiring extends.

[0024] In addition, in this specification and the like, "parallel" means, for example, a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Also, "perpendicular" and "orthogonal" mean, for example, a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included.

[0025] In addition, in this specification and the like, regarding numerical values and measured values, or things, methods, and events that can be converted into numerical values or measured values, when using terms such as "identical", "the same", "equal", or "uniform", unless otherwise specified, they shall include an error of plus or minus 20%.

[0026] In addition, in this specification and the like, the terms "adjacent" and "proximate" do not limit the components to be in direct contact. For example, in the expression "electrode B adjacent to insulating layer A", it is not necessary for insulating layer A and electrode B to be formed in direct contact, and those including other components between insulating layer A and electrode B are not excluded.

[0027] In many cases, voltage indicates the potential difference between a certain potential and a reference potential (such as ground potential or source potential). Therefore, voltage and potential can often be used interchangeably. In this specification and the like, unless otherwise specified, voltage and potential can be used interchangeably.

[0028] Even when referred to as a "semiconductor", for example, when its conductivity is sufficiently low, it has the characteristics of an "insulator". Therefore, it is also possible to replace "semiconductor" with "insulator" and use it. In this case, the boundary between "semiconductor" and "insulator" is ambiguous, and it is difficult to strictly distinguish between the two. Therefore, the "semiconductor" and "insulator" described in this specification may be able to be read as each other in some cases.

[0029] Even when referred to as a "semiconductor", for example, when its conductivity is sufficiently high, it has the characteristics of a "conductor". Therefore, it is also possible to replace "semiconductor" with "conductor" and use it. In this case, the boundary between "semiconductor" and "conductor" is ambiguous, and it is difficult to strictly distinguish between the two. Therefore, the "semiconductor" and "conductor" described in this specification may be able to be read as each other in some cases.

[0030] In this specification and the like, a "resistive element" can be, for example, a circuit element, wiring, etc. having a resistance value higher than 0 Ω. Therefore, in this specification and the like, a "resistive element" includes wiring having a resistance value, a transistor through which current flows between source and drain, a diode, an inductor, etc. Therefore, the term "resistive element" can be replaced with terms such as "resistance", "load", "region having a resistance value", and conversely, terms such as "resistance", "load", "region having a resistance value" can be replaced with terms such as "resistive element". As the resistance value, for example, it can preferably be 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, still more preferably 10 mΩ or more and 1 Ω or less. Also, for example, it may be 1 Ω or more and 1×10 9 Ω or less.

[0031] In addition, in this specification and the like, the "capacitive element" can be, for example, a circuit element having a capacitance value higher than 0F, a wiring region having a capacitance value higher than 0F, a parasitic capacitance, a gate capacitance of a transistor, and the like. Therefore, in this specification and the like, the "capacitive element" includes not only a circuit element including a pair of electrodes and a dielectric contained between the electrodes, but also a parasitic capacitance generated between wirings, a gate capacitance generated between one of the source or drain of a transistor and the gate, and the like. Further, terms such as "capacitive element", "parasitic capacitance", and "gate capacitance" can be replaced with terms such as "capacitance", and conversely, the term "capacitance" can be replaced with terms such as "capacitive element", "parasitic capacitance", and "gate capacitance". In addition, the term "a pair of electrodes" of "capacitance" can be replaced with "a pair of conductors", "a pair of conductive regions", "a pair of regions", and the like. Note that the capacitance value can be, for example, 0.05 fF or more and 10 pF or less. Further, for example, it may be 1 pF or more and 10 μF or less.

[0032] Note that even when components that are independent on a circuit diagram are shown as being electrically connected, there may be a case where one component has the functions of a plurality of components. For example, when a part of a wiring also functions as an electrode, one conductive film has the functions of both a wiring component and an electrode component. Therefore, the electrically connected in this specification includes such a case where one conductive film has the functions of a plurality of components within its scope.

[0033] In addition, in this specification and the like, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as the source or the drain are the input / output terminals of the transistor. Which of the two input / output terminals becomes the source and which becomes the drain depends on the conductivity type (n-channel type, p-channel type) of the transistor and the levels of the potentials applied to the three terminals of the transistor.

[0034] Thus, since the functions of the source and the drain are interchangeable depending on operating conditions such as when transistors with different polarities are employed or when the direction of current changes in circuit operation, it is difficult to limit which one is the source or the drain. For this reason, in this specification, the terms "source" and "drain" are assumed to be interchangeable.

[0035] Also, in this specification and the like, when explaining the connection relationship of a transistor, notations such as "one of the source or the drain" (or the first electrode, or the first terminal), and "the other of the source or the drain" (or the second electrode, or the second terminal) are used. Note that depending on the structure of the transistor, in addition to the three terminals described above, there may be a back gate. In this case, in this specification and the like, one of the gate or the back gate of the transistor may be referred to as the first gate, and the other of the gate or the back gate of the transistor may be referred to as the second gate. Further, in the same transistor, the terms "gate" and "back gate" may be interchangeable. Also, when a transistor has three or more gates, in this specification and the like, each gate may be referred to as the first gate, the second gate, the third gate, and so on.

[0036] Also, in this specification and the like, the high power supply potential Vdd (hereinafter, also simply referred to as "Vdd", "potential H", or "H") indicates a power supply potential having a potential higher than the low power supply potential Vss (hereinafter, also simply referred to as "Vss", "potential L", or "L"). Also, Vss indicates a power supply potential having a potential lower than Vdd. Also, the ground potential (hereinafter, also simply referred to as "GND" or "GND potential") can be used as Vdd or Vss. For example, when Vdd is the ground potential, Vss is a potential lower than the ground potential, and when Vss is the ground potential, Vdd is a potential higher than the ground potential.

[0037] Also, unless otherwise specified, the transistors described in this specification and the like are enhancement-mode (normally-off) n-channel field-effect transistors. Therefore, their threshold voltage (also referred to as "Vth") is greater than 0V. Also, unless otherwise specified, "applying an H potential to the gate of the transistor" may be synonymous with "turning on the transistor." Also, unless otherwise specified, "applying an L potential to the gate of the transistor" may be synonymous with "turning off the transistor."

[0038] Also, in this specification and the like, the gate refers to a part or all of the gate electrode and the gate wiring. The gate wiring refers to the wiring for electrically connecting the gate electrode of at least one transistor to another electrode or another wiring.

[0039] Also, in this specification and the like, the source refers to a part or all of the source region, the source electrode, and the source wiring. The source region refers to a region in the semiconductor layer where the resistivity is below a certain value. The source electrode refers to the conductive layer connected to the source region. The source wiring refers to the wiring for electrically connecting the source electrode of at least one transistor to another electrode or another wiring.

[0040] Also, in this specification and the like, the drain refers to a part or all of the drain region, the drain electrode, and the drain wiring. The drain region refers to a region in the semiconductor layer where the resistivity is below a certain value. The drain electrode refers to the conductive layer connected to the drain region. The drain wiring refers to the wiring for electrically connecting the drain electrode of at least one transistor to another electrode or another wiring.

[0041] In addition, in drawings and the like, in order to make the potential of wirings, electrodes, conductors, etc. easier to understand, an "H" indicating the H potential or an "L" indicating the L potential may be appended adjacent to the wiring, electrode, conductor, etc. Further, when some circuits are stopped in function, an "X" symbol may be appended over the relevant circuit.

[0042] In addition, in this specification and the like, when the same reference signs are used for a plurality of elements, when it is particularly necessary to distinguish them, identification signs such as "a", "A", "_1", "_2", "[m,n]", etc. may be appended to the reference signs for description. For example, one of two wirings GL may be described as wiring GLa, and the other may be described as wiring GLb.

[0043] Note that ordinal numbers such as "first" and "second" in this specification and the like are appended to avoid confusion of components, and do not indicate any order or rank such as process order or lamination order. Also, even for terms without ordinal numbers in this specification and the like, ordinal numbers may be appended in the claims to avoid confusion of components. Further, even for terms with ordinal numbers in this specification and the like, different ordinal numbers may be appended in the claims. Also, even for terms with ordinal numbers in this specification and the like, ordinal numbers may be omitted in the claims and the like.

[0044] In addition, in this specification and the like, when it is described that X and Y are connected, it is assumed that the cases where X and Y are electrically connected, where X and Y are functionally connected, and where X and Y are directly connected are those disclosed in this specification and the like. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or the text, and those other than the connection relationship shown in the figure or the text are also assumed to be those disclosed in the figure or the text. It is assumed that X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0045] As an example of the case where X and Y are electrically connected, one or more elements that enable the electrical connection between X and Y (for example, a switch, transistor, capacitor, inductor, resistor, diode, display device, light-emitting device, load, etc.) can be connected between X and Y. Note that the switch has a function of controlling the on state and the off state. That is, the switch has a function of becoming a conductive state (on state) or a non-conductive state (off state) and controlling whether to allow current to flow or not.

[0046] As an example of the case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, a logic circuit (such as an inverter, NAND circuit, NOR circuit, etc.), a signal conversion circuit (such as a digital-analog conversion circuit, analog-digital conversion circuit, gamma correction circuit, etc.), a potential level conversion circuit (such as a power supply circuit (step-up circuit, step-down circuit, etc.), a level shifter circuit that changes the potential level of a signal, etc.), a voltage source, a current source, a switching circuit, an amplification circuit (a circuit that can increase the signal amplitude or current amount, etc., such as an operational amplifier, differential amplification circuit, source follower circuit, buffer circuit, etc.), a signal generation circuit, a memory circuit, a control circuit, etc.) can be connected between X and Y. Note that, as an example, even if another circuit is interposed between X and Y, if the signal output from X is transmitted to Y, it is considered that X and Y are functionally connected.

[0047] Note that when it is explicitly described that X and Y are electrically connected, it includes the case where X and Y are electrically connected (that is, the case where they are connected with another element or another circuit interposed between X and Y) and the case where X and Y are directly connected (that is, the case where they are connected without another element or another circuit interposed between X and Y).

[0048] Also, for example, it can be expressed as "X, Y, the source (or the first terminal, etc.) of the transistor, and the drain (or the second terminal, etc.) of the transistor are electrically connected to each other, and they are electrically connected in the order of X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y." Or, it can be expressed as "The source (or the first terminal, etc.) of the transistor is electrically connected to X, the drain (or the second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as "X is electrically connected to Y through the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y are provided in this connection order." By stipulating the connection order in the circuit configuration using an expression method similar to these examples, the source (or the first terminal, etc.) of the transistor and the drain (or the second terminal, etc.) of the transistor can be distinguished to determine the technical scope. Note that these expression methods are just examples and are not limited to these expression methods. Here, it is assumed that X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0049] In addition, in this specification and the like, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as the source or the drain are the input / output terminals of the transistor. Depending on the conduction type of the transistor (n-channel type, p-channel type) and the levels of the potentials applied to the three terminals of the transistor, one of the two input / output terminals becomes the source and the other becomes the drain. Therefore, in this specification and the like, the terms source and drain are considered to be interchangeable with each other. Further, in this specification and the like, when explaining the connection relationship of the transistor, notations such as "one of the source or the drain" (or the first electrode, or the first terminal), "the other of the source or the drain" (or the second electrode, or the second terminal) are used. Note that depending on the structure of the transistor, in addition to the three terminals described above, there may be a back gate. In this case, in this specification and the like, one of the gate or the back gate of the transistor may be referred to as the first gate, and the other of the gate or the back gate of the transistor may be referred to as the second gate. Further, in the same transistor, the terms "gate" and "back gate" may be interchangeable with each other. Also, when the transistor has three or more gates, in this specification and the like, each gate may be referred to as the first gate, the second gate, the third gate, and so on.

[0050] In addition, in this specification and the like, the "on state" of a transistor refers to a state in which the source and the drain of the transistor can be considered to be electrically short-circuited (also referred to as the "conducting state"). Further, the "off state" of a transistor refers to a state in which the source and the drain of the transistor can be considered to be electrically interrupted (also referred to as the "non-conducting state").

[0051] In addition, in this specification and the like, the "on current" may refer to the current flowing between the source and the drain when the transistor is in the on state. Further, the "off current" may refer to the current flowing between the source and the drain when the transistor is in the off state.

[0052] In addition, in this specification and the like, "node" can be rephrased as a terminal, wiring, electrode, conductive layer, conductor, impurity region, etc., according to the circuit configuration or device structure, etc. Further, it is possible to rephrase a terminal, wiring, etc. as a node.

[0053] In addition, in this specification and the like, "voltage" and "electric potential" can be rephrased as appropriate. "Voltage" is the potential difference from a reference potential. For example, if the reference potential is the ground potential (earthing potential), "voltage" can be rephrased as "electric potential". Note that the ground potential does not necessarily mean 0V. Also, electric potential is relative, and when the reference potential changes, the potential applied to the wiring, the potential applied to a circuit, etc., and the potential output from a circuit, etc. also change.

[0054] "Current" refers to the phenomenon of charge movement (electrical conduction). For example, the description "electrical conduction of a positive charge carrier is occurring" can be rephrased as "electrical conduction of a negative charge carrier is occurring in the opposite direction". Therefore, in this specification and the like, "current" shall refer to the phenomenon of charge movement (electrical conduction) associated with the movement of carriers, unless otherwise specified. The carriers referred to here include electrons, holes, anions, cations, complex ions, etc., and the carriers vary depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, vacuum, etc.). Also, the "direction of current" in wiring, etc. is defined as the direction in which positive carriers move, and is described with a positive current amount. In other words, the direction in which negative carriers move is the opposite direction to the direction of current, and is expressed with a negative current amount. Therefore, in this specification and the like, when there is no specification regarding the positive or negative of the current (or the direction of the current), descriptions such as "current flows from element A to element B" can be rephrased as "current flows from element B to element A", etc. Also, descriptions such as "current is input to element A" can be rephrased as "current is output from element A", etc.

[0055] In addition, in this specification and the like, ordinal numbers such as "first", "second", and "third" are attached to avoid confusion of components. Therefore, they do not limit the number of components, nor do they limit the order of components. For example, in one of the embodiments of this specification and the like, the component referred to as "first" may be the component referred to as "second" in other embodiments or in the claims. Also, for example, in one of the embodiments of this specification and the like, the component referred to as "first" may be omitted in other embodiments or in the claims.

[0056] In addition, the terms "upper" and "lower" do not limit that the positional relationship of components is directly above or directly below and in direct contact. For example, in the expression "electrode B on insulating layer A", it is not necessary that electrode B is directly formed on insulating layer A, and those including other components between insulating layer A and electrode B are not excluded.

[0057] In addition, the positional relationship of components changes appropriately according to the direction of depicting each component. Therefore, it is not limited to the phrases described in the specification and the like, and can be appropriately rephrased according to the situation. For example, in this specification and the like, phrases indicating arrangements such as "above" and "below" may be used for convenience in explaining the positional relationship of components with reference to the drawings. Therefore, in the expression "insulator located on the upper surface of the conductor", by rotating the direction of the shown drawing by 180 degrees, it can be rephrased as "insulator located on the lower surface of the conductor". Also, in the expression "insulator located on the upper surface of the conductor", by rotating the direction of the shown drawing by 90 degrees, it can be rephrased as "insulator located on the left surface (or right surface) of the conductor".

[0058] Similarly, in this specification and the like, terms such as "overlap" do not limit the state such as the stacking order of components. For example, in the expression "electrode B overlapping insulating layer A", it is not limited to the state where "electrode B is formed on insulating layer A", and states such as "electrode B is formed under insulating layer A" or "electrode B is formed on the right side (or left side) of insulating layer A" are not excluded.

[0059] Also, in this specification and the like, terms such as "film" and "layer" can be interchanged with each other according to the situation. For example, the term "conductive layer" may be changed to the term "conductive film". Or, for example, the term "insulating film" may be changed to the term "insulating layer". Or, in some cases, or according to the situation, it is possible to replace the terms such as "film" and "layer" with other terms without using them. For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor". Or, for example, the terms "insulating layer" and "insulating film" may be changed to the term "insulator".

[0060] Also, in this specification and the like, terms such as "electrode", "wiring", and "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where a plurality of "electrodes" and "wirings" are integrally formed. Also, for example, a "terminal" may be used as part of "wiring" or "electrode", and vice versa. Furthermore, the term "terminal" also includes cases where a plurality of "electrodes", "wirings", "terminals", etc. are integrally formed. Therefore, for example, an "electrode" can be part of "wiring" or "terminal", and, for example, a "terminal" can be part of "wiring" or "electrode". Also, terms such as "electrode", "wiring", "terminal", etc. may be replaced with terms such as "region" in some cases.

[0061] In addition, in this specification and the like, terms such as "wiring", "signal line", and "power supply line" can be interchanged with each other depending on the case or situation. For example, the term "wiring" may be changed to the term "signal line". Also, for example, the term "wiring" may be changed to terms such as "power supply line". Conversely, terms such as "signal line" and "power supply line" may be changed to the term "wiring". Terms such as "power supply line" may be changed to terms such as "signal line". Conversely, terms such as "signal line" may be changed to terms such as "power supply line". Also, the term "potential" applied to the wiring may be changed to terms such as "signal" depending on the case or situation. Conversely, terms such as "signal" may be changed to the term "potential".

[0062] In this specification and the like, the impurities in a semiconductor refer to, for example, components other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic% is an impurity. When impurities are contained, for example, the density of defect levels in the semiconductor may increase, the carrier mobility may decrease, and / or the crystallinity may decrease. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, transition metals other than the main components, etc. In particular, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. Specifically, when the semiconductor is silicon, impurities that change the characteristics of the semiconductor include, for example, oxygen, Group 1 elements excluding hydrogen, Group 2 elements, Group 13 elements, Group 15 elements, etc.

[0063] In this specification and the like, a switch refers to a device that can be in a conductive state (on state) or a non-conductive state (off state) and has a function of controlling whether or not to allow current to flow. Alternatively, a switch refers to a device that has a function of selecting and switching a path for current to flow. As an example, an electrical switch, a mechanical switch, etc. can be used. That is, the switch only needs to be able to control current and is not limited to a specific type.

[0064] As an example of an electrical switch, there are transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), or logic circuits combining these. When using a transistor as a switch, the "conductive state" of the transistor refers to a state where the source electrode and the drain electrode of the transistor can be regarded as being electrically short-circuited. Also, the "non-conductive state" of the transistor refers to a state where the source electrode and the drain electrode of the transistor can be regarded as being electrically disconnected. When operating a transistor simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0065] As an example of a mechanical switch, there is a switch using MEMS (Micro-Electro-Mechanical Systems) technology. The switch has electrodes that can be mechanically moved, and by moving the electrodes, it controls conduction and non-conduction to operate.

[0066] In this specification, "parallel" means a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Further, "substantially parallel" or "approximately parallel" means a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Also, "perpendicular" means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. Further, "substantially perpendicular" or "approximately perpendicular" means a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0067] In this specification or the like, when referring to numerical values and measured values, or things or methods convertible to numerical values or measured values, the terms "identical", "the same", "equal", or "uniform" etc. shall include an error of plus or minus 20% unless otherwise specified.

[0068] In this specification etc., a metal oxide is an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS), etc. For example, when a metal oxide is used for the active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide can constitute a channel formation region of a transistor having at least one of an amplification action, a rectification action, and a switching action, the metal oxide can be referred to as a metal oxide semiconductor. Also, when described as an "OS transistor", it can be paraphrased as a transistor having a metal oxide or an oxide semiconductor.

[0069] In this specification etc., a metal oxide having nitrogen may also be collectively referred to as a metal oxide. Also, a metal oxide having nitrogen may be referred to as a metal oxynitride.

[0070] In addition, in this specification and the like, the configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form an aspect of the present invention. Further, when a plurality of configuration examples are shown in one embodiment, it is possible to appropriately combine the configuration examples with each other.

[0071] Note that the content described in one embodiment (even a part of the content) can be applied to, combined with, or replaced with at least one of the content described in another part of the same embodiment (even a part of the content) and the content described in one or more other embodiments (even a part of the content).

[0072] Note that the content described in the embodiments refers to the content described using various figures or the text described in the specification in each embodiment (or example).

[0073] Note that the figure (even a part of it) described in one embodiment can be combined with at least one of another part of the figure, another figure (even a part of it) described in the same embodiment, and the figure (even a part of it) described in one or more other embodiments to form more figures.

[0074] The embodiments described in this specification will be described with reference to the drawings. However, it is easily understood by those skilled in the art that the embodiments can be implemented in many different ways and that the form and details can be variously changed without departing from the spirit and scope thereof. Therefore, the present invention is not to be construed as being limited to the content described in the embodiments. In the configuration of the invention of the embodiments, the same reference numerals are commonly used among different drawings for the same part or parts having the same or similar functions, and the repeated description thereof may be omitted. Also, for ease of understanding the drawings, in perspective views or top views, etc., the description of some components may be omitted.

[0075] In this specification and the like, in the block diagram, components are classified by function and shown as independent blocks. However, in an actual circuit or the like, it is difficult to separate components by function, and there may be cases where a single circuit is related to multiple functions or a single function is related to multiple circuits. Therefore, the blocks in the block diagram are not limited to the components described in the specification and can be appropriately rephrased according to the situation.

[0076] Also, in drawings and the like, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to its size, aspect ratio, etc. The drawings schematically show ideal examples and are not limited to the shapes or values shown in the drawings. For example, it can include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations.

[0077] (Embodiment 1) The AD conversion device (analog-to-digital conversion device) 100 according to one aspect of the present invention will be described with reference to the drawings.

[0078] <Configuration example of the AD conversion device 100> FIG. 1 shows a block diagram of the AD conversion device 100. The AD conversion device 100 includes a comparison unit 110, a control unit 120, a DA conversion unit (digital-to-analog conversion unit) 130a, and a DA conversion unit 130b. Also, a wiring 101a is electrically connected to an input terminal 111a of the comparison unit 110, and a wiring 101b is electrically connected to an input terminal 111b of the comparison unit 110.

[0079] The comparison unit 110 has a function of comparing the value of the current flowing through the input terminal 111a with the value of the current flowing through the input terminal 111b and supplying one of the two potentials to the output terminal D. For example, consider a case where a current Ia flows through the input terminal 111a via the wiring 101a and a current Ib flows through the input terminal 111b via the wiring 101b. When the current value of the current Ia exceeds the current value of the current Ib, the comparison unit 110 supplies the potential H to the output terminal D as an output. Also, when the current value of the current Ia is less than or equal to the current value of the current Ib, the comparison unit 110 supplies the potential L to the output terminal D as an output. Further, the output of the comparison unit 110 is input to the control unit 120 via the output terminal D.

[0080] The control unit 120 includes a sign generation unit 121 and a digital signal generation unit 122. The sign generation unit 121 has a function of generating a 1-bit sign bit according to the output of the comparison unit 110. For example, when the output of the comparison unit 110 is the potential H, “0” is generated as the sign bit. Also, when the output of the comparison unit 110 is the potential L, “1” is generated as the sign bit. Note that the sign bit may be “1” when the output of the comparison unit 110 is the potential H and “0” when the potential is L.

[0081] The digital signal generation unit 122 has a function of generating a digital signal that is a digital value with a resolution of 8 bits or more and 16 bits or less. When the resolution is small, the AD conversion accuracy is low, but the AD conversion speed can be increased. When the resolution is large, the AD conversion accuracy is high, but the AD conversion speed is slow. Note that the resolution of the digital signal generation unit 122 is not limited to 8 bits or more and 16 bits or less. The resolution of the digital signal generation unit 122 may be 7 bits or less, or 17 bits or more. The resolution may be appropriately determined according to the purpose and application.

[0082] In the present embodiment, it is assumed that the digital signal generation unit 122 generates a digital signal with a resolution of 8 bits. Note that in this specification and the like, each digit of a digital signal represented by a binary number may be referred to as a “bit”.

[0083] The control unit 120 has a function of supplying the digital signal generated by the digital signal generation unit 122 to the DA conversion unit 130 (DA conversion unit 130a and / or DA conversion unit 130b). Further, the control unit 120 has a function of externally outputting (OUT) a signal obtained by adding a sign bit to the digital signal. When the resolution of the digital signal is 8 bits, a 9-bit signed digital signal obtained by adding 1 bit of the sign bit can be externally output. Further, the control unit 120 functions as a successive approximation register (SAR).

[0084] The DA conversion unit 130 functions as a current output type DAC (Digital to Analog Converter). That is, the DA conversion unit 130 has a function of outputting a current having a value corresponding to the digital signal supplied from the control unit 120 to the output terminal C (output terminal Ca and / or output terminal Cb).

[0085] In FIG. 1, the output terminal Ca of the DA conversion unit 130a is electrically connected to the input terminal 111a of the comparison unit 110 via the node NDa. Therefore, the output current of the DA conversion unit 130a is added to the input terminal 111a of the comparison unit 110. That is, the current Ia and the output current of the DA conversion unit 130a flow through the input terminal 111a. In other words, a current obtained by adding the output current of the DA conversion unit 130a to the current Ia flows through the input terminal 111a.

[0086] Also, in FIG. 1, the output terminal Cb of the DA conversion unit 130b is electrically connected to the input terminal 111b of the comparison unit 110 via the node NDb. Therefore, the output current of the DA conversion unit 130b is added to the input terminal 111b of the comparison unit 110. That is, the current Ib and the output current of the DA conversion unit 130b flow through the input terminal 111b. In other words, a current obtained by adding the output current of the DA conversion unit 130b to the current Ib flows through the input terminal 111b.

[0087] Note that node NDa is a node to which the output section of DA conversion section 130a, wiring 101a, and input terminal 111a are electrically connected. Also, node NDb is a node to which the output section of DA conversion section 130b, wiring 101b, and input terminal 111b are electrically connected.

[0088] <Operation example of AD conversion device 100> FIG. 2 is a flowchart for explaining an operation example of the AD conversion device 100. In the present embodiment, the resolution of the digital signal generated by the digital signal generation section 122 is set to 8 bits, and the step of the output current of the DA conversion section 130 is set to 1 nA. Here, an operation of converting the difference value between current Ia and current Ib (also referred to as "differential current") into a digital signal with a sign bit will be described.

[0089] [Step S201] Perform a reset operation of the control section 120. Specifically, set an 8-bit digital signal to (00000000)2. Also, supply the digital signal to the DA conversion section 130a and the DA conversion section 130b. Thus, the outputs of the DA conversion section 130a and the DA conversion section 130b stop.

[0090] [Step S202] Compare the current value of current Ia and the current value of current Ib by the comparison section 110. In the present embodiment, when the current value of current Ia is greater than the current value of current Ib (Yes), the comparison section 110 supplies a potential H to the output terminal D. Also, when the current value of current Ia is less than or equal to the current value of current Ib (No), the comparison section 110 supplies a potential L to the output terminal D.

[0091] [Step S203a] When the comparison section 110 outputs a potential H in step S202, set "0" in the sign bit.

[0092] [Step S204a] When the sign bit is "0", successive approximation (SA) is performed using the DA conversion unit 130b. During the SA period, keep supplying (00000000)₂ to the DA conversion unit 130a as a digital signal. Alternatively, the power supply to the DA conversion unit 130a may be stopped. By stopping the power supply to the DA conversion unit 130a, the power consumption can be reduced. Note that the operation of SA will be described later.

[0093] [Step S203b] When the comparison unit 110 outputs a potential L in step S202, set "1" in the sign bit.

[0094] [Step S204b] When the sign bit is "1", SA is performed using the DA conversion unit 130a. During the SA period, keep supplying (00000000)₂ to the DA conversion unit 130b as a digital signal. Alternatively, the power supply to the DA conversion unit 130b may be stopped. By stopping the power supply to the DA conversion unit 130b, the power consumption can be reduced.

[0095] [Step S205] After the end of step S204a or step S204b, combine the obtained digital signal and the sign bit to generate a signed digital signal. The sign bit may be the most significant bit or the least significant bit of the signed digital signal.

[0096] For example, when the sign bit is "1" and the digital signal obtained by SA is (01001011)₂, the signed digital signal may be (101001011)₂ using the sign bit as the most significant bit (MSB: Most Significant Bit). Also, the signed digital signal may be (010010111)₂ using the sign bit as the least significant bit (LSB: Least Significant Bit).

[0097] [Step S206] Output the generated digital signal with a sign externally. When the sign bit "0" is positive and the sign bit "1" is negative, the AD conversion device 100 according to one aspect of the present invention can output a positive digital signal or a negative digital signal. Alternatively, the AD conversion device 100 according to one aspect of the present invention can output the magnitude relationship between the current Ia and the current Ib and the absolute value of the differential current between the two as a digital signal.

[0098] <Sequential comparison operation example> Using FIG. 3, the sequential comparison operation corresponding to step S204b will be described. FIG. 3 shows the states of the current Ia, the current Ib, the output terminal D, and each digit (Q0 bit to Q7 bit) of the digital signal in periods T1 to T8. As described above, the resolution of the digital signal generated by the digital signal generation unit 122 is set to 8 bits, and the step of the output current of the DA conversion unit 130 is set to 1 nA. Here, the case where the current Ia is 75 nA and the current Ib is 150 nA will be described. Note that the potential of the output terminal D before the sequential comparison operation (initial state) is the potential L. Also, the digital signal in the initial state is (00000000)2.

[0099] [Period T1] In period T1, set the Q7 bit, which is the MSB of the digital signal, to "1". That is, generate the digital signal (10000000)2. This digital signal is input to the DA conversion unit 130a, and 128 nA is output from the DA conversion unit 130a. The output is supplied to the input terminal 111a via the node NDa. Therefore, a current of 203 nA (75 + 128 nA) flows through the input terminal 111a. Since 150 nA flows through the input terminal 111b, the potential of the output terminal D becomes the potential H.

[0100] When the potential of the output terminal D changes from the potential in the initial state in period T1, set the Q7 bit to "0" until the control unit 120 is reset after period T1. When the potential of the output terminal D does not change from the potential in the initial state, set the Q7 bit to "1" until the control unit 120 is reset after period T1. In the present embodiment, after period T1, the Q7 bit is "0".

[0101] [Period T2] During period T2, set the Q6 bit, which is 1 bit below the MSB of the digital signal, to "1". That is, generate the digital signal (01000000)₂. This digital signal is input to the DA conversion unit 130a, and 64 nA is output from the DA conversion unit 130a. This output is supplied to the input terminal 111a via the node NDa. Therefore, a current of 139 nA (75 + 64 nA) flows through the input terminal 111a, and the potential of the output terminal D is the same potential L as the initial state.

[0102] If the potential of the output terminal D changes from the potential of the initial state during period T2, then after period T2, set the Q6 bit to "0" until the control unit 120 is reset. If the potential of the output terminal D does not change from the potential of the initial state, then after period T2, set the Q6 bit to "1" until the control unit 120 is reset. In this embodiment, after period T2, the Q6 bit is "1".

[0103] [Period T3] During period T3, set the Q5 bit, which is 2 bits below the MSB of the digital signal, to "1". That is, generate the digital signal (01100000)₂. This digital signal is input to the DA conversion unit 130a, and 96 nA (64 + 32 nA) is output from the DA conversion unit 130a. This output is supplied to the input terminal 111a via the node NDa. Therefore, a current of 171 nA (75 + 64 + 32 nA) flows through the input terminal 111a, and the potential of the output terminal D becomes potential H.

[0104] If the potential of the output terminal D changes from the potential of the initial state during period T3, then after period T3, set the Q5 bit to "0" until the control unit 120 is reset. If the potential of the output terminal D does not change from the potential of the initial state, then after period T3, set the Q5 bit to "1" until the control unit 120 is reset. In this embodiment, after period T3, the Q5 bit is "0".

[0105] [Period T4] During period T4, set the Q4 bit, which is 3 bits below the MSB of the digital signal, to "1". That is, generate the digital signal (01010000)₂. This digital signal is input to the DA conversion unit 130a, and 80 nA (64 + 16 nA) is output from the DA conversion unit 130a. This output is supplied to the input terminal 111a via the node NDa. Therefore, a current of 155 nA (75 + 64 + 16 nA) flows through the input terminal 111a, and the potential of the output terminal D becomes potential H.

[0106] When the potential of the output terminal D changes from the potential in the initial state during period T4, the Q4 bit is set to "0" after period T4 until the control unit 120 is reset. When the potential of the output terminal D does not change from the potential in the initial state, the Q4 bit is set to "1" after period T4 until the control unit 120 is reset. In this embodiment, the Q4 bit is "0" after period T4.

[0107] [Period T5] During period T5, set the Q3 bit, which is 4 bits below the MSB of the digital signal, to "1". That is, generate the digital signal (01001000)₂. This digital signal is input to the DA conversion unit 130a, and 72 nA (64 + 8 nA) is output from the DA conversion unit 130a. This output is supplied to the input terminal 111a via the node NDa. Therefore, a current of 147 nA (75 + 64 + 8 nA) flows through the input terminal 111a, and the potential of the output terminal D becomes potential L.

[0108] When the potential of the output terminal D changes from the potential in the initial state during period T5, the Q3 bit is set to "0" after period T5 until the control unit 120 is reset. When the potential of the output terminal D does not change from the potential in the initial state, the Q3 bit is set to "1" after period T5 until the control unit 120 is reset. In this embodiment, the Q3 bit is "1" after period T5.

[0109] [Period T6] During period T6, set the Q2 bit, which is 5 bits below the MSB of the digital signal, to "1". That is, generate the digital signal (01001100)₂. This digital signal is input to the DA conversion unit 130a, and 76 nA (64 + 8 + 4 nA) is output from the DA conversion unit 130a. This output is supplied to the input terminal 111a via the node NDa. Therefore, a current of 151 nA (75 + 64 + 8 + 4 nA) flows through the input terminal 111a, and the potential of the output terminal D becomes potential H.

[0110] When the potential of the output terminal D changes from the potential in the initial state during period T6, after period T6, set the Q2 bit to "0" until the control unit 120 is reset. When the potential of the output terminal D does not change from the potential in the initial state, after period T6, set the Q2 bit to "1" until the control unit 120 is reset. In this embodiment, after period T6, the Q2 bit is "0".

[0111] [Period T7] During period T7, set the Q1 bit, which is 6 bits below the MSB of the digital signal, to "1". That is, generate the digital signal (01001010)₂. This digital signal is input to the DA conversion unit 130a, and 74 nA (64 + 8 + 2 nA) is output from the DA conversion unit 130a. This output is supplied to the input terminal 111a via the node NDa. Therefore, a current of 149 nA (75 + 64 + 8 + 2 nA) flows through the input terminal 111a, and the potential of the output terminal D becomes potential L.

[0112] When the potential of the output terminal D changes from the potential in the initial state during period T7, after period T7, set the Q1 bit to "0" until the control unit 120 is reset. When the potential of the output terminal D does not change from the potential in the initial state, after period T7, set the Q1 bit to "1" until the control unit 120 is reset. In this embodiment, after period T7, the Q1 bit is "1".

[0113] [Period T8] During period T8, set the Q0 bit, which is the LSB of the digital signal, to "1". That is, generate the digital signal (01001011)₂. This digital signal is input to the DA conversion unit 130a, and 75 nA (64 + 8 + 2 + 1 nA) is output from the DA conversion unit 130a. This output is supplied to the input terminal 111a via the node NDa. Therefore, a current of 150 nA (75 + 64 + 8 + 2 + 1 nA) flows through the input terminal 111a, and the potential of the output terminal D becomes the potential L.

[0114] If the potential of the output terminal D changes from the potential in the initial state during period T8, then after period T8, set the Q0 bit to "0" until the control unit 120 is reset. If the potential of the output terminal D does not change from the potential in the initial state, then after period T8, set the Q0 bit to "1" until the control unit 120 is reset. In this embodiment, after period T8, the Q0 bit is "1".

[0115] In this way, by comparing in order from the MSB to the LSB, the differential current of 75 nA, which is the difference between the current Ia and the current Ib, can be converted into the digital signal (01001011)₂.

[0116] Regarding the successive comparison operation corresponding to step S204a, it can be understood by replacing the potential H with the potential L and replacing the DA conversion unit 130a with the DA conversion unit 130b in the above description.

[0117] Also, in this embodiment, since the step of the output current of the DA conversion unit 130 is set to 1 nA, a differential current up to a maximum of 255 nA can be converted into a digital signal. By increasing the step of the output current of the DA conversion unit 130, it is possible to handle a larger differential current. For example, by setting the step of the output current of the DA conversion unit 130 to 2 nA, a differential current up to a maximum of 510 nA can be converted into a digital signal.

[0118] Also, by increasing the resolution of the digital signal, or decreasing the step of the output current of the DA conversion unit 130, or doing both, more precise AD conversion can be realized.

[0119] Note that, for example, there is also a method of converting the differential current between current Ia and current Ib into a digital signal using the AD conversion device 190 shown in FIG. 4. The AD conversion device 190 shown in FIG. 4 has a function of converting current Ia into a voltage by an operational amplifier OPa and then converting it into an output OUTa of a digital signal by an AD conversion unit ADCa, and a function of converting current Ib into a voltage by an operational amplifier OPb and then converting it into an output OUTb of a digital signal by an AD conversion unit ADCb. The output OUTa and the output OUTb can be calculated by the calculation unit 195 to obtain the difference between the two.

[0120] Current Ia is supplied to the inverting input of operational amplifier OPa, and a reference voltage Vref is supplied to the non-inverting input of operational amplifier OPa. The output and the non-inverting input of operational amplifier OPa are electrically connected via resistor Ra. Also, current Ib is supplied to the inverting input of operational amplifier OPb, and a reference voltage Vref is supplied to the non-inverting input of operational amplifier OPb. The output and the non-inverting input of operational amplifier OPb are electrically connected via resistor Rb.

[0121] If the resolution of both the AD conversion unit ADCa and the AD conversion unit ADCb provided in the AD conversion device 190 is 8 bits and the current value per bit is 1 nA, for currents Ia and Ib exceeding 255 nA, both the output OUTa and the output OUTb will be (11111111)2. Therefore, for example, when current Ia is 300 nA and current Ib is 261 nA, the output of the AD conversion device 190 will be 0.

[0122] Both the AD conversion device 100 and the AD conversion device 190 are equipped with a function of converting the differential current into a digital signal. In particular, the AD conversion device 100 can accurately convert the differential current between the two into a digital signal even when the current values of current Ia and current Ib are large.

[0123] <Configuration example of the comparison unit 110> As described above, the comparison unit 110 has a function of comparing the current value supplied to the input terminal 111a with the current value supplied to the input terminal 111b and supplying one of the two potentials to the output terminal D. The comparison unit 110 functions as a current comparison type comparator. FIG. 5A shows an example of a circuit configuration applicable to the comparison unit 110.

[0124] The comparison unit 110 shown in FIG. 5A includes transistors M11a, M11b, M11c, M11d, M12a, M12b, M12c, M12d, M13a, M13b, M14a, M14b, M15a, M15b, M16a, M16b, M17a, and transistor M17b. Also, the comparison unit 110 shown in FIG. 5A includes an inverter INVa and an inverter INVb.

[0125] Also, the comparison unit 110 shown in FIG. 5A includes an output terminal DB. The other potential of the two potentials is supplied to the output terminal DB. That is, when the potential H is supplied to the output terminal D, the potential L is supplied to the output terminal DB. Also, when the potential L is supplied to the output terminal D, the potential H is supplied to the output terminal DB.

[0126] It is sufficient if at least one of the output terminal D and the output terminal DB exists. For example, if the output terminal DB is unnecessary, the output terminal DB may not be provided. Or, if the output terminal DB is unnecessary, the output terminal DB and the inverter INVb may not be provided.

[0127] Transistors M11a, M11b, M11c, M11d, M12a, M12b, M12c, M12d, M14a, and M14b are p-channel transistors. Also, transistors M13a, M13b, M15a, M15b, M16a, M16b, M17a, and M17b are n-channel transistors.

[0128] One of the source or drain of transistor M11a is electrically connected to terminal 112, and the other is electrically connected to one of the source or drain of transistor M12a. The other of the source or drain of transistor M12a, the gate of transistor M11a, and the gate of transistor M11b are electrically connected to input terminal 111a. The gate of transistor M12a and the gate of transistor M12b are electrically connected to terminal 113.

[0129] One of the source or drain of transistor M11b is electrically connected to terminal 112, and the other is electrically connected to one of the source or drain of transistor M12b. One of the source or drain of transistor M13a is electrically connected to terminal 112, and the other is electrically connected to the other of the source or drain of transistor M12b.

[0130] The gate of transistor M13a and the gate of transistor M13b are electrically connected to terminal 114.

[0131] One of the source or drain of transistor M11c is electrically connected to terminal 112, and the other is electrically connected to one of the source or drain of transistor M12c. The other of the source or drain of transistor M12c, the gate of transistor M11c, and the gate of transistor M11d are electrically connected to input terminal 111b. The gate of transistor M12c and the gate of transistor M12d are electrically connected to terminal 113.

[0132] One of the source or drain of transistor M11d is electrically connected to terminal 112, and the other is electrically connected to one of the source or drain of transistor M12d. One of the source or drain of transistor M13b is electrically connected to terminal 112, and the other is electrically connected to the other of the source or drain of transistor M12d.

[0133] One of the source or drain of transistor M14a is electrically connected to the other of the source or drain of transistor M13a, and the other is electrically connected to one of the source or drain of transistor M15a. The other of the source or drain of transistor M15a is electrically connected to terminal 117. The gates of transistor M14a and transistor M15a are electrically connected to one of the source or drain of transistor M16b and the input of inverter INVb. The output of inverter INVb is electrically connected to output terminal DB. The other of the source or drain of transistor M16b is electrically connected to terminal 117.

[0134] One of the source or drain of transistor M17b is electrically connected to one of the source or drain of transistor M14b, and the other is electrically connected to terminal 117. The gates of transistor M16b and transistor M17b are electrically connected to terminal 116.

[0135] One of the source or drain of transistor M14b is electrically connected to the other of the source or drain of transistor M13b, and the other is electrically connected to one of the source or drain of transistor M15b. The other of the source or drain of transistor M15b is electrically connected to terminal 117. The gates of transistor M14b and transistor M15b are electrically connected to one of the source or drain of transistor M16a and the input of inverter INVa. The output of inverter INVa is electrically connected to output terminal D. The other of the source or drain of transistor M16a is electrically connected to terminal 117.

[0136] One of the source or drain of transistor M17a is electrically connected to one of the source or drain of transistor M14a, and the other is electrically connected to terminal 117. The gates of transistor M16a and transistor M17a are electrically connected to terminal 115.

[0137] Vdd is supplied to terminal 112, and Vss is supplied to terminal 117. Also, the potential of terminal 117 may be set to GND.

[0138] The first control signal Sig1 is supplied to terminal 113, the second control signal Sig2 is supplied to terminal 114, and the third control signal Sig3 is supplied to terminals 115 and 116. FIG. 5B shows the potential changes of terminals 113 to 116.

[0139] The comparison unit 110 shown in FIG. 5A compares the current values of the current Ia flowing through the input terminal 111a and the current Ib flowing through the input terminal 111b during the period Tw when the first control signal Sig1 and the third control signal Sig3 are at the potential L and the second control signal Sig2 is at the potential H, and outputs the comparison result to the output terminal D and the output terminal DB.

[0140] Since the comparison unit 110 shown in FIG. 5A is a comparator that operates when the first to third control signals are in the aforementioned combination, the power consumption can be reduced compared to a constantly operating comparator. Also, since the input current can be converted into a digital signal without converting it into a voltage, reduction of power consumption and occupied area can be achieved. Therefore, an AD conversion device 100 with reduced power consumption can be realized. Also, an AD conversion device 100 with reduced occupied area can be realized.

[0141] Also, in the circuit configuration of the comparison unit 110 shown in FIG. 5A, p-channel transistors may be used for the transistor M13a and the transistor M13b. However, it is preferable to use n-channel transistors for the transistor M13a and the transistor M13b.

[0142] For example, when Vdd is 3.3V and Vss is 0V, if p-channel transistors are used for the transistor M13a and the transistor M13b, it is necessary to set the potential H supplied to the terminal 114 to 3.3V (Vdd) and the potential L to approximately 2.8V. When n-channel transistors are used for the transistor M13a and the transistor M13b, the potential H supplied to the terminal 114 can be set to 1.2V and the potential L to 0V (Vss). Therefore, by using n-channel transistors for the transistor M13a and the transistor M13b, the potential required for circuit operation can be lowered. That is, the power consumption can be reduced.

[0143] Also, when 2.8V is used for circuit operation, it is necessary to newly provide a power supply. On the other hand, since 1.2V is a potential used as the power supply potential of a general semiconductor device, it is suitable because there is no need to newly provide a power supply.

[0144] <Configuration Example of DA Conversion Unit 130> FIG. 6A is a block diagram showing a configuration example of the DA conversion unit 130. The DA conversion unit 130 has a switch SWW. The first terminal of the switch SWW is electrically connected to the output terminal C, and the second terminal of the switch SWW is electrically connected to the wiring VINIL1. The wiring VINIL1 functions as a wiring for applying an initialization potential to the output terminal C, and the initialization potential can be GND, Vss, Vdd, or the like. Note that the switch SWW is turned on only when applying an initialization potential to the output terminal C, and is turned off otherwise.

[0145] As the switch SWW, for example, an electrical switch such as an analog switch or a transistor, or a mechanical switch such as MEMS can be used.

[0146] Also, the DA conversion unit 130 shown in FIG. 6A has a current mirror circuit CM. The current mirror circuit CM has a transistor Q1 and a transistor Q2. The first terminal of the transistor Q1 is electrically connected to the terminal Qin and the gate of the transistor Q1. Vss or GND is supplied to the second terminal of the transistor Q1. The first terminal of the transistor Q2 is electrically connected to the terminal Qout. Vss or GND is supplied to the second terminal of the transistor Q2. The gate of the transistor Q2 is electrically connected to the gate of the transistor Q1.

[0147] Also, the DA conversion unit 130 shown in FIG. 6A has a plurality of current sources CS. Specifically, the DA conversion unit 130 has a function of outputting the first data of K bits (2 K value) (K is an integer of 1 or more) as a current. In this case, the DA conversion unit 130 has 2 K -1 current sources CS. Note that the DA conversion unit 130 has one current source CS that outputs information corresponding to the value of the first bit as a current, two current sources CS that output information corresponding to the value of the second bit as a current, and 2 K-1 current sources CS that output information corresponding to the value of the Kth bit as a current.

[0148] In FIG. 6A, each current source CS has a terminal T1 and a terminal T2. The terminal T1 of each current source CS is electrically connected to the terminal Qin of the current mirror circuit CM. Also, the terminal Qout of the current mirror circuit CM is electrically connected to the output terminal C. Further, the terminal T2 of one current source CS is electrically connected to the terminal DW[1], and each of the terminals T2 of the two current sources CS is electrically connected to the terminal DW[2], and each of the terminals T2 of the K-1 two current sources CS is electrically connected to the terminal DW[K].

[0149] A digital signal output from the control unit 120 is input to the terminal DW. Specifically, the information of the first bit of the digital signal is input to the terminal DW[1], the information of the second bit is input to the terminal DW[2], and the information of the Kth bit is input to the terminal DW[K].

[0150] The plurality of current sources CS included in the DA conversion unit 130 shown in FIG. 6A each have a function of outputting the same constant current I Wut from the terminal T1. In practice, in the manufacturing stage of the arithmetic circuit, an error may occur due to variations in the characteristics of the transistors included in each current source CS. The error of the constant current I Wut output from each of the terminals T1 of the plurality of current sources CS is preferably within 10%, more preferably within 5%, and even more preferably within 1%. In this embodiment, it is described that there is no error in the constant current I Wut output from the terminals T1 of the plurality of current sources CS included in the DA conversion unit 130.

[0151] The terminals DW[1] to DW[K] function as wiring for transmitting a control signal for outputting the constant current I Wut from the current source CS to which they are electrically connected. Specifically, for example, when Vdd is applied to the terminal DW[1], the current source CS electrically connected to the terminal DW[1] outputs the constant current I WutWhen flowing through terminal T1 and when Vss is applied to terminal DW[1], current source CS electrically connected to terminal DW[1] does not output a constant current I Wut For example, when Vdd is applied to terminal DW[2], two current sources CS electrically connected to terminal DW[2] flow a total of 2I Wut as a constant current through terminal T1. Also, when Vss is applied to terminal DW[2], current source CS electrically connected to terminal DW[2] does not output a total constant current of 2I Wut For example, when Vdd is applied to terminal DW[K], two K-1 current sources CS electrically connected to terminal DW[K] flow a total of 2 K-1 I Wut as a constant current through terminal T1. Also, when Vss is applied to terminal DW[K], current source CS electrically connected to terminal DW[K] does not output a total constant current of 2 K-1 I Wut For example, when Vdd is applied to terminal DW[K], two current sources CS electrically connected to terminal DW[K] flow a total of 2

[0152] The current flowing through one current source CS electrically connected to terminal DW[1] corresponds to the value of the first bit, the current flowing through two current sources CS electrically connected to terminal DW[2] corresponds to the value of the second bit, and the current flowing through two K-1 current sources CS electrically connected to terminal DW[K] corresponds to the value of the Kth bit. Here, consider the DA conversion unit 130 when K is 2.

[0153] For example, when the value of the first bit is "1" and the value of the second bit is "0", Vdd is applied to terminal DW[1] and Vss is applied to terminal DW[2]. At this time, current I Wut flows as a reference current through terminal Qin of current mirror circuit CM.

[0154] Also, for example, when the value of the first bit is "0" and the value of the second bit is "1", Vss is applied to terminal DW[1] and Vdd is applied to terminal DW[2]. At this time, current 2I Wut flows as a reference current through terminal Qin of current mirror circuit CM.

[0155] Also, for example, when the value of the first bit is "1" and the value of the second bit is "1", Vdd is applied to terminals DW[1] and DW[2]. At this time, a reference current of 3I flows through terminal Qin of current mirror circuit CM. Wut flows.

[0156] Also, a current corresponding to the reference current flows through terminal Qout. Therefore, a current corresponding to the reference current also flows through output terminal C. When the transistor characteristics of transistor Q1 and transistor Q2 are the same, the current values of the current flowing through terminal Qin and the current flowing through terminal Qout become equal. Therefore, the current values of the current flowing through terminal Qin and the current flowing through output terminal C become equal.

[0157] Also, for example, when the value of the first bit is "0" and the value of the second bit is "0", Vss is applied to terminals DW[1] and terminal DW「2」. In this case, no current flows through terminal Qin. Therefore, no current flows through the output terminal either.

[0158] Note that FIG. 6A shows a configuration example of DA conversion unit 130 when K is an integer of 3 or more. When K is 1, a configuration may be adopted in which current source CS electrically connected to terminals DW[2] to DW[K] in FIG. 6A is not provided. Similarly, when K is 2, a configuration may be adopted in which current source CS electrically connected to terminals DW[3] (not shown) to DW[K] in FIG. 6A is not provided.

[0159] Next, a specific configuration example of current source CS will be described.

[0160] Current source CS1 shown in FIG. 7A is a circuit applicable to current source CS included in DA conversion unit 130 of FIG. 6A. Current source CS1 includes transistor Tr1 and transistor Tr2.

[0161] The first terminal of transistor Tr1 is electrically connected to wiring VDDL, and the second terminal of transistor Tr1 is electrically connected to the gate of transistor Tr1, the back gate of transistor Tr1, and the first terminal of transistor Tr2. The second terminal of transistor Tr2 is electrically connected to terminal T1, and the gate of transistor Tr2 is electrically connected to terminal T2. Also, terminal T2 is electrically connected to terminal DW. Terminal DW is any one of terminals DW[1] to DW[K] in FIG. 6A.

[0162] Wiring VDDL functions as a wiring for supplying a constant voltage. As the constant voltage, for example, it can be Vdd.

[0163] When the constant voltage supplied by wiring VDDL is Vdd, Vdd is input to the first terminal of transistor Tr1. Also, the potential of the second terminal of transistor Tr1 is set to a potential lower than Vdd. At this time, the first terminal of transistor Tr1 functions as a drain, and the second terminal of transistor Tr1 functions as a source.

[0164] Also, since the gate of transistor Tr1 and the second terminal of transistor Tr1 are electrically connected, the gate-source voltage of transistor Tr1 becomes 0V. Therefore, when the threshold voltage of transistor Tr1 is within an appropriate range, a subthreshold region current (drain current) flows between the first terminal and the second terminal of transistor Tr1. Also, it is more preferable that the current is within a range that increases exponentially with respect to the gate-source voltage. That is, transistor Tr1 functions as a current source for flowing a current in the subthreshold region.

[0165] In this specification and the like, the subthreshold region refers to a region in a graph showing the gate voltage (Vg)-drain current (Id) characteristics of a transistor where the absolute value of the gate voltage is smaller than the absolute value of the threshold voltage. Or the subthreshold region refers to a region where current flows due to carrier diffusion, which deviates from the gradual channel approximation (a model that only considers drift current). Or the subthreshold region refers to a region where the drain current increases exponentially with respect to the increase in the gate voltage. Or the subthreshold region is assumed to include regions that can be regarded as the regions described above.

[0166] Also, the drain current when the transistor operates in the subthreshold region is referred to as the subthreshold current. The subthreshold current increases exponentially with respect to the gate voltage regardless of the drain voltage. In circuit operation using the subthreshold current, the influence of variations in the drain voltage can be reduced.

[0167] Transistor Tr2 functions as a switching element. By the way, when the potential of the first terminal of transistor Tr2 is higher than the potential of the second terminal of transistor Tr2, the first terminal of transistor Tr2 functions as a drain, and the second terminal of transistor Tr2 functions as a source. Also, since the back gate of transistor Tr2 and the second terminal of transistor Tr2 are electrically connected, the back gate-source voltage becomes 0V. For this reason, when the threshold voltage of transistor Tr2 is within an appropriate range, when Vdd is input to the gate of transistor Tr2, transistor Tr2 is assumed to be in the on state, and when Vss is input to the gate of transistor Tr2, transistor Tr2 is assumed to be in the off state. Specifically, when transistor Tr2 is in the on state, the current in the subthreshold region described above flows from the second terminal of transistor Tr1 to terminal T1, and when transistor Tr2 is in the off state, no current flows from the second terminal of transistor Tr1 to terminal T1.

[0168] Note that the circuit applicable to the current source CS included in the DA conversion unit 130 in FIG. 6A is not limited to the current source CS1 in FIG. 7A. For example, although the current source CS1 is configured such that the back gate of the transistor Tr2 and the second terminal of the transistor Tr2 are electrically connected, the back gate of the transistor Tr2 may be electrically connected to another wiring. Such a configuration example is shown in FIG. 7B. The current source CS2 shown in FIG. 7B is configured such that the back gate of the transistor Tr2 is electrically connected to the wiring VTHL. The current source CS2 can apply the predetermined potential to the back gate of the transistor Tr2 from the external circuit or the like via the wiring VTHL by electrically connecting the wiring VTHL to the external circuit or the like. Thereby, the threshold voltage of the transistor Tr2 can be varied. In particular, by increasing the threshold voltage of the transistor Tr2, the off-current of the transistor Tr2 can be reduced.

[0169] The current source CS1 is configured such that the back gate of the transistor Tr1 and the second terminal of the transistor Tr1 are electrically connected, but a configuration may be adopted in which a voltage is held between the back gate of the transistor Tr1 and the second terminal of the transistor Tr1 by a capacitor. Such a configuration example is shown in FIG. 7C. The current source CS3 shown in FIG. 7C includes the transistor Tr3 and the capacitor C6 in addition to the transistor Tr1 and the transistor Tr2.

[0170] The current source CS3 is different from the current source CS1 in that the second terminal of the transistor Tr1 and the back gate of the transistor Tr1 are electrically connected via the capacitor C6, and the back gate of the transistor Tr1 and the first terminal of the transistor Tr3 are electrically connected.

[0171] Also, a current source CS3, in which a second terminal of a transistor Tr3 is electrically connected to a wiring VTL and a gate of the transistor Tr3 is electrically connected to a wiring VWL, can make the wiring VTL and a back gate of the transistor Tr1 in a conductive state by applying Vdd to the wiring VWL and turning on the transistor Tr3. Therefore, a predetermined potential can be input from the wiring VTL to the back gate of the transistor Tr1. Further, by turning off the transistor Tr3, the voltage between a second terminal of the transistor Tr1 and the back gate of the transistor Tr1 can be held by a capacitor C6. That is, by controlling the voltage applied to the back gate of the transistor Tr1 via the wiring VTL, the threshold voltage of the transistor Tr1 can be varied, and the threshold voltage of the transistor Tr1 can be fixed by the transistor Tr3 and the capacitor C6. Also, by controlling the potential of the wiring VTL, the current value flowing through a terminal T1 per bit can be controlled.

[0172] Further, as a circuit applicable to the current source CS included in the DA conversion unit 130 of FIG. 6A, it may be a current source CS4 shown in FIG. 7D. The current source CS4 has a configuration in which, in the current source CS3 of FIG. 7C, the back gate of the transistor Tr2 is electrically connected to a wiring VTHL instead of the second terminal of the transistor Tr2. That is, similar to the current source CS2 of FIG. 7B, the current source CS4 can vary the threshold voltage of the transistor Tr2 by controlling the potential applied to the back gate of the transistor Tr2 via the wiring VTHL.

[0173] In the current source CS4, when a large current flows between a first terminal and a second terminal of the transistor Tr1, it is necessary to increase the on-current of the transistor Tr2 in order to flow the current from the terminal T1 to the outside of the current source CS4. In this case, the current source CS4 can flow a large current flowing between the first terminal and the second terminal of the transistor Tr1 from the terminal T1 to the outside of the current source CS4 by applying Vdd to the wiring VTHL, lowering the threshold voltage of the transistor Tr2, and increasing the on-current of the transistor Tr2.

[0174] Also, when it is desired to reduce the current flowing between the first terminal and the second terminal of the transistor Tr1, the potential supplied to the wiring VTHL may be decreased. Alternatively, a negative voltage may be supplied to the wiring VTHL.

[0175] Also, as a circuit applicable to the current source CS included in the DA conversion unit 130 of FIG. 6A, the current source CS5 shown in FIG. 7E may be used. The current source CS5 is a modification of the current source CS1, and is different from the current source CS1 in that the gate of the transistor Tr1 is electrically connected to the wiring VGL instead of the second terminal of the transistor Tr1. For example, a potential at which the transistor Tr1 operates in the subthreshold region is supplied to the wiring VGL. By controlling the potential of the wiring VGL, the current value flowing through the terminal T1 per bit can be controlled.

[0176] By applying the current sources CS1 to CS5 shown in FIGS. 7A to 7E as the current source CS included in the DA conversion unit 130 of FIG. 6A, the DA conversion unit 130 can output a current corresponding to the K-bit first data.

[0177] Also, as the DA conversion unit 130, the circuit shown in FIG. 6B may be applied. The DA conversion unit 130 of FIG. 6B is configured such that one current source CS1 of FIG. 7A is connected to each of the terminals DW[1] to DW[K].

[0178] Also, when the channel lengths of the transistors Tr1[1] to Tr1[K] are the same, and the channel width of the transistor Tr1[1] is w[1], the channel width of the transistor Tr1[2] is w[2], and the channel width of the transistor Tr1[K] is w[K], the ratio of the respective channel widths is w[1]:w[2]:w[K]=1:2:2 K-1 is satisfied. Since the current flowing between the source and drain of a transistor operating in the subthreshold region is proportional to the channel width, the DA conversion unit 130 shown in FIG. 6B can output a current corresponding to the K-bit first data, similar to the DA conversion unit 130 of FIG. 6A.

[0179] Note that the transistor Tr1 (including transistors Tr1[1] to Tr1[K]), the transistor Tr2 (including transistors Tr2[1] to Tr2[K]), and the transistor Tr3 are preferably OS transistors.

[0180] When the gate voltage of the OS transistor is less than the threshold voltage of the transistor, a current extremely small as the drain current per 1 μm channel width, such as less than 1×10 -20 A, less than 1×10 -22 A, or less than 1×10 -24 A, can flow. Also, when the gate voltage of the OS transistor is the threshold voltage of the transistor, a drain current per 1 μm channel width, such as 1.0×10 -8 A or less, 1.0×10 -12 A or less, or 1.0×10 -15 A or less, can flow. For example, in the subthreshold region, the OS transistor can flow a drain current per 1 μm channel width in the range of 1×10 -24 A or more and 1.0×10 -8 A or less.

[0181] The OS transistor can flow subthreshold currents of different magnitudes in the range of the gate voltage operating in the subthreshold region. That is, the OS transistor can have a wide range of the gate voltage operating in the subthreshold region. Specifically, when the threshold voltage of the OS transistor is Vth, in the subthreshold region, circuit operation can be performed using a gate voltage in the voltage range of (Vth - 1.0 V) or more and Vth or less, or (Vth - 0.5 V) or more and Vth or less.

[0182] On the other hand, in the Si transistor, the off-current is large and the range of the gate voltage operating in the subthreshold region is narrow. When using the subthreshold current, the OS transistor can perform circuit operation in a wider range of the gate voltage than the Si transistor.

[0183] Therefore, it is preferable to use an OS transistor as the transistor that operates in the subthreshold region. However, depending on the purpose or application, a transistor other than the OS transistor may be used as the transistor that operates in the subthreshold region. An OS transistor and a transistor other than the OS transistor may be used in combination.

[0184] A modification example of the DA conversion unit 130 shown in FIG. 6A is shown in FIG. 8A. The DA conversion unit 130 shown in FIG. 8A is different from the DA conversion unit 130 shown in FIG. 6A in that it does not have a current mirror circuit CM.

[0185] A configuration example of the current source CS6 that can be used for the current source CS of the DA conversion unit 130 shown in FIG. 8A is shown in FIG. 8B.

[0186] The current source CS6 shown in FIG. 8B includes a transistor Tr1 and a transistor Tr2. Vss or GND is supplied to the first terminal of the transistor Tr1. The second terminal of the transistor Tr1 is electrically connected to the first terminal of the transistor Tr2. The second terminal of the transistor Tr2 is electrically connected to the terminal T1.

[0187] The gate of the transistor Tr1 is electrically connected to the wiring VGL. For example, a potential at which the transistor Tr1 operates in the subthreshold region is supplied to the wiring VGL. By controlling the potential of the wiring VGL, the current value flowing through the terminal T1 per bit can be controlled.

[0188] The gate of the transistor Tr2 is electrically connected to the terminal T2. The back gate of the transistor Tr1 and the back gate of the transistor Tr2 are electrically connected to the first terminal of the transistor Tr1.

[0189] A configuration example of a current source CS7, which is a modified example of the current source CS6, is shown in FIG. 8C. In the current source CS7, the gate and back gate of the transistor Tr1 are electrically connected, and the gate and back gate of the transistor Tr2 are electrically connected. By electrically connecting the gate and back gate, the on-current of the transistor can be increased.

[0190] Also, as the current source CS of the DA conversion unit 130 shown in FIG. 8A, the current source CS8 shown in FIG. 8D can be used. The current source CS8 uses a p-channel transistor for the transistor Tr1 and an n-channel transistor for the transistor Tr2.

[0191] In the current source CS8, Vss or GND is supplied to the first terminal of the transistor Tr1. The second terminal of the transistor Tr1 is electrically connected to the first terminal of the transistor Tr2. The second terminal of the transistor Tr2 is electrically connected to the terminal T1. The gate and back gate of the transistor Tr1 are electrically connected to the second terminal of the transistor Tr1. The back gate of the transistor Tr2 is electrically connected to the first terminal of the transistor Tr2. Note that the current source CS8 can operate in the same manner as the current source CS1, although the direction of the current flowing through the terminal T1 is different.

[0192] Also, as the current source CS of the DA conversion unit 130 shown in FIG. 8A, the current source CS9 shown in FIG. 8E may be used.

[0193] The current source CS9 is different from the current source CS8 in that the second terminal of the transistor Tr1 and the back gate of the transistor Tr1 are electrically connected via the capacitor C6, and the back gate of the transistor Tr1 and the first terminal of the transistor Tr3 are electrically connected.

[0194] Also, in current source CS9, the second terminal of transistor Tr3 is electrically connected to wiring VTL, and the gate of transistor Tr3 is electrically connected to wiring VWL. By applying Vdd to wiring VWL and turning on transistor Tr3, conduction can be established between wiring VTL and the back gate of transistor Tr1. Thus, a predetermined potential can be input from wiring VTL to the back gate of transistor Tr1 via transistor Tr3. Also, by turning off transistor Tr3, the voltage between the second terminal of transistor Tr1 and the back gate of transistor Tr1 can be held by capacitor C6. By controlling the voltage applied to the back gate of transistor Tr1 via wiring VTL, the threshold voltage of transistor Tr1 can be varied, and the threshold voltage of transistor Tr1 can be fixed by transistor Tr3 and capacitor C6.

[0195] Current source CS9 can operate in the same manner as current source CS3, although the direction of the current flowing into terminal T1 is different.

[0196] Also, as the current source CS of the DA conversion unit 130 shown in FIG. 8A, current source CS10 shown in FIG. 8F may be used. Current source CS10 is a modification of current source CS8, and differs from current source CS8 in that the gate of transistor Tr1 is electrically connected to wiring VGL instead of the second terminal of transistor Tr1. For example, a potential at which transistor Tr1 operates in the subthreshold region is supplied to wiring VGL. By controlling the potential of wiring VGL, the current value flowing into terminal T1 per bit can be controlled.

[0197] Also, current sources CS8 to CS10 may electrically connect the back gate of transistor Tr2 to wiring VTHL instead of the first terminal of transistor Tr2, like current sources CS2 and CS4. By controlling the potential applied to the back gate of transistor Tr2 via wiring VTHL, the threshold voltage of transistor Tr2 can be varied.

[0198] Also, the DA conversion unit 130 shown in FIG. 8A may have the same configuration as the DA conversion unit 130 shown in FIG. 6B.

[0199] This embodiment can be appropriately combined with other embodiments shown in this specification and the like.

[0200] (Embodiment 2) The semiconductor device according to one aspect of the present invention can be used, for example, in an arithmetic circuit that performs neural network operations. In this embodiment, an arithmetic circuit that performs neural network operations will be described.

[0201] <Hierarchical neural network> First, a hierarchical neural network will be described. As an example, a hierarchical neural network has one input layer, one or more intermediate layers (hidden layers), and one output layer, and is composed of a total of three or more layers. The hierarchical neural network 300 shown in FIG. 9A shows an example thereof, and the neural network 300 has the first layer to the Rth layer (where R can be an integer of 4 or more). In particular, the first layer corresponds to the input layer, the Rth layer corresponds to the output layer, and the other layers correspond to the intermediate layers. In FIG. 9A, the (k - 1)th layer and the kth layer (where k is an integer of 3 or more and R - 1 or less) are shown as intermediate layers, and the illustration of the other intermediate layers is omitted.

[0202] Each layer of the neural network 300 has one or more neurons. In FIG. 9A, the first layer has neurons N1 (1) to neuron N p (1) (p is an integer of 1 or more), the (k - 1)th layer has neurons N1 (k-1) to neuron N m (k-1) (m is an integer of 1 or more), the kth layer has neurons N1 (k) to neuron N n (k) (n is an integer of 1 or more), and the Rth layer has neurons N1 (R)up to neuron N q (R) (q is an integer of 1 or more.) It has.

[0203] Note that in FIG. 9A, neuron N1 (1) , neuron N p (1) , neuron N1 (k-1) , neuron N m (k-1) , neuron N1 (k) , neuron N n (k) , neuron N1 (R) , neuron N q (R) In addition to, neuron N of the (k - 1) - th layer i (k-1) (i is an integer of 1 or more and m or less.), neuron N of the k - th layer j (k) (j is an integer of 1 or more and n or less.) are also shown, and other neurons are not shown.

[0204] Next, the transmission of signals from neurons in the previous layer to neurons in the next layer, and the signals input and output in each neuron will be described. Note that in this description, attention is paid to neuron N of the k - th layer j (k) .

[0205] FIG. 9B shows neuron N of the k - th layer j (k) , the signal input to neuron N j (k) , and the signal output from neuron N j (k) .

[0206] Specifically, z1 which is the output signal of each of neurons N1 (k-1) up to neuron N m (k-1) of the (k - 1) - th layer (k-1) up to z m (k-1) is, neuron N j (k)is output toward. And neuron N j (k) is z1 (k-1) to z m (k-1) According to z j (k) generates z j (k) and outputs z

[0207] The signal input from the neurons in the previous layer to the neurons in the next layer has the degree of signal transmission determined by the connection strength of the synapses connecting those neurons (hereinafter referred to as the weight coefficient). In the neural network 300, the signal output from the neurons in the previous layer is multiplied by the corresponding weight coefficient and input to the neurons in the next layer. Let i be an integer from 1 to m, and the neuron N i (k-1) in the (k - 1)th layer and the neuron N j (k) in the kth layer, when the weight coefficient of the synapse between them is w i (k-1) j (k) j (k) (k-1) The signal input to the neuron N

[0208]

Equation

[0209] That is, when the signal is transmitted from each of the neurons N1 (k-1) to N m (k-1) in the (k - 1)th layer to the neuron N j (k) in the kth layer, for the signals z1 (k-1) to z m (k-1) each signal has the corresponding weight coefficient (w1 (k-1) j (k) to w m(k-1) j (k) ) is multiplied. And for the neuron N in the k-th layer j (k) there are inputs of w1 (k-1) j (k) ·z1 (k-1) to w m (k-1) j (k) ·z m (k-1) At this time, the sum u of the signals input to the neuron N in the k-th layer j (k) is given by Equation (1.2). j (k)

[0210]

Equation

[0211] Also, to the result of the sum of products of the weight coefficients w1 (k-1) j (k) to w m (k-1) j (k) and the neuron signals z1 (k-1) to z m (k-1) a bias may be given as a bias. When the bias is b, Equation (1.2) can be rewritten as the following Equation (1.3).

[0212]

Equation

[0213] The neuron N j (k) generates an output signal z j (k) in response to u j (k) Here, the output signal z from the neuron N j (k) j (k) ​​is defined by the following equation (1.4).

[0214] [Number]

[0215] The function f(u j (k) ) is an activation function in a hierarchical neural network, and a step function, a linear ramp function, a sigmoid function, etc. can be used. Note that the activation function may be the same for all neurons, or may be different. In addition, the activation function of neurons may be the same or different for each layer.

[0216] By the way, the signals output by the neurons in each layer, the weight coefficients w, and the bias b may be analog values, discrete values of two or more values, or digital values. The digital value may be one bit or more. For example, when the signal output by the neurons in each layer is an analog value, a linear ramp function, a sigmoid function, etc. may be used as the activation function. Also, when the signal output by the neurons in each layer is a digital value of 1 bit (two values), for example, a step function that converts the output to either -1 or 1, or a step function that converts the output to either 0 or 1 may be used.

[0217] Also, when the signal output by the neurons in each layer is three-valued, the activation function may be, for example, a step function that converts the output to either -1, 0, or 1, or a step function that converts the output to either 0, 1, or 2. Also, when the signal output by the neurons in each layer is five-valued, the activation function may be, for example, a step function that converts the output to either -2, -1, 0, 1, or 2.

[0218] By using digital values for at least one of the signals output by the neurons in each layer, the weight coefficient w, or the bias b, it is possible to reduce the circuit scale, reduce power consumption, or increase the calculation speed. Also, by using analog values for at least one of the signals output by the neurons in each layer, the weight coefficient w, or the bias b, it is possible to improve the calculation accuracy.

[0219] When an input signal is input to the first layer (input layer) of the neural network 300, in each layer from the first layer (input layer) to the last layer (output layer) in sequence, based on the signal input from the previous layer, the output signal is generated using Equation (1.1), Equation (1.2) (or Equation (1.3)), and Equation (1.4), and the output signal is output to the next layer. The signal output from the last layer (output layer) corresponds to the result calculated by the neural network 300.

[0220] <Configuration Example of Arithmetic Circuit> Here, in the above-described neural network 300, an example of an arithmetic circuit capable of performing the operations of Equation (1.2) (or Equation (1.3)) and Equation (1.4) will be described. In this arithmetic circuit, as an example, the weight coefficients of the synaptic circuits of the neural network 300 are binary values (combinations of “-1” and “+1”, or combinations of “0” and “+1”, etc.), ternary values (combinations of “-1”, “0”, and “1”, etc.), or multi-valued values of four or more values (in the case of five values, combinations of “-2”, “-1”, “0”, “1”, and “2”, etc.), and the activation function of the neuron is a function that outputs binary values (combinations of “-1” and “+1”, or combinations of “0” and “+1”, etc.), ternary values (combinations of “-1”, “0”, and “1”, etc.), multi-valued values of four or more values (in the case of four values, combinations of “0”, “1”, “2”, and “3”, etc.). Note that the weight coefficients of the synaptic circuits of the neural network 300 and the values of the signals input from the neurons in the previous layer to the neurons in the next layer are not limited to digital values, and it is also possible to use analog values for at least one of them.

[0221] The arithmetic circuit 310 shown in FIG. 10A is, as an example, a semiconductor device having an array section ALP, a circuit ILD, a circuit WLD, a circuit XLD, and a circuit AFP. The arithmetic circuit 310 processes the signals z1 (k) to neuron N n (k) input to neurons N1 (k-1) to z m (k-1) in FIG. 9A and FIG. 9B, layer k, and generates the signals z1 (k) to neuron N1 n (k) output from each of neurons N (k) to z n (k) .

[0222] Note that the entire arithmetic circuit 310 or a part thereof may be used for applications other than neural networks and AI. For example, when performing multiplication-accumulation operation processing or matrix operation processing in graphic-oriented calculations or scientific calculations, the entire arithmetic circuit 310 or a part thereof may be used for the processing. That is, not only for AI-oriented calculations but also for general calculations, the entire arithmetic circuit 310 or a part thereof may be used.

[0223] The circuit ILD is electrically connected to, as an example, wirings IL[1] to IL[n] and wirings ILB[1] to ILB[n]. The circuit WLD is electrically connected to, as an example, wirings WLS[1] to WLS[m]. The circuit XLD is electrically connected to, as an example, wirings XLS[1] to XLS[m]. The circuit AFP is electrically connected to, as an example, wirings OL[1] to OL[n] and wirings OLB[1] to OLB[n].

[0224] <<Array section ALP>> The arithmetic circuit 310 shown in FIG. 10A has a circuit MP in which an array unit ALP is arranged in an m×n matrix. In FIG. 10A, the circuit MP located at the i-th row and j-th column (where i is an integer from 1 to m, and j is an integer from 1 to n) is denoted as circuit MP[i,j]. However, in FIG. 10A, only circuit MP[1,1], circuit MP[m,1], circuit MP[i,j], circuit MP[1,n], and circuit MP[m,n] are illustrated, and the illustration of other circuits MP is omitted.

[0225] As an example, circuit MP[i,j] is electrically connected to wiring IL[j], wiring ILB[j], wiring WLS[i], wiring XLS[i], wiring OL[j], and wiring OLB[j].

[0226] As an example, circuit MP[i,j] is a neuron N i (k-1) and neuron N j (k) and has a function of holding a weight coefficient (also referred to as first data) between them. Specifically, circuit MP[i,j] holds information (such as potential, resistance value, current value, etc.) corresponding to the weight coefficient input from wiring IL[j] and wiring ILB[j]. Also, circuit MP[i,j] i (k-1) outputs the product of z i (k-1) (also referred to as second data) and the first data. As a specific example, when the second data is input from wiring XLS[i], circuit MP[i,j] outputs a current corresponding to the product of the first data and the second data to wiring OL[j] and wiring OLB[j]. In FIG. 10A, an example where wiring IL[j] and wiring ILB[j] are arranged is shown, but one aspect of the present invention is not limited to this. Only one of wiring IL[j] and wiring ILB[j] may be arranged.

[0227] <<Circuit ILD>> The circuit ILD, as an example, has a function of inputting information (such as potential, resistance value, current value, etc.) corresponding to the first data w1 (k-1) 1 (k) to the first data w m (k-1) n (k) through the wiring IL[1] to IL[n] and the wiring ILB[1] to ILB[n] for each of the circuits MP[1,1] to MP[m,n]. As a specific example, the circuit ILD supplies information (such as potential, resistance value, or current value, etc.) corresponding to the first data w i (k-1) j (k) to the circuit MP[i,j] through the wiring IL[j] and ILB[j].

[0228] <<Circuit XLD>> The circuit XLD, as an example, has a function of supplying the second data z1 (k-1) to the second data z m (k) output from the neurons N1 (k-1) to each of the circuits MP[1,1] to MP[m,n] through the wiring XLS[1] to XLS[m]. Specifically, the circuit XLD supplies information (such as potential, current value, etc.) corresponding to the second data z m (k-1) output from the neurons N i (k-1) to the circuits MP[i,1] to MP[i,n] through the wiring XLS[i]. i (k-1)

[0229] <<Circuit WLD>> The circuit WLD has a function of selecting, as an example, a circuit MP that is a destination for writing information (such as potential, resistance value, current value, etc.) corresponding to the first data input from the circuit ILD. For example, when writing information (such as potential, resistance value, current value, etc.) to the circuits MP[i,1] to MP[i,n] located in the i-th row of the array section ALP, the circuit WLD supplies, for example, signals for turning on or off the writing switching elements included in the circuits MP[i,1] to MP[i,n] to the wiring WLS[i], and supplies a potential for turning off the writing switching elements included in the circuits MP other than the i-th row to the wiring WLS. Although an example where the wiring WLS[i] is arranged has been shown, one aspect of the present invention is not limited thereto. In addition to the wiring WLS[i], for example, a wiring for transmitting an inverted signal of the signal input to the wiring WLS[i] may be separately arranged.

[0230] <<Circuit AFP>> The circuit AFP has, as an example, circuits ACTF[1] to ACTF[n]. The circuit ACTF[j] is electrically connected to each of the wiring OL[j] and the wiring OLB[j], as an example. The circuit ACTF[j] generates, as an example, a signal corresponding to each piece of information (such as potential, current value, etc.) input from the wiring OL[j] and the wiring OLB[j]. The signal corresponds to the signal z j (k) output from the neuron N j (k) For example, the circuits ACTF[1] to ACTF[n] may have a function of converting an analog signal into a digital signal. Therefore, the AD conversion device 100 can be used for the circuits ACTF[1] to ACTF[n].

[0231] In addition, the circuits ACTF[1] to ACTF[n] may have a function of amplifying and outputting an analog signal, that is, a function of converting an output impedance. Alternatively, the circuits ACTF[1] to ACTF[n] may have a function of converting current or charge into voltage. Alternatively, the circuits ACTF[1] to ACTF[n] may each have a function of initializing the potentials of the wiring OL and the wiring OLB that are electrically connected thereto.

[0232] <<Circuit MP>> FIG. 10B shows a configuration example of the circuit MP[i, j]. The circuit MP[i, j] includes a circuit MC and a circuit MCr. The circuit MC and the circuit MCr are circuits that calculate the product of the weight coefficient and the input signal (computed value) of the neuron in the circuit MP. The circuit MC can have the same configuration as the circuit MCr or a different configuration from the circuit MCr. Therefore, the circuit MCr is labeled with "r" in the symbol to distinguish it from the circuit MC. Also, the symbols of the circuit elements described later included in the circuit MCr are also labeled with "r".

[0233] The circuit MC has a holding unit HC, and the circuit MCr has a holding unit HCr. The holding unit HC and the holding unit HCr each have a function of holding information (for example, potential, resistance value, current value, etc.). Note that the first data w set in the circuit MP[i, j] i (k-1) j (k) is determined according to the information held in each of the holding unit HC and the holding unit HCr. Therefore, each of the holding unit HC and the holding unit HCr is electrically connected to the wiring IL[j] and the wiring ILB[j] that supply the respective information corresponding to the first data w i (k-1) j (k) to which it corresponds.

[0234] In FIG. 10B, circuit MP[i,j] is electrically connected to wiring VE[j] and wiring VEr[j]. Wiring VE[j] and wiring VEr[j] function as wirings that supply a constant voltage. Further, wiring VE[j] also functions as a wiring that discharges the current from wiring OL via circuit MC. Further, wiring VEr[j] also functions as a wiring that discharges the current from wiring OLB via circuit MCr.

[0235] The wiring WL[i] shown in FIG. 10B corresponds to the wiring WLS[i] in FIG. 10A. Wiring WL[i] is electrically connected to each of holding section HC and holding section HCr. When writing information (for example, potential, resistance value, current value, etc.) corresponding to first data w i (k-1) j (k) to holding section HC and holding section HCr included in circuit MP[i,j], by supplying a predetermined potential to wiring WL[i], a conductive state is established between wiring IL[j] and holding section HC, and a conductive state is established between wiring ILB[j] and holding section HCr. Then, by supplying a potential etc. corresponding to first data w i (k-1) j (k) to each of wiring IL[j] and ILB[j], the potential etc. can be input to each of holding section HC and holding section HCr. Thereafter, by supplying a predetermined potential to wiring WL[i], a non-conductive state is established between wiring IL[j] and holding section HC, and a non-conductive state is established between wiring ILB[j] and holding section HCr. Then, a voltage etc. corresponding to first data w i (k-1) j (k) is held in each of holding section HC and holding section HCr.

[0236] For example, consider the case where first data w i (k-1) j (k) takes any one of the three values of “-1”, “0”, and “1”. First data w i (k-1) j (k)When it is "1", as an example, a predetermined potential is held in the holding unit HC so that a current corresponding to "1" flows from the wiring OL[j] through the circuit MC to the wiring VE[j], and a potential V0 is held in the holding unit HCr so that no current flows from the wiring OLB[j] through the circuit MCr to the wiring VEr[j]. Also, the first data w i (k-1) j (k) When it is "-1", as an example, a potential V0 is held in the holding unit HC so that no current flows from the wiring OL[j] through the circuit MC to the wiring VE[j], and a predetermined potential is held in the holding unit HCr so that a current corresponding to "-1" flows from the wiring OLB[j] through the circuit MCr to the wiring VEr[j]. And the first data w i (k-1) j (k) When it is "0", as an example, a potential V0 is held in the holding unit HC so that no current flows from the wiring OL[j] through the circuit MC to the wiring VE[j], and a potential V0 is held in the holding unit HCr so that no current flows from the wiring OLB[j] through the circuit MC to the wiring VEr[j]. Note that the potential V0 can be, for example, Vss.

[0237] Note that, as another example, the first data w i (k-1) j (k) Consider the case where it takes an analog value, specifically, "negative analog value", "0", or "positive analog value". The first data w i (k-1) j (k) When it is "positive analog value", a predetermined potential is held in the holding unit HC so that an analog current corresponding to the "positive analog value" flows from the wiring OL[j] through the circuit MC to the wiring VE[j], and a potential V0 is held in the holding unit HCr so that no current flows from the wiring OLB[j] through the circuit MCr to the wiring VEr[j]. Also, the first data w i (k-1) j (k)When it is a "negative analog value", the holding unit HC holds the potential V0 so that no current flows from the wiring OL[j] to the wiring VE[j] via the circuit MC, and the holding unit HCr holds a predetermined potential so that an analog current corresponding to the "negative analog value" flows from the wiring OLB[j] to the wiring VEr[j] via the circuit MCr. And the first data w i (k-1) j (k) When it is "0", the holding unit HC holds the potential V0 so that no current flows from the wiring OL[j] to the wiring VE[j] via the circuit MC, and the holding unit HCr holds the potential V0 so that no current flows from the wiring OLB[j] to the wiring VEr[j] via the circuit MC.

[0238] Also, the circuit MC has a function of outputting a current or the like corresponding to the information held in the holding unit HC to one of the wiring OL[j] or the wiring OLB[j], and the circuit MCr has a function of outputting a current or the like corresponding to the information held in the holding unit HCr to the other of the wiring OL[j] or the wiring OLB[j]. For example, when the first potential is held in the holding unit HC, the circuit MC is assumed to flow a current having the first current value from the wiring OL[j] or the wiring OLB[j] to the wiring VE, and when the second potential is held in the holding unit HC, the circuit MC is assumed to flow a current having the second current value from the wiring OL[j] or the wiring OLB[j] to the wiring VE. Similarly, when the first potential is held in the holding unit HCr, the circuit MCr is assumed to flow a current having the first current value from the wiring OL[j] or the wiring OLB[j] to the wiring VEr, and when the second potential is held in the holding unit HCr, the circuit MCr is assumed to flow a current having the second current value from the wiring OL[j] or the wiring OLB[j] to the wiring VE. Note that the magnitudes of the first current value and the second current value are the first data w i (k-1) j (k)It is determined by the value of . Therefore, the first current value may be greater than or less than the second current value. Furthermore, one of the first current value or the second current value may be a zero current, that is, the current value is 0. Or, the directions in which the current flows may be different between the current having the first current value and the current having the second current value.

[0239] In particular, for example, the first data w i (k-1) j (k) takes one of the three values of "-1", "0", and "1", it is preferable to configure the circuits MC and MCr so that one of the first current value or the second current value becomes zero. Note that the first data w i (k-1) j (k) takes an analog value, for example, "negative analog value", "0", or "positive analog value", the first current value or the second current value can also take an analog value.

[0240] By the way, when making the current flowing from the wiring OL[j] or the wiring OLB[j] to the wiring VE through the circuit MC equal to the current flowing from the wiring OL[j] or the wiring OLB[j] to the wiring VEr through the circuit MCr, due to factors such as the manufacturing process of the transistor, the characteristics of the transistor may vary. Therefore, the potential held by the circuit MC and the potential held by the circuit MCr may not be equal. The semiconductor device according to one aspect of the present invention can make the amount of current flowing from the wiring OL[j] or the wiring OLB[j] to the wiring VE through the circuit MC substantially equal to the amount of current flowing from the wiring OL[j] or the wiring OLB[j] to the wiring VEr through the circuit MCr even if there are variations in the characteristics of the transistor.

[0241] In addition, in this specification and the like, the current, voltage, etc. corresponding to the information held in the holding unit HC or the holding unit HCr may be a positive current, positive voltage, etc., or a negative current, negative voltage, etc., or a zero current, zero voltage, etc., or a mixture of positive, negative, and 0. That is, for example, the description "having a function of outputting a current, voltage, etc. corresponding to the information held in the holding unit HC to one of the wirings OL[j] or OLB[j], and the circuit MCr has a function of outputting a current, voltage, etc. corresponding to the information held in the holding unit HCr to the other of the wirings OL[j] or OLB[j]" can be paraphrased as "having a function of discharging a current, voltage, etc. corresponding to the information held in the holding unit HC from one of the wirings OL[j] or OLB[j], and the circuit MCr has a function of discharging a current, voltage, etc. corresponding to the information held in the holding unit HCr from the other of the wirings OL[j] or OLB[j]".

[0242] The wirings X1L[i] and X2L[i] shown in FIG. 10B correspond to the wiring XLS[i] in FIG. 10A. Note that the second data z input to the circuit MP[i,j] i (k-1) is, as an example, determined by the respective potentials or currents of the wirings X1L[i] and X2L[i]. Therefore, to the circuits MC and MCr, for example, the second data z i (k-1) is input with each potential corresponding thereto via the wirings X1L[i] and X2L[i].

[0243] The circuit MC is electrically connected to the wirings OL[j] and OLB[j], and the circuit MCr is electrically connected to the wirings OL[j] and OLB[j]. The circuits MC and MCr, in response to the potential or current, etc. input to the wirings X1L[i] and X2L[i], supply the first data w i (k-1) j (k) and the second data z i (k-1)It has a function of outputting a current or a potential according to the product with [something]. As a specific example, the output destinations of the currents from circuits MC and MCr are determined by the potentials of wirings X1L[i] and X2L[i]. For example, circuits MC and MCr have a circuit configuration such that the current output from circuit MC flows through one of wirings OL[j] or OLB[j], and the current output from circuit MCr flows through the other of wirings OL[j] or OLB[j]. That is, the respective currents output from circuits MC and MCr flow through different wirings from each other, not the same wiring. Note that there may be a case where no current flows from circuits MC and MCr through either of wirings OL[j] or OLB[j].

[0244] For example, the second data z i (k-1) is considered to take one of the three values of "-1", "0", and "1". For example, when the second data z i (k-1) is "1", circuit MP makes the connection between circuit MC and wiring OL[j] in a conductive state and the connection between circuit MCr and wiring OLB[j] in a conductive state. When the second data z i (k-1) is "-1", circuit MP makes the connection between circuit MC and wiring OLB[j] in a conductive state and the connection between circuit MCr and wiring OL[j] in a conductive state. When the second data z i (k-1) is "0", in order to prevent the currents output from circuits MC and MCr from flowing through either of wirings OL[j] and OLB[j], circuit MP makes the connections between circuit MC and wiring OL[j] and between circuit MC and wiring OLB[j] in a non-conductive state, and also makes the connections between circuit MCr and wiring OL[j] and between circuit MC and wiring OLB[j] in a non-conductive state.

[0245] An example of summarizing the above operations is shown. The first data w i (k-1) j (k)When it is "1", current may flow from wiring OL[j] or wiring OLB[j] to wiring VE[j] via circuit MC, and no current flows from wiring OL[j] or wiring OLB[j] to wiring VEr[j] via circuit MCr. First data w i (k-1) j (k) When it is "-1", no current flows from wiring OL[j] or wiring OLB[j] to wiring VE[j] via circuit MC, and current may flow from wiring OL[j] or wiring OLB[j] to wiring VEr[j] via circuit MCr. And second data z i (k-1) When it is "1", the connection between circuit MC and wiring OL[j], and the connection between circuit MCr and wiring OLB[j] become conductive states. Second data z i (k-1) When it is "-1", the connection between circuit MC and wiring OLB[j], and the connection between circuit MCr and wiring OL[j] become conductive states. From the above, first data w i (k-1) j (k) and second data z i (k-1) When the product of and second data z is a positive value, either current flows from wiring OL[j] to wiring VE[j] via circuit MC or current flows from wiring OL[j] to wiring VEr[j] via circuit MCr. First data w i (k-1) j (k) and second data z i (k-1) When the product of is a negative value, either current flows from wiring OLB[j] to wiring VEr[j] via circuit MCr or current flows from wiring OLB[j] to wiring VE[j] via circuit MC. First data w i (k-1) j (k) and second data z i (k-1) When the product of is a zero value, no current flows from wiring OL[j] or wiring OLB[j] to wiring VE[j], and no current flows from wiring OL[j] or wiring OLB[j] to wiring VEr[j].

[0246] Taking the above example as a specific example, the first data w i (k-1) j (k) is "1", and the second data z i (k-1) is "1". For example, a current I1[i, j] with a first current value flows from the circuit MC to the wiring OL[j], and a current I2[i, j] with a second current value flows from the circuit MCr to the wiring OLB[j]. At this time, as an example, the magnitude of the second current value is zero. The first data w i (k-1) j (k) is "-1", and the second data z i (k-1) is "1". For example, a current I1[i, j] with a second current value flows from the circuit MC to the wiring OL[j], and a current I2[i, j] with a first current value flows from the circuit MCr to the wiring OLB[j]. At this time, as an example, the magnitude of the second current value is zero. The first data w i (k-1) j (k) is "0", and the second data z i (k-1) is "1". A current I1[i, j] with a second current value flows from the circuit MC to the wiring OL[j], and a current I2[i, j] with a second current value flows from the circuit MCr to the wiring OLB[j]. At this time, as an example, the magnitude of the second current value is zero.

[0247] Also, when the first data w i (k-1) j (k) is "1" and the second data z i (k-1) is "-1", a current I1[i, j] with a first current value flows from the circuit MC to the wiring OLB[j], and a current I2[i, j] with a second current value flows from the circuit MCr to the wiring OL[j]. At this time, as an example, the magnitude of the second current value is zero. The first data w i (k-1) j(k) is “-1” and the second data z i (k-1) is “-1”, a current I1[i, j] with a second current value flows from the circuit MC to the wiring OLB[j], and a current I2[i, j] with a first current value flows from the circuit MCr to the wiring OL[j]. At this time, as an example, the magnitude of the second current value is zero. The first data w i (k-1) j (k) is “0” and the second data z i (k-1) is “-1”, a current I1[i, j] with a second current value flows from the circuit MC to the wiring OLB[j], and a current I2[i, j] with the second current value flows from the circuit MCr to the wiring OL[j]. At this time, as an example, the magnitude of the second current value is zero.

[0248] Also, when the second data z i (k-1) is “0”, the states between the circuit MC and the wiring OL[j] and between the circuit MC and the wiring OLB[j] become non-conductive states. Similarly, the states between the circuit MCr and the wiring OL[j] and between the circuit MCr and the wiring OLB[j] become non-conductive states. Therefore, no matter what value the first data w i (k-1) j (k) may have, no current is output from the circuit MC and the circuit MCr to the wiring OL[j] and the wiring OLB[j].

[0249] In this way, when the product of the first data w i (k-1) j (k) and the second data z i (k-1) takes a positive value, current flows from either the circuit MC or the circuit MCr to the wiring OL[j]. Specifically, when the first data w i (k-1) j (k) is a positive value, current flows from the circuit MC to the wiring OL[j], and when the first data w i (k-1) j(k) When the value of (k) is negative, current flows from the circuit MCr to the wiring OLj.

[0250] On the other hand, when the product of the first data w i (k-1) j (k) and the second data z i (k-1) is negative, current flows from either the circuit MC or the circuit MCr to the wiring OLBj. Specifically, when the first data w i (k-1) j (k) is positive, current flows from the circuit MC to the wiring OLBj, and when the first data w i (k-1) j (k) is negative, current flows from the circuit MCr to the wiring OLBj.

[0251] Therefore, the sum of the currents output from the plurality of circuits MC or the plurality of circuits MCr connected to the wiring OLj will flow through the wiring OLj. That is, a current corresponding to the sum of positive values will flow through the wiring OLj. On the other hand, the sum of the currents output from the plurality of circuits MC or the plurality of circuits MCr connected to the wiring OLBj will flow through the wiring OLBj. That is, a current corresponding to the sum of negative values will flow through the wiring OLBj.

[0252] As a result of the above operations, a current corresponding to the sum of positive values flows through the wiring OLj, and a current corresponding to the sum of negative values flows through the wiring OLBj. By obtaining the difference between the current flowing through the wiring OLj and the current flowing through the wiring OLBj, the product-sum operation process is completed.

[0253] At this time, if the value of the current flowing through wiring OL[j] is greater than the value of the current flowing through wiring OLB[j], it can be determined that the product-sum operation result takes a positive value. If the value of the current flowing through wiring OL[j] is smaller than the value of the current flowing through wiring OLB[j], it can be determined that the product-sum operation result takes a negative value. If the value of the current flowing through wiring OL[j] is the same as or approximately the same as the value of the current flowing through wiring OLB[j], it can be determined that the product-sum operation result is zero.

[0254] By using the AD conversion device 100 according to an aspect of the present invention for the circuit ACTF[j] to which the wiring OL[j] and the wiring OLB[j] are electrically connected, the product-sum operation result can be efficiently converted into a digital signal with positive and negative signs.

[0255] Note that for the second data z i (k-1) when it is any two values among "-1", "0", and "1", for example, in the case of two values of "-1" and "1", or in the case of two values of "0" and "1", it can be operated in the same manner. Similarly, for the first data w i (k-1) j (k) when it is any two values among "-1", "0", and "1", for example, in the case of two values of "-1" and "1", or in the case of two values of "0" and "1", it can be operated in the same manner.

[0256] Note that the first data w i (k-1) j (k) may take an analog value or a multi-bit (multi-value) digital value. For example, instead of "-1", it may take a "negative analog value", and instead of "1", it may take a "positive analog value". In this case, the magnitude of the current flowing from the circuit MC or the circuit MCr also becomes an analog value corresponding to the absolute value of the value of the first data w i (k-1) j (k) of the value.

[0257] A circuit configuration example applicable to circuit MP is shown in Fig. 11A. Circuit MP includes circuit MC and circuit MCr. Circuit MC has transistors M1 to M5 and capacitor C1. The holding part HC is constituted by transistor M2, transistor M5, and capacitor C1.

[0258] Circuit MCr has a circuit configuration substantially the same as that of circuit MC. Therefore, in order to distinguish the circuit elements and the like of circuit MCr from those of circuit MC, an "r" is attached to the symbols.

[0259] In Fig. 11A, transistors M1 to M5 are represented as n-channel transistors with a multi-gate structure having a back gate. Therefore, each of transistors M1 to M5 shown in Fig. 11A includes a first gate and a second gate. Also, in transistors M3 and M4, it is preferable that their sizes such as channel length and channel width are equal.

[0260] Although the back gates are shown for transistors M1 to M5 illustrated in Fig. 11A, the connection configuration of the back gates is not shown. The electrical connection destination of the back gate can be determined at the design stage. For example, in a transistor having a back gate, the gate and the back gate may be electrically connected to increase the on-current of the transistor. For example, the gate and the back gate of transistor M2 may be electrically connected.

[0261] In addition, in a transistor having a back gate, an arbitrary potential may be applied to the back gate in order to vary the threshold voltage of the transistor or to reduce the off-current of the transistor. Note that the transistors M1 to M5 may be transistors without a back gate. That is, they may be transistors having a single gate structure. Also, some transistors may have a back gate and other transistors may not have a back gate. Note that these descriptions apply not only to the transistors described in FIG. 11A, but also to the transistors described in other parts of the specification or illustrated in other drawings.

[0262] Also, transistors of various structures can be used for the transistors according to an aspect of the present invention. Therefore, there is no limitation on the type of transistor to be used. As an example of a transistor, a transistor having single crystal silicon or a transistor having a non-single crystal semiconductor film typified by amorphous silicon, polycrystalline silicon, microcrystalline (also referred to as microcrystal, nanocrystal, semi-amorphous) silicon, etc. can be used. Alternatively, a thin film transistor (TFT) in which these semiconductors are thinned can be used. When using a TFT, there are various advantages. For example, since it can be manufactured at a lower temperature than in the case of single crystal silicon, it is possible to reduce the manufacturing cost or the size of the manufacturing apparatus. Since the manufacturing apparatus can be made larger, it can be manufactured on a large substrate. Therefore, since many display devices can be manufactured at the same time, it can be manufactured at low cost. Alternatively, since the manufacturing temperature is low, a substrate with weak heat resistance can be used. Therefore, a transistor can be manufactured on a substrate having translucency. Alternatively, the transmission of light in a display element can be controlled using a transistor on a substrate having translucency. Alternatively, since the film thickness of the transistor is thin, a part of the film forming the transistor can transmit light. Therefore, the aperture ratio can be improved.

[0263] In addition, as the semiconductor in which the channel of the transistor is formed, it is not limited to a single semiconductor composed of a single element as the main component, and compound semiconductors (for example, SiGe, GaAs, etc.), or oxide semiconductors (for example, Zn - O, In - Ga - Zn - O, In - Zn - O, In - Sn - O (ITO), Sn - O, Ti - O, Al - Zn - Sn - O (AZTO), In - Sn - Zn - O, etc.) can be used. Note that these semiconductor materials can be used not only as the semiconductor in which the channel of the transistor is formed, but also for other applications. For example, they can be used as resistance elements or electrodes having translucency. Since they can be formed or deposited simultaneously with the transistor, the manufacturing cost can be reduced.

[0264] In addition, as the semiconductor material, an organic semiconductor or a carbon nanotube can be used. By using these, a transistor can be formed on a substrate that can be bent. An apparatus using a transistor having an organic semiconductor or a carbon nanotube can be made resistant to impact.

[0265] In addition, as the transistor according to one aspect of the present invention, transistors having various structures can be used. For example, it can have various configurations such as a planar type, a FIN type (fin type), a TRI - GATE type (trigate type), a top - gate type, a bottom - gate type, a double - gate type (where gates are arranged above and below the channel), etc. Also, as the transistor according to one aspect of the present invention, a MOS type transistor, a junction type transistor, a bipolar transistor, etc. can be used. By using a MOS type transistor as the transistor, the occupied area of the transistor can be reduced. Therefore, a large number of transistors can be mounted. By using a bipolar transistor as the transistor, a large current can be made to flow. Therefore, the circuit can be operated at high speed. Note that a MOS type transistor and a bipolar transistor may be formed mixed on one substrate. Thereby, low power consumption, miniaturization, high - speed operation, etc. can be realized.

[0266] In the circuit MC of FIG. 11A, the first terminal (one of the source or drain) of the transistor M1 is electrically connected to the wiring VE. The second terminal (the other of the source or drain) of the transistor M1 is electrically connected to the first terminal of the transistor M3 and the first terminal of the transistor M4. The gate of the transistor M1 is electrically connected to the first terminal of the capacitor C1 (one of the pair of electrodes constituting the capacitor) and the first terminal of the transistor M2. The second terminal of the capacitor C1 (the other of the pair of electrodes constituting the capacitor) is electrically connected to the wiring VE. The second terminal of the transistor M2 is electrically connected to the wiring IL and the first terminal of the transistor M5. The gate of the transistor M2 is electrically connected to the wiring WL. The second terminal of the transistor M3 is electrically connected to the wiring OL, and the gate of the transistor M3 is electrically connected to the wiring X1L. The second terminal of the transistor M4 is electrically connected to the wiring OLB, and the gate of the transistor M4 is electrically connected to the wiring X2L. The second terminal of the transistor M5 is electrically connected to the second terminal of the transistor M1, the first terminal of the transistor M3, and the first terminal of the transistor M4. The gate of the transistor M5 is electrically connected to the wiring WL.

[0267] A connection configuration different from that of the circuit MC in the circuit MCr will be described. The second terminal of the transistor M3r is electrically connected to the wiring OLB instead of the wiring OL, and the second terminal of the transistor M4r is electrically connected to the wiring OL instead of the wiring OLB. The first terminal of the transistor M1r and the first terminal of the capacitor C1r are electrically connected to the wiring VEr.

[0268] The sizes such as the channel length and channel width of the transistors M1, M2, M3, M4, and M5 are preferably equal to the sizes of the transistors M1r, M2r, M3r, M4r, and M5r, respectively. With such a configuration, there is a possibility of efficient layout.

[0269] In the holding unit HC shown in FIG. 11A, the electrical connection point of the gate of the transistor M1, the first terminal of the capacitor C1, and the first terminal of the transistor M2 is defined as the node n1. Further, in the holding unit HCr, the electrical connection point of the gate of the transistor M1r, the second terminal of the capacitor C1r, and the first terminal of the transistor M2r is defined as the node n1r.

[0270] The holding unit HC has a function of holding a potential corresponding to the first data. Writing of the potential to the holding unit HC is performed by turning on the transistor M2 and turning off the transistor M5, and supplying a potential corresponding to the first data from the wiring IL to the node n1. Thereafter, by turning off the transistor M2, the potential corresponding to the first data is held at the node n1.

[0271] Similar to the holding unit HC, the holding unit HCr also has a function of holding a potential corresponding to the first data. Writing of the potential to the holding unit HCr is performed by turning on the transistor M2r and turning off the transistor M5r, and supplying a potential corresponding to the first data from the wiring ILB to the node n1r. Thereafter, by turning off the transistor M2r, the potential corresponding to the first data is held at the node n1r.

[0272] For the transistor M2, in order to hold the potential of the node n1 for a long time, it is preferable to apply a transistor with a small off-current. As the transistor with a small off-current, for example, an OS transistor can be used. Further, as the transistor M2, a transistor having a back gate may be applied, and a low-level potential or a negative voltage may be applied to the back gate to shift the threshold voltage to the positive side to reduce the off-current. The same applies to the transistor M2r.

[0273] Wiring VE and wiring VEr function as wirings for supplying a constant voltage. When the constant voltage is, for example, when transistor M3, transistor M3r, transistor M4, or transistor M4r is an n-channel transistor, it can be Vss, GND, or other low-level potential.

[0274] Also, the voltages supplied by wiring VE and wiring VEr may be different from each other or the same. Also, when the voltages supplied by the respective wirings are the same, those wirings may be shared.

[0275] Also, a modified example of the circuit MP in FIG. 11A is shown in FIG. 11B. In the circuit MP shown in FIG. 11B, the first terminal of transistor M5 is electrically connected to the first terminal of transistor M2, the gate of transistor M1, and the first terminal of capacitor C1. The circuit MP shown in FIG. 11B can operate in the same manner as the circuit MP shown in FIG. 11A.

[0276] Note that SRAM (Static Random Access Memory), phase change memory (PCM: Phase-Change Memory), resistive random access memory (ReRAM: Resistive Random Access Memory), magnetoresistive random access memory (MRAM: Magnetoresistive Random Access Memory), ferroelectric random access memory (FeRAM: Ferroelectric Random Access Memory), etc. may be used for the holding units HC and HCr that hold the first data which is a weight coefficient.

[0277] A modified example of the circuit MP shown in FIG. 11A is shown in FIG. 12. As shown in FIG. 12, one wiring may be used as the wiring OL or the wiring IL, and the other one wiring may be used as the wiring OLB or the wiring ILB. In addition, the configuration may be such that the wiring X2L, the transistors M4, M4r, M5, and M5r are not provided. In the circuit MP shown in FIG. 12, the second terminals of the transistor M2 and the transistor M3 are electrically connected to the wiring OL (wiring IL). Also, the second terminals of the transistor M2r and the transistor M3r are electrically connected to the wiring OLB (wiring ILB).

[0278] This embodiment can be appropriately combined with other embodiments shown in this specification and the like.

[0279] (Embodiment 3) The product-sum operation result obtained by the neuron is often output through an activation function. As the activation function, a linear ramp function (ReLU function), a sigmoid function, a step function, etc. are known. The AD conversion device 100 according to one aspect of the present invention can realize the function of the ReLU function in addition to the AD conversion function.

[0280] FIG. 13 is a flowchart for explaining the operation of the AD conversion device 100 with the function of the ReLU function added. Using FIG. 13, the operation of the AD conversion device 100 with the function of the ReLU function added will be explained. Since the operation example of the AD conversion device 100 has already been described in Embodiment 1, in this embodiment, the points different from the operation example described in Embodiment 1 will be described.

[0281] [Step S211] After the end of step S203b, it is determined whether (Yes) or not (No) to make the AD conversion device 100 function as a ReLU function. If it is not made to function as a ReLU function, after performing step S204b, step S205 is performed.

[0282] [Step S212] When the AD conversion device 100 functions as a ReLU function, (00000000)2 is set as the digital signal. Then, step S205 is performed.

[0283] In this way, when the differential current is negative (when the sign bit is 1), (100000000)2 is output as the signed digital signal regardless of the value of the differential current. When the differential current is positive (when the sign bit is 0), successive comparison is performed in the DA conversion unit 130b to generate a digital signal corresponding to the value of the differential current.

[0284] Figure 14A is a graph showing the change in the digital signal generated when the AD conversion device 100 functions as a ReLU function. The horizontal axis in Figure 14A represents the differential current, and the vertical axis represents the output digital signal (quantization value). Figure 14A shows that when the differential current is negative, 0 is output as the digital signal, and when the differential current is positive, a digital signal corresponding to the value of the differential current is output.

[0285] Since the AD conversion device 100 can also function as a ReLU function, there is no need to separately provide a ReLU function. Therefore, the semiconductor device including the AD conversion device 100 can reduce power consumption. Also, the semiconductor device including the AD conversion device 100 can reduce the occupied area.

[0286] Also, when the function of the ReLU function is added to the AD conversion device 100, since the operation of the DA conversion unit 130a is not performed, the power supply to the DA conversion unit 130a may be stopped (see Figure 14B). By stopping the power supply to the DA conversion unit 130a, the power consumption can be further reduced.

[0287] This embodiment can be appropriately combined with other embodiments shown in this specification and the like.

[0288] (Embodiment 4) In this embodiment, a configuration example of a display device to which the semiconductor device described in the above embodiment can be applied will be described. As an example, a configuration example in which the semiconductor device described in the above embodiment is applied to the AD conversion circuit of a display device will be described. A configuration in which the semiconductor device according to one aspect of the present invention is used for the AD conversion circuit of a display device is effective in reducing the occupied area and power consumption.

[0289] <Configuration Example of Display Device> FIG. 15 is a block diagram showing a configuration example of a display device. The display device 200 includes a pixel portion 210, a functional circuit 220A, and a peripheral circuit 220B.

[0290] The functional circuit 220A includes a CPU 230, a control circuit 231, a power supply circuit 232, an image processing circuit 233, and a memory 234.

[0291] The CPU 230 is a circuit for executing instructions and comprehensively controlling the display device 200. The instructions executed by the CPU 230 are instructions input from the outside and instructions stored in the internal memory. The CPU 230 generates signals for controlling the control circuit 231 and the image processing circuit 233. Based on the control signal of the CPU 230, the control circuit 231 controls the operation of the display device 200. The control circuit 231 controls the peripheral circuit 220B, the power supply circuit 232, the image processing circuit 233, and the memory 234 so that the processing determined by the CPU 230 is executed. Various synchronization signals for determining the timing of screen rewriting, for example, are input to the control circuit 231. Examples of the synchronization signals include a horizontal synchronization signal, a vertical synchronization signal, and a reference clock signal, etc., and the control circuit 231 generates a control signal for the peripheral circuit 220B from these signals. The power supply circuit 232 has a function of supplying a power supply voltage to the pixel portion 210 and the peripheral circuit 220B.

[0292] The pixel section 210 has a plurality of pixels 211, a plurality of wirings GL, a plurality of wirings SL, and a plurality of wirings ML. The plurality of pixels 211 are arranged in an array. The plurality of wirings GL, SL, and ML are provided according to the arrangement of the plurality of pixels 211. The wiring GL is arranged in the vertical direction. The wirings SL and ML are arranged in the horizontal direction. The wiring GL may be called a gate line, a scanning line, a selection signal line, etc. The wiring SL may be called a source line, a data line, etc. The wiring ML is a wiring provided for monitoring the pixel 211 and can be called, for example, a monitor wiring.

[0293] The peripheral circuit 220B has a gate driver circuit 221, a source driver circuit 222, a monitor circuit 223, and an AD conversion circuit 224.

[0294] The gate driver circuit 221 is a circuit for driving the wiring GL and has a function of generating a signal to be supplied to the wiring GL. The source driver circuit 222 is a circuit for driving the wiring SL and has a function of generating a signal to be supplied to the wiring SL. The monitor circuit 223 has a function of detecting an analog signal flowing through the wiring ML. The AD conversion circuit 224 is a circuit for converting the analog signal output from the monitor circuit 223 into a digital signal. The AD conversion circuit 224 outputs a signal CMOUT to the image processing circuit 233.

[0295] In the display device 200, the AD conversion device 100 of Embodiment 1 is applied to the AD conversion circuit 224. Therefore, the display device 200 is a display device in which the occupied area and the power consumption are reduced.

[0296] The image processing circuit 233 has a function of processing a video signal input from the outside to generate a data signal VDATA. The data signal VDATA is a digital signal representing gradation. Also, the image processing circuit 233 has a function of correcting the data signal VDATA using the signal CMOUT. The source driver circuit 222 has a function of processing the data signal VDATA to generate a data signal to be supplied to each wiring SL. The memory 234 is provided to store data necessary for the image processing circuit 233 to perform processing. For example, the signal CMOUT, the data signal VDATA, or a video signal input from the outside is stored in the memory 234.

[0297] Although the analog signal flowing through the wiring ML is a minute current of several nA to several 100 nA, by using the AD conversion device 100 of the first embodiment in the AD conversion circuit 224, the display device 200 can detect the analog signal with high precision and correct the data signal VDATA with high precision.

[0298] FIG. 16A is a schematic diagram for explaining the arrangement of the pixel portion 210, the functional circuit 220A, and the peripheral circuit 220B in the display device 200. In FIG. 16A, as an example, a display device 200 in which each component is provided across the layer 201 and the layer 202 is illustrated. In FIG. 16A, the layer 202 is provided by being laminated, for example, above the layer 201. Note that an interlayer insulator or a conductor for making an electrical connection between different layers can be provided between the layer 201 and the layer 202.

[0299] The transistor provided in layer 201 can be, for example, a transistor having silicon in the channel formation region (also referred to as an Si transistor), and can be, for example, a transistor having single-crystalline silicon in the channel formation region. In particular, when a transistor having single-crystalline silicon in the channel formation region is used as the transistor provided in layer 201, the on-current of the transistor can be increased. Therefore, since the circuit included in layer 201 can be driven at high speed, it is preferable. Further, since the Si transistor can be formed by microfabrication such that the channel length is 3 nm to 10 nm, a display device 200 provided with functional circuits such as a CPU, a GPU, and other accelerators, and an application processor can be used.

[0300] The transistor provided in layer 202 can be, for example, an OS transistor. In particular, as the OS transistor, it is preferable to use a transistor having an oxide containing at least one of indium, element M (element M is aluminum, gallium, yttrium, or tin), and zinc in the channel formation region. Such an OS transistor has the characteristic that the off-current is very low. Therefore, in particular, when an OS transistor is used as the transistor provided in the pixel circuit included in the display unit, it is preferable because the analog data written in the pixel circuit can be held for a long time.

[0301] A functional circuit 220A and a peripheral circuit 220B are provided in layer 201. The transistor 203 in layer 201 is an Si transistor having silicon in the channel formation region 205. The Si transistor can increase the on-current of the transistor. Therefore, the CPU 230, the control circuit 231, the power supply circuit 232, the image processing circuit 233, and the memory 234 included in the functional circuit 220A, and the gate driver circuit 221, the source driver circuit 222, the monitor circuit 223, and the AD conversion circuit 224 included in the peripheral circuit 220B can be driven at high speed.

[0302] The pixel portion 210 provided with a plurality of pixels 211 is provided in layer 202. The transistor 204 in layer 202 is an OS transistor having an oxide (oxide semiconductor) that functions as a semiconductor in the channel formation region 206. The OS transistor can hold the data written in the pixel 211 for a long period of time. Note that the pixel 211 functions as a sub-pixel whose emission of red, green, and blue light is controlled.

[0303] FIG. 16B shows a schematic diagram of a case where a part of the circuit included in the peripheral circuit 220B provided in layer 201 is provided in layer 202. FIG. 16B illustrates a configuration in which the gate driver circuit 221 and the source driver circuit 222 are provided in layer 202. Note that the source driver circuit 222 provided in layer 202 can be configured to include a demultiplexer in layer 202 that distributes signals output from the source driver 222 to the wiring SL.

[0304] <Configuration Example of Pixel> FIG. 17A is a circuit diagram showing an example of the pixel 211, and FIG. 17B is a timing chart showing an operation example of the pixel 211 shown in FIG. 17A.

[0305] FIG. 17A shows the pixel 211 disposed in the k-th row and the j-th column (k is an integer of 2 or more and m or less, and j is an integer of 2 or more and n or less). The pixel 211 is electrically connected to the wirings GL, SL, ML, and ANL. The pixel 211 includes transistors M25 to M27, a capacitor element C11, and a light-emitting element EL1. Note that in this specification and the like, the term “element” may be replaced with “device” in some cases. For example, a display element, a light-emitting element, and a liquid crystal element can be replaced with a display device, a light-emitting device, and a liquid crystal device, respectively.

[0306] The light-emitting element EL1 has a pair of terminals (anode and cathode). As the light-emitting element EL1, an element capable of controlling the luminance by current or voltage can be used. Representative examples of the light-emitting element EL1 include an LED (Light Emitting Diode) and an OLED (Organic Light Emitting Diode). For example, in the case of an OLED, the light-emitting element EL1 has an EL (electroluminescence) layer. The EL layer is provided between the anode and the cathode and is composed of a single layer or a plurality of layers. The EL layer includes at least a layer containing a light-emitting substance (light-emitting layer). A light-emitting element that uses the EL layer for light emission may be called an EL element. A display device in which an EL element is applied to a pixel may be called an EL display device. In particular, a light-emitting element having an organic EL layer may be called an organic EL element, and a display device using an organic EL element may be called an organic EL display device. Of course, the light-emitting element EL1 can be an organic EL element.

[0307] The transistors M25 to M27 shown in FIG. 17A can be OS transistors. The transistors M25 to M27 may be Si transistors for some or all of them. Also, in FIG. 17A, the transistors M25 to M27 are n-channel transistors, but some or all of them may be p-channel transistors. Further, the transistors M25 to M27 have a back gate electrically connected to the gate. By adopting such a device structure, the current driving ability of the transistors M25 to M27 can be improved. Some or all of the transistors M25 to M27 may be transistors without a back gate.

[0308] Transistor M25 is a pass transistor that connects between the gate (node N12) of transistor M26 and wiring SL. Transistor M27 is a pass transistor that connects between wiring ML and the anode (node N11) of light-emitting element EL1. Transistor M26 is a drive transistor and functions as a current source supplied to light-emitting element EL1. The luminance of light-emitting element EL1 is adjusted according to the magnitude of the drain current of transistor M26. Capacitive element C11 is a holding capacitor that holds the voltage between node N11 and node N12.

[0309] Next, an operation example of pixel 211 will be described. A voltage Vda, which is a data signal, is input to wiring SL. Voltage Vda is a voltage corresponding to the gradation of the video signal. [k] and [k + 1] in FIG. 17B represent the data signals Vda input to the pixels 211 in the k-th row and the (k + 1)-th row, respectively.

[0310] Period P1 is a writing operation period, and light-emitting element EL1 does not emit light. A voltage Vano is applied to wiring ANL, and a voltage Vcat is applied to the cathode of light-emitting element EL1. Wiring ML is electrically connected to a power supply line that supplies voltage V0. Wiring GL is set to a high level to turn on transistors M25 and M26. The voltage Vda of wiring SL is applied to node N12. A drain current corresponding to voltage Vda flows through transistor M26.

[0311] Note that voltage Vano, voltage V0, and voltage Vcat are preferably set to satisfy the following equations (b1)-(b3). In the following equations, voltage V thE is the threshold voltage of light-emitting element EL1, and voltage V th2 is the threshold voltage of transistor M26. V0 < Vcat + V thE (b1) Vano > V0 + V thE (b2) Vano > Vcat + V thE + V th2 (b3)

[0312] By being (b1) and (b2), even when the transistor M27 is on during the period P1 (writing period), the drain current of the transistor M26 can preferentially flow through the wiring ML rather than the light-emitting element EL1. By satisfying (b3), a potential difference is generated between the wiring ANL and the cathode of the light-emitting element EL1 during the period P2 (light-emitting period), so that the drain current of the transistor M26 is supplied to the light-emitting element EL1, and the light-emitting element EL1 can be caused to emit light. During the period P2, the transistors M25 and M27 are turned off.

[0313] The period P3 is a monitor period for acquiring the drain current of the transistor M26. The transistors M25 and M27 are turned on. Also, the electrical connection between the wiring ML and the power supply line supplying the voltage V0 is cut off. A voltage higher than the voltage V is applied to the wiring SL. A voltage Vano is applied to the wiring ANL, and a voltage Vcat is applied to the cathode of the light-emitting element EL1. By driving the wiring SL and the like in this way, the drain current of the transistor M26 can preferentially flow through the wiring ML rather than the light-emitting element EL1. th2 The signal I output from the pixel 211 to the wiring ML during the period P3 includes the drain current flowing through the transistor M26 during the light-emitting period. By analyzing the signal I and correcting the voltage Vda of the data signal based on the analysis result, the deviation in the luminance of the pixel 211 can be corrected.

[0314] It is not necessary to always perform the monitor operation after the light-emitting operation. For example, in the pixel 211, the monitor operation can be performed after repeating the data writing operation and the light-emitting operation cycle a plurality of times. Also, after performing the monitor operation, a data signal corresponding to the minimum gradation value 0 can be written to the pixel 211 to make the light-emitting element EL1 in a non-light-emitting state. MON The signal I MON includes the drain current flowing through the transistor M26 during the light-emitting period. By analyzing the signal I and correcting the voltage Vda of the data signal based on the analysis result, the deviation in the luminance of the pixel 211 can be corrected.

[0315] It is not necessary to always perform the monitor operation after the light-emitting operation. For example, in the pixel 211, the monitor operation can be performed after repeating the data writing operation and the light-emitting operation cycle a plurality of times. Also, after performing the monitor operation, a data signal corresponding to the minimum gradation value 0 can be written to the pixel 211 to make the light-emitting element EL1 in a non-light-emitting state.

[0316] The signal I MONis input into the monitor circuit 223 shown in FIG. 15. The monitor circuit 223 has a function of controlling the output to the AD conversion circuit 224 of the signal I MON The AD conversion circuit 224 has a function of controlling the output to the AD conversion circuit 224 of the signal I

[0317] <Method for forming a light-emitting element> Hereinafter, a method for forming the light-emitting element EL1 provided in each of the pixels 211 included in the pixel portion 210 will be described.

[0318] FIG. 18A shows a schematic top view of the light-emitting elements EL_R, EL_G, and EL_B applicable to the light-emitting element EL1. The light-emitting element EL_R is a light-emitting element that emits red light, the light-emitting element EL_G is a light-emitting element that emits green light, and the light-emitting element EL_B is a light-emitting element that emits blue light. In FIG. 18A, for the sake of simplicity in distinguishing each light-emitting element, the symbols R, G, and B are attached to the light-emitting regions of the respective light-emitting elements. Note that the configuration shown in FIG. 18A may be referred to as an SBS (Side By Side) structure. In addition, although the configuration shown in FIG. 18A is exemplified for a configuration having three colors of red (R), green (G), and blue (B), it is not limited thereto. For example, a configuration having four or more colors may be used.

[0319] The light-emitting elements EL_R, EL_G, and EL_B are each arranged in a matrix. FIG. 18A shows a so-called stripe arrangement in which light-emitting elements of the same color are arranged in one direction. Note that the arrangement method of the light-emitting elements is not limited to this, and an arrangement method such as a delta arrangement or a zigzag arrangement may be applied, or a pentile arrangement may be used.

[0320] As the light-emitting elements EL_R, EL_G, and EL_B, it is preferable to use an organic EL device such as an OLED (Organic Light Emitting Diode) or a QLED (Quantum-dot Light Emitting Diode). Examples of the light-emitting substances included in the EL elements are substances that emit fluorescence (fluorescent materials), substances that emit phosphorescence (phosphorescent materials), inorganic compounds (such as quantum dot materials), and substances that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) materials).

[0321] FIG. 18B is a schematic cross-sectional view corresponding to the dashed-dotted line A1-A2 in FIG. 18A.

[0322] FIG. 18B shows cross-sections of the light-emitting elements EL_R, EL_G, and EL_B. The light-emitting elements EL_R, EL_G, and EL_B are each provided on the insulating layer 251 and have a conductor 252 that functions as a pixel electrode and a conductor 254 that functions as a common electrode.

[0323] The light-emitting element EL_R has an EL layer 253R between the conductor 252 and the conductor 254. The EL layer 253R contains a light-emitting organic compound that emits light having intensity in at least the red wavelength range. The EL layer 253G of the light-emitting element EL_G contains a light-emitting organic compound that emits light having intensity in at least the green wavelength range. The EL layer 253B of the light-emitting element EL_B contains a light-emitting organic compound that emits light having intensity in at least the blue wavelength range.

[0324] Each of the EL layer 253R, the EL layer 253G, and the EL layer 253B may have one or more of an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer in addition to the layer containing a light-emitting organic compound (light-emitting layer).

[0325] The conductor 252 is provided for each light-emitting element. Further, the conductor 254 is provided as a continuous layer common to each light-emitting element. A conductive film having translucency to visible light is used for either one of the conductor 252 and the conductor 254 that functions as a common electrode, and a conductive film having reflectivity is used for the other. By making the conductor 252 translucent and the conductor 254 reflective, a bottom emission type display device can be obtained. Conversely, by making the conductor 252 reflective and the conductor 254 translucent, a top emission type display device can be obtained. Note that by making both the conductor 252 and the conductor 254 translucent, a dual emission type display device can also be obtained.

[0326] An insulating layer 255 is provided to cover the end of the conductor 252. The end of the insulating layer 255 is preferably tapered.

[0327] The EL layer 253R, the EL layer 253G, and the EL layer 253B each have a region in contact with the upper surface of the conductor 252 and a region in contact with the surface of the insulating layer 255. Further, the ends of the EL layer 253R, the EL layer 253G, and the EL layer 253B are located on the insulating layer 255.

[0328] As shown in FIG. 18B, a gap is provided between two EL layers between light-emitting elements of different colors. Thus, it is preferable that the EL layer 253R, the EL layer 253G, and the EL layer 253B are provided so as not to contact each other. Thereby, current can flow through two adjacent EL layers, and unintentional light emission (also referred to as crosstalk) can be suitably prevented. Therefore, the contrast can be increased, and a display device with high display quality can be realized.

[0329] The EL layer 253R, the EL layer 253G, and the EL layer 253B can be separately fabricated by a vacuum deposition method using a shadow mask such as a metal mask or the like. Alternatively, they may be separately fabricated by a photolithography method. By using the photolithography method, a display device with high definition, which is difficult to achieve when using a metal mask, can be realized.

[0330] Further, a protective layer 256 is provided on the conductor 254 so as to cover the light-emitting elements EL_R, EL_G, and EL_B. The protective layer 256 has a function of preventing impurities such as water from diffusing into each light-emitting element from above.

[0331] The protective layer 256 can have, for example, a single-layer structure or a laminated structure including at least an inorganic insulating film. Examples of the inorganic insulating film include oxide films or nitride films such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum oxynitride film, and a hafnium oxide film. Alternatively, a semiconductor material such as indium gallium oxide or indium gallium zinc oxide may be used as the protective layer 256. The protective layer 256 may be formed using an ALD method, a CVD method, or a sputtering method. Although the configuration including an inorganic insulating film is exemplified as the protective layer 256, it is not limited thereto. For example, the protective layer 256 may have a laminated structure of an inorganic insulating film and an organic insulating film.

[0332] FIG. 18C shows an example different from the above.

[0333] In FIG. 18C, there is a light-emitting element EL_W that exhibits white light. The light-emitting element EL_W has an EL layer 253W that exhibits white light between the conductor 252 and the conductor 254.

[0334] As the EL layer 253W, for example, it can be configured by laminating two or more light-emitting layers selected such that their respective emission colors are in a complementary color relationship. Also, a stacked EL layer in which a charge generation layer is sandwiched between the light-emitting layers, that is, an EL layer having a so-called tandem structure, may be used. Note that by adopting a tandem structure, a light-emitting element capable of high-brightness emission can be obtained.

[0335] FIG. 18C shows three light-emitting elements EL_W arranged side by side. A coloring layer 257R is provided above the left light-emitting element EL_W. The coloring layer 257R functions as a band-pass filter that transmits red light. Similarly, a coloring layer 257G that transmits green light is provided above the central light-emitting element EL_W, and a coloring layer 257B that transmits blue light is provided above the right light-emitting element EL_W. Thereby, the display device can display a color image.

[0336] Here, between two adjacent light-emitting elements EL_W, the EL layer 253W and the conductor 254 are separated from each other. Thereby, in two adjacent light-emitting elements EL_W, current can be prevented from flowing through the EL layer 253W and causing unintended light emission. In particular, when a stacked EL element in which a charge generation layer is provided between two light-emitting layers is used as the EL layer 253W, the higher the fineness, that is, the smaller the distance between adjacent pixels, the more significant the influence of crosstalk, and there is a problem that the contrast decreases. Therefore, by adopting such a configuration, a display device having both high fineness and high contrast can be realized.

[0337] The separation of the EL layer 253W and the conductor 254 is preferably performed by a photolithography method. Thereby, since the interval between the light-emitting elements can be narrowed, for example, a display device with a high aperture ratio can be realized as compared with the case where a shadow mask such as a metal mask is used.

[0338] In the case of a bottom emission type light-emitting element, a coloring layer may be provided between the conductor 252 and the insulating layer 251.

[0339] FIG. 18D shows an example different from the above. Specifically, FIG. 18D has a configuration in which the insulating layer 255 is not provided between the light-emitting element EL_R, the light-emitting element EL_G, and the light-emitting element EL_B. By adopting such a configuration, a display device with a high aperture ratio can be obtained. Further, the protective layer 256 is configured to cover the side surfaces of the light-emitting element EL_R, the light-emitting element EL_G, and the light-emitting element EL_B. By adopting such a configuration, impurities (typically water, etc.) that can enter from the side surfaces of the light-emitting element EL_R, the light-emitting element EL_G, and the light-emitting element EL_B can be suppressed. Further, in the configuration shown in FIG. 18D, the upper surface shapes of the conductor 252, the EL layer 253R, and the conductor 254 are substantially the same. Such a structure can be formed collectively using a resist mask or the like after forming the conductor 252, the EL layer 253R, and the conductor 254. Such a process can also be called self-aligned patterning because the EL layer 253R and the conductor 252 are processed using the conductor 254 as a mask. Although the light-emitting element EL_R has been described here, the light-emitting element EL_G and the light-emitting element EL_B can have the same configuration.

[0340] Further, in FIG. 18D, there is a structure in which a further protective layer 258 is provided on the protective layer 256. For example, the protective layer 256 is formed using a device capable of forming a film with high covering properties (typically an ALD device, etc.), and the protective layer 258 is formed using a device in which a film with lower covering properties than the protective layer 256 is formed (typically a sputtering device, etc.), so that a gap 259 can be provided between the protective layer 256 and the protective layer 258. In other words, the gap 259 is located between the light-emitting element EL_R and the light-emitting element EL_G, and between the light-emitting element EL_G and the light-emitting element EL_B.

[0341] Note that the void 259 has any one or more selected from, for example, air, nitrogen, oxygen, carbon dioxide, and Group 18 elements (typically, helium, neon, argon, xenon, krypton, etc.). Further, the void 259 may contain, for example, a gas used when forming the protective layer 258. For example, when forming the protective layer 258 by sputtering, the void 259 may contain any one or more of the above Group 18 elements. When the void 259 contains a gas, the gas can be identified by a gas chromatography method or the like. Alternatively, when forming the protective layer 258 by sputtering, the gas used during sputtering may also be contained in the film of the protective layer 258. In this case, when the protective layer 258 is analyzed by energy-dispersive X-ray analysis (EDX analysis) or the like, an element such as argon may be detected.

[0342] Further, when the refractive index of the void 259 is lower than the refractive index of the protective layer 256, light emitted from the light-emitting element EL_R, the light-emitting element EL_G, or the light-emitting element EL_B is reflected at the interface between the protective layer 256 and the void 259. Thereby, it is possible to suppress the light emitted from the light-emitting element EL_R, the light-emitting element EL_G, or the light-emitting element EL_B from entering an adjacent pixel. Thereby, since mixing of light of different colors can be suppressed, the image quality of the display device can be improved.

[0343] In the case of the structure shown in FIG. 18D, the region between the light-emitting element EL_R and the light-emitting element EL_G, or the region between the light-emitting element EL_G and the light-emitting element EL_B (hereinafter simply referred to as the distance between the light-emitting elements) can be narrowed. Specifically, the distance between the light-emitting elements can be 1 μm or less, preferably 500 nm or less, more preferably 200 nm or less, 100 nm or less, 90 nm or less, 70 nm or less, 50 nm or less, 30 nm or less, 20 nm or less, 15 nm or less, or 10 nm. In other words, it has a region where the distance between the side surface of the light-emitting element EL_R and the side surface of the light-emitting element EL_G, or the distance between the side surface of the light-emitting element EL_G and the side surface of the light-emitting element EL_B is 1 μm or less, preferably a region of 0.5 μm (500 nm) or less, and more preferably a region of 100 nm or less.

[0344] Also, for example, when the void 259 has air, the structure shown in FIG. 18D can be referred to as an air isolation structure. By having the air isolation structure, it is possible to suppress color mixing or crosstalk of light from each light-emitting element while separating the elements from each other.

[0345] FIG. 19A shows an example different from the above. Specifically, the structure shown in FIG. 19A is different from the structure shown in FIG. 18D in the structure of the insulating layer 251. The insulating layer 251 has a recess with a part of its upper surface being shaved off during the processing of the light-emitting element EL_R, the light-emitting element EL_G, and the light-emitting element EL_B. A protective layer 256 is formed in the recess. In other words, in a cross-sectional view, it has a region where the lower surface of the protective layer 256 is located lower than the lower surface of the conductor 252. By having this region, it is possible to preferably suppress impurities (typically water, etc.) that can enter the light-emitting element EL_R, the light-emitting element EL_G, and the light-emitting element EL_B from below. The above-mentioned recess can be formed when removing impurities (also referred to as residue) that can adhere to the side surfaces of the respective light-emitting elements during the processing of the light-emitting element EL_R, the light-emitting element EL_G, and the light-emitting element EL_B by wet etching or the like. After removing the above-mentioned residue, by covering the side surfaces of each light-emitting element with the protective layer 256, a highly reliable display device can be obtained.

[0346] Further, FIG. 19B shows an example different from the above. Specifically, the configuration shown in FIG. 19B has, in addition to the configuration shown in FIG. 19A, an insulating layer 276 and a microlens array 277. The insulating layer 276 functions as an adhesive layer. When the refractive index of the insulating layer 276 is lower than the refractive index of the microlens array 277, the microlens array 277 can condense the light emitted from the light-emitting element EL_R, the light-emitting element EL_G, and the light-emitting element EL_B. Thereby, the light extraction efficiency of the display device can be improved. In particular, when the user views the display surface from the front of the display surface of the display device, a bright image can be visually recognized, which is preferable. As the insulating layer 276, various curable adhesives such as a photocurable adhesive such as an ultraviolet curable type, a reaction curable adhesive, a thermosetting adhesive, and an anaerobic adhesive can be used. Examples of these adhesives include epoxy resin, acrylic resin, silicone resin, phenol resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. In particular, a material with low moisture permeability such as epoxy resin is preferable. Also, a two-component mixed resin may be used. Further, an adhesive sheet or the like may be used.

[0347] <Configuration Example 1 of AD Conversion Circuit Having AD Conversion Device 100> FIG. 20 is a circuit diagram showing a configuration example of an AD conversion circuit 224 including the AD conversion device 100 described in Embodiment 1. The AD conversion circuit 224 includes a plurality of transistors M1 (M1[1] to M1[N], where N is a natural number of 1 or more), a plurality of AD conversion devices 100 (100[1] to 100[N]), a plurality of TRIBUF (tri-state buffer circuits) 262, and a circuit SR (shift register).

[0348] Hereinafter, the transistor M1 will be described as an n-channel type transistor, but one aspect of the present invention can also be applied when the transistor M1 is a p-channel type transistor.

[0349] The signal I shown in FIG. 20 MON (I MON [1] to I MON [N]) includes, as information, the value of the current (analog signal) flowing through the pixel 211 of the display device 200. The AD conversion device 100 has a function of converting these signals I MON into digital signals and outputting them as signal CMOUT.

[0350] Also, the signal I shown in FIG. 20 TEST includes, as information, the value of the reference current (analog signal). The AD conversion device 100 has a function of reading the difference between signal I MON and signal I TEST and outputting the difference as signal CMOUT.

[0351] Signal I TEST is input to the AD conversion device 100 via the transistor M1. Also, signal I MON is input to the AD conversion device 100. Note that signals I MON , I TEST can handle not only the current flowing from the external pixel into the AD conversion device 100 but also the current flowing from the AD conversion device 100 into the external pixel.

[0352] The AD conversion device 100 has a function of converting the input analog signal into a digital signal, signal OUT (signals OUT_1 to OUT_N), and outputting it.

[0353] Also, the circuit SR is a shift register and has a function of selecting one of the signals OUT_1 to OUT_N. The signals SP and SCLK shown in FIG. 20 represent the pulse signal and the clock signal input to the circuit SR, respectively.

[0354] The circuit SR outputs a plurality of signals SEL (SEL[1] to SEL[N]). Among the signals SEL[1] to SEL[N], one signal becomes High level (hereinafter, H level), and the remaining N - 1 signals become Low level (L level). The signal SEL that becomes H level turns on the transistor M1 and makes the TRIBUF262 conductive. On the other hand, the signal SEL that becomes L level turns off the transistor M1 and makes the TRIBUF262 in a high impedance state. Also, the AD conversion device 100 can be switched between an operable state and a standby state according to the signal SEL. In this way, the signal I TEST selected by the circuit SR is input to the AD conversion device 100, and the signal OUT selected by the circuit SR is output to the outside as the signal CMOUT.

[0355] For example, consider the case where the signal SEL[1] becomes H level. At this time, a H level potential is applied to the gate of the transistor M1[1], and the transistor M1[1] turns on. On the other hand, a L level potential is applied to the gates of the transistors M1[2] to M1[N], and the transistors M1[2] to M1[N] turn off. As a result, only the transistor M1[1] turns on, and the signal I TEST is input to the AD conversion device 100[1]. Also, only the signal OUT_1 is output to the outside as the signal CMOUT. Thereafter, by repeating the operations based on the plurality of signals SEL, the signal I MON or the signal I TEST corresponding signal OUT can be output as the signal CMOUT.

[0356] Note that, in this embodiment, an example of handling 8-bit data is shown, but it is not limited thereto. One aspect of the present invention can also handle data of arbitrary k bits (k is a natural number of 1 or more).

[0357] In the AD conversion circuit 224, the transistor M1 is preferably an OS transistor with a small off-current.

[0358] In a display device including a transistor with a small pixel size and a light-emitting element described with reference to FIGS. 18A to 18C, the current flowing through the light-emitting element is small, and correction within the pixel is difficult. In an AD conversion circuit including a semiconductor device according to an aspect of the present invention, it is possible to detect a minute current with high accuracy. Therefore, high-precision correction of the current flowing through the display element can be performed.

[0359] <Configuration Example 2 of AD Conversion Circuit Having AD Conversion Device 100> FIG. 21 is a circuit diagram showing a configuration example of an AD conversion circuit 224 including the AD conversion device 100 described in Embodiment 1 having a configuration different from that of FIG. 20. The AD conversion circuit 224 includes a plurality of transistors M1 (M1[1] to M1[N], where N is a natural number of 1 or more), the AD conversion device 100, and a circuit SR (shift register).

[0360] In FIG. 21, a signal I MON is input to the AD conversion device 100 via the transistor M1. Also, the signal I TEST is input to the AD conversion device 100.

[0361] The AD conversion device 100 has a function of outputting an input analog signal as a digital signal, a signal CMOUT.

[0362] The circuit SR outputs a plurality of signals SEL (SEL[1] to SEL[N]). Among the signals SEL[1] to SEL[N], one signal becomes High level (hereinafter, H level), and the remaining N - 1 signals become Low level (L level). The signal SEL that has become H level turns on the transistor M1. On the other hand, the signal SEL that has become L level turns off the transistor M1. Also, the AD conversion device 100 can be switched between an operable state and a standby state according to any one of the plurality of signals SEL. In this way, the signal I MON selected by the circuit SR is input to the AD conversion device 100, and the signal CMOUT selected by the circuit SR is output to the outside.

[0363] For example, consider the case where signal SEL[1] becomes the H level. At this time, an H-level potential is applied to the gate of transistor M1[1], and transistor M1[1] turns on. On the other hand, an L-level potential is applied to the gates of transistors M1[2] to M1[N], and transistors M1[2] to M1[N] turn off. As a result, only transistor M1[1] turns on, and signal I MON is input to the AD conversion device 100, and signal CMOUT is output from the AD conversion device 100 to the outside. Thereafter, by repeating the operations based on a plurality of signals SEL, signal I MON or signal I TEST can output a signal CMOUT corresponding thereto.

[0364] By using this configuration, in a display device including a semiconductor device, miniaturization or high integration can be achieved.

[0365] This embodiment can be appropriately combined with other embodiments shown in this specification and the like.

[0366] (Embodiment 5) In this embodiment, a configuration example of a transistor applicable to the semiconductor device described in the above embodiment will be described. As an example, a configuration in which transistors having different electrical characteristics are stacked will be described. By adopting such a configuration, the design freedom of the semiconductor device can be increased. Further, by stacking transistors having different electrical characteristics, the integration degree of the semiconductor device can be increased.

[0367] A partial cross-sectional structure of a semiconductor device is shown in FIG. 22. The semiconductor device shown in FIG. 22 includes a transistor 500, a transistor 550, and a capacitor element 600. In FIG. 22, the capacitor element 600 is shown in a parallel-plate type, but the shape of the capacitor element 600 is not limited to this. The capacitor element 600 may be, for example, a cylinder type. FIG. 23A is a top view of the transistor 500. FIG. 23B is a cross-sectional view taken along the portion L1-L2 indicated by the dashed line in FIG. 23A, and is a cross-sectional view in the channel length direction of the transistor 500. FIG. 23C is a cross-sectional view taken along the portion W1-W2 indicated by the dashed line in FIG. 23A, and is a cross-sectional view in the channel width direction of the transistor 500. For example, the transistor 500 corresponds to an OS transistor applicable to the transistor shown in the above embodiment, that is, a transistor having an oxide semiconductor in the channel formation region. Also, the transistor 550 corresponds to a Si transistor applicable to the transistor shown in the above embodiment, that is, a transistor having silicon in the channel formation region.

[0368] The transistor 500 is an OS transistor. The OS transistor has an extremely small off-current. Therefore, it is possible to hold the data voltage or charge written to the memory node via the transistor 500 for a long period of time. That is, since the refresh operation frequency of the memory node can be reduced or the refresh operation is not required, the power consumption of the semiconductor device can be reduced.

[0369] In FIG. 22, the transistor 500 is provided above the transistor 550, and the capacitor element 600 is provided above the transistor 550 and the transistor 500.

[0370] The transistor 550 is provided on a substrate 371. The substrate 371 is, for example, a p-type silicon substrate. The substrate 371 may also be an n-type silicon substrate. The oxide layer 374 is preferably an insulating layer (also referred to as a BOX layer) formed of a buried oxide in the substrate 371, for example, silicon oxide. The transistor 550 is provided on a single-crystalline silicon, so-called SOI (Silicon On Insulator) substrate provided on the substrate 371 via the oxide layer 374.

[0371] In the SOI substrate, an insulator 373 that functions as an element isolation layer is provided on the substrate 371. The substrate 371 also has a well region 372. The well region 372 is a region to which n-type or p-type conductivity is imparted according to the conductivity type of the transistor 550. In the single-crystalline silicon in the SOI substrate, a semiconductor region 375, low-resistance regions 376a and 376b that function as a source region or a drain region are provided. Also, a low-resistance region 376c is provided on the well region 372.

[0372] The transistor 550 can be provided overlapping a well region 372 to which an impurity element for imparting conductivity is added. The well region 372 can function as a bottom gate electrode of the transistor 550 by independently changing the potential via the low-resistance region 376c. Therefore, the threshold voltage of the transistor 550 can be controlled. In particular, by applying a negative potential to the well region 372, the threshold voltage of the transistor 550 can be made larger and the off-current can be reduced. Therefore, by applying a negative potential to the well region 372, the drain current when the potential applied to the gate electrode of the Si transistor is 0V can be made smaller. As a result, the power consumption based on the through-current or the like in the arithmetic circuit having the transistor 550 can be reduced, and the arithmetic efficiency can be improved.

[0373] The transistor 550 is preferably of a so-called Fin type in which the upper surface of the semiconductor layer and the side surfaces in the channel width direction are covered with the conductor 378 via the insulator 377. By making the transistor 550 of the Fin type, the effective channel width increases, thereby improving the on characteristics of the transistor 550. In addition, since the contribution of the electric field of the gate electrode can be increased, the off characteristics of the transistor 550 can be improved.

[0374] Note that the transistor 550 may be either a p-channel type transistor or an n-channel type transistor.

[0375] The conductor 378 may function as a first gate (also referred to as a top gate) electrode. Also, the well region 372 may function as a second gate (also referred to as a back gate or a bottom gate) electrode. In that case, the potential applied to the well region 372 can be controlled via the low resistance region 376c.

[0376] In the region where the channel of the semiconductor region 375 is formed, the region in the vicinity thereof, the source region, or the drain region, the low resistance regions 376a and 376b, and the low resistance region 376c connected to the electrode for controlling the potential of the well region 372, etc., it is preferable to include a semiconductor such as a silicon-based semiconductor, and it is preferable to include single crystal silicon. Alternatively, it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), etc. A configuration using silicon in which stress is applied to the crystal lattice and the effective mass is controlled by changing the lattice spacing may also be used. Alternatively, by using GaAs and GaAlAs, etc., the transistor 550 may be a HEMT.

[0377] The well region 372, the low resistance regions 376a, 376b, and 376c include elements that impart n-type conductivity such as arsenic and phosphorus, or elements that impart p-type conductivity such as boron, in addition to the semiconductor material applied to the semiconductor region 375.

[0378] The conductor 378 functioning as a gate electrode can be made of a semiconductor material such as silicon containing an element imparting n-type conductivity such as arsenic or phosphorus, or an element imparting p-type conductivity such as boron, a metal material, an alloy material, or a conductive material such as a metal oxide material. Further, the conductor 378 may be made of a silicide such as nickel silicide.

[0379] Since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride and / or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten and / or aluminum as a laminate for the conductor, and it is particularly preferable to use tungsten from the viewpoint of heat resistance.

[0380] The low-resistance regions 376a, 376b, and 376c may be configured by laminating another conductor, for example, a silicide such as nickel silicide. By adopting such a configuration, the conductivity of the region functioning as an electrode can be enhanced. Further, at this time, an insulator functioning as a sidewall spacer (also referred to as a sidewall insulating layer) may be provided on the side surface of the conductor 378 functioning as a gate electrode and on the side surface of the insulator functioning as a gate insulating film. By adopting such a configuration, it is possible to prevent the conductor 378 and the low-resistance regions 376a and 376b from being in a conductive state.

[0381] Over the transistor 550, insulators 379, 381, 383, and 385 are sequentially laminated and provided.

[0382] As the insulators 379, 381, 383, and 385, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, etc. may be used.

[0383] In this specification and the like, "oxynitride" refers to a material having a higher oxygen content than nitrogen in its composition, and "nitride oxide" refers to a material having a higher nitrogen content than oxygen in its composition. For example, in this specification and the like, silicon oxynitride refers to a material having a higher oxygen content than nitrogen in its composition, and silicon nitride oxide refers to a material having a higher nitrogen content than oxygen in its composition.

[0384] The insulator 381 may have a function as a planarization film that planarizes a step formed by a transistor 550 or the like provided below it. For example, the upper surface of the insulator 381 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance flatness.

[0385] Further, for the insulator 383, it is preferable to use a film having a barrier property that prevents hydrogen and impurities from diffusing from the substrate 371 or the transistor 550 or the like into the region where the transistor 500 is provided.

[0386] As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element having an oxide semiconductor such as the transistor 500, the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the transistor 550. Specifically, the film that suppresses the diffusion of hydrogen is a film having a small amount of hydrogen desorption.

[0387] The amount of hydrogen desorption can be analyzed using, for example, temperature-programmed desorption gas analysis (TDS). For example, the amount of hydrogen desorption from the insulator 383 is such that in the TDS analysis, in the range where the surface temperature of the film is from 50°C to 500°C, the desorption amount converted to hydrogen atoms, per unit area of the insulator 383, is 10×10 15 atoms / cm 2 or less, preferably 5×10 15 atoms / cm 2 or less.

[0388] Note that the insulator 385 preferably has a lower dielectric constant than the insulator 383. For example, the relative dielectric constant of the insulator 385 is preferably less than 4, more preferably less than 3. Also, for example, the relative dielectric constant of the insulator 385 is preferably 0.7 times or less, more preferably 0.6 times or less, of the relative dielectric constant of the insulator 383. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced.

[0389] Also, a capacitor element 600, or conductors 328 and 330 connected to the transistor 500, etc. are embedded in the insulator 379, insulator 381, insulator 383, and insulator 385. Note that the conductors 328 and 330 have the function of a plug or a wiring. Also, conductors having the function of a plug or a wiring may be given the same reference numeral when summarizing a plurality of configurations. Also, in this specification, etc., a wiring and a plug connected to the wiring may be an integral body. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.

[0390] As the material of each plug and wiring (conductors 328, 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used alone or in a laminated form. It is preferable to use a high melting point material such as tungsten or molybdenum that combines heat resistance and conductivity, and it is preferable to use tungsten. Or, it is preferably formed of a low-resistance conductive material such as aluminum or copper. By using a low-resistance conductive material, the wiring resistance can be lowered.

[0391] A wiring layer may be provided on the insulator 385 and the conductor 330. For example, in FIG. 22, the insulators 350, 352, and 354 are sequentially stacked and provided. Further, a conductor 356 is formed on the insulators 350, 352, and 354. The conductor 356 has a function as a plug connected to the transistor 550 or a wiring. Note that the conductor 356 can be provided using the same material as the conductors 328 and 330.

[0392] Note that, for example, as the insulator 350, it is preferable to use an insulator having a barrier property against hydrogen, similar to the insulator 383. Further, the conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 350 having a barrier property against hydrogen. With this configuration, the transistor 550 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0393] Note that, as the conductor having a barrier property against hydrogen, for example, tantalum nitride or the like may be used. Further, by laminating tantalum nitride and tungsten having high conductivity, diffusion of hydrogen from the transistor 550 can be suppressed while maintaining the conductivity as a wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen.

[0394] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, in FIG. 22, the insulators 360, 362, and 364 are sequentially stacked and provided. Further, a conductor 366 is formed on the insulators 360, 362, and 364. The conductor 366 has a function as a plug or a wiring. Note that the conductor 366 can be provided using the same material as the conductors 328 and 330.

[0395] Note that, for example, the insulator 360 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 383. Further, the conductor 366 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in the opening of the insulator 360 having a barrier property against hydrogen. With this configuration, the transistor 550 and the transistor 500 can be separated by a barrier layer, and the diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0396] A wiring layer may be provided on the insulator 364 and the conductor 366. For example, in FIG. 22, the insulator 370, the insulator 369, and the insulator 368 are sequentially stacked and provided. Further, a conductor 376 is formed in the insulator 370, the insulator 369, and the insulator 368. The conductor 376 has a function as a plug or a wiring. Note that the conductor 376 can be provided using the same materials as the conductor 328 and the conductor 330.

[0397] Note that, for example, the insulator 370 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 383. Further, the conductor 376 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in the opening of the insulator 370 having a barrier property against hydrogen. With this configuration, the transistor 550 and the transistor 500 can be separated by a barrier layer, and the diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0398] A wiring layer may be provided on the insulator 368 and the conductor 376. For example, in FIG. 22, the insulator 380, the insulator 382, and the insulator 384 are provided in a stacked manner in sequence. Further, a conductor 386 is formed on the insulator 380, the insulator 382, and the insulator 384. The conductor 386 has a function as a plug or a wiring. Note that the conductor 386 can be provided using the same material as the conductor 328 and the conductor 330.

[0399] Note that, for example, it is preferable to use an insulator having a barrier property against hydrogen for the insulator 380 in the same manner as the insulator 383. Further, the conductor 386 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 380 having a barrier property against hydrogen. With this configuration, the transistor 550 and the transistor 500 can be separated by a barrier layer, and the diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0400] In the above, the wiring layer including the conductor 356, the wiring layer including the conductor 366, the wiring layer including the conductor 376, and the wiring layer including the conductor 386 have been described, but the semiconductor device according to the present embodiment is not limited thereto. The number of wiring layers similar to the wiring layer including the conductor 356 may be three or less, or may be five or more.

[0401] On the insulator 384, an insulator 510, an insulator 512, an insulator 514, and an insulator 516 are provided in a stacked manner in sequence. It is preferable to use a material having a barrier property against oxygen and hydrogen for any of the insulator 510, the insulator 512, the insulator 514, and the insulator 516.

[0402] For example, for the insulator 510 and the insulator 514, it is preferable to use a film having a barrier property against hydrogen and impurities in, for example, a region where the substrate 371 or the transistor 550 is provided, in the region where the transistor 500 is provided. Therefore, the same material as that of the insulator 383 can be used.

[0403] As an example of a film having a barrier property against hydrogen, silicon nitride formed by CVD method can be used. Here, when hydrogen diffuses into a semiconductor element having an oxide semiconductor such as the transistor 500, the characteristics of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the transistor 500 and the transistor 550.

[0404] Also, as a film having a barrier property against hydrogen, for example, for the insulator 510 and the insulator 514, it is preferable to use metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide.

[0405] In particular, aluminum oxide has a high blocking effect of not allowing the film to permeate both oxygen and impurities such as hydrogen and moisture that are factors causing fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent the incorporation of impurities such as hydrogen and moisture into the transistor 500 during and after the manufacturing process of the transistor. In addition, it is possible to suppress the release of oxygen from the oxide constituting the transistor 500. Therefore, it is suitable to be used as a protective film for the transistor 500.

[0406] Also, for example, for the insulator 512 and the insulator 516, the same material as that of the insulator 379 can be used. In addition, by applying a material having a relatively low dielectric constant to these insulators, the parasitic capacitance generated between the wirings can be reduced. For example, as the insulator 512 and the insulator 516, a silicon oxide film or a silicon oxynitride film can be used.

[0407] In addition, conductors such as the conductor 518 and the conductor (e.g., conductor 503) constituting the transistor 500 are embedded in the insulators 510, 512, 514, and 516. Note that the conductor 518 functions as a plug connected to the capacitor element 600 or the transistor 550, or as a wiring. The conductor 518 can be provided using the same material as the conductors 328 and 330.

[0408] In particular, the conductor 518 in the regions in contact with the insulator 510 and the insulator 514 is preferably a conductor having barrier properties against oxygen, hydrogen, and water. With this configuration, the transistor 550 and the transistor 500 can be separated by a layer having barrier properties against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0409] A transistor 500 is provided above the insulator 516.

[0410] As shown in FIGS. 23A to 23C, the transistor 500 includes a conductor 503 arranged to be embedded in the insulators 514 and 516, an insulator 520 arranged on the insulator 516 and the conductor 503, an insulator 522 arranged on the insulator 520, an insulator 524 arranged on the insulator 522, an oxide 530a arranged on the insulator 524, an oxide 530b arranged on the oxide 530a, conductors 542a and 542b arranged separately from each other on the oxide 530b, an insulator 580 arranged on the conductors 542a and 542b and having an opening formed by overlapping between the conductor 542a and the conductor 542b, an insulator 545 arranged on the bottom surface and the side surface of the opening, and a conductor 560 arranged on the formation surface of the insulator 545.

[0411] Also, as shown in FIGS. 23B and 23C, it is preferable that an insulator 544 is disposed between the oxides 530a, 530b, the conductors 542a, 542b, and the insulator 580. Further, as shown in FIGS. 23A to 23C, the conductor 560 preferably includes a conductor 560a provided inside the insulator 545 and a conductor 560b provided so as to be embedded inside the conductor 560a. Also, as shown in FIGS. 23B and 23C, it is preferable that an insulator 574 is disposed on the insulator 580, the conductor 560, and the insulator 545.

[0412] Note that in this specification and the like, the oxides 530a and 530b may be collectively referred to as the oxide 530.

[0413] Note that in the transistor 500, a configuration in which two layers of the oxides 530a and 530b are laminated in a region where a channel is formed and in the vicinity thereof is shown, but the present invention is not limited thereto. For example, a single layer of the oxide 530b or a laminated configuration of three or more layers may be provided.

[0414] Also, in the transistor 500, the conductor 560 is shown as a two-layer laminated configuration, but the present invention is not limited thereto. For example, the conductor 560 may have a single-layer configuration or a laminated configuration of three or more layers. Also, the transistor 500 shown in FIGS. 22 and 23A to 23C is an example and is not limited to its configuration, and an appropriate transistor may be used according to the circuit configuration, driving method, and the like.

[0415] Here, the conductor 560 functions as the gate electrode of the transistor 500, and the conductors 542a and 542b function as the source electrode or the drain electrode, respectively. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542a and the conductor 542b. The arrangement of the conductor 560, the conductor 542a, and the conductor 542b is self-alignedly selected with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be self-alignedly arranged between the source electrode and the drain electrode. Therefore, the conductor 560 can be formed without providing an alignment margin, so that the occupied area of the transistor 500 can be reduced. Thereby, miniaturization and high integration of the semiconductor device can be achieved.

[0416] Furthermore, since the conductor 560 is self-alignedly formed in the region between the conductor 542a and the conductor 542b, the conductor 560 does not have a region overlapping with the conductor 542a or the conductor 542b. Thereby, the parasitic capacitance formed between the conductor 560, the conductor 542a, and the conductor 542b can be reduced. Therefore, the switching speed of the transistor 500 can be improved, and high frequency characteristics can be achieved.

[0417] The conductor 560 may function as a first gate (also referred to as a gate or a top gate) electrode. Also, the conductor 503 may function as a second gate (also referred to as a back gate or a bottom gate) electrode. In that case, the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently without linking it to the potential applied to the conductor 560. In particular, by applying a negative potential to the conductor 503, the threshold voltage of the transistor 500 can be made larger and the off-current can be reduced. Therefore, applying a negative potential to the conductor 503 can make the drain current smaller when the potential applied to the conductor 560 is 0V than when no negative potential is applied.

[0418] The conductor 503 is arranged to overlap with the oxide 530 and the conductor 560. Thus, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected, and the channel formation region formed in the oxide 530 can be covered.

[0419] In this specification and the like, the configuration of a transistor in which a channel formation region is electrically surrounded by the electric fields of a pair of gate electrodes (a first gate electrode and a second gate electrode) is referred to as a surrounded channel (S-channel) configuration. Further, the S-channel configuration disclosed in this specification and the like is different from the Fin type configuration and the planar type configuration. By adopting the S-channel configuration, it is possible to enhance the resistance to the short-channel effect, in other words, to obtain a transistor in which the short-channel effect hardly occurs.

[0420] Also, the conductor 503 has the same configuration as the conductor 518. A conductor 503a is formed in contact with the inner walls of the openings of the insulator 514 and the insulator 516, and a conductor 503b is further formed inside. Note that in the transistor 500, a configuration in which the conductor 503a and the conductor 503b are stacked is shown, but the present invention is not limited to this. For example, the conductor 503 may be provided in a single layer or a stacked configuration of three or more layers.

[0421] Here, it is preferable to use a conductive material in which the conductor 503a has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the above impurities are difficult to permeate). Alternatively, it is preferable to use a conductive material in which the conductor 503a has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (the above oxygen is difficult to permeate). Note that in this specification, the function of suppressing the diffusion of impurities or oxygen means the function of suppressing the diffusion of any one or all of the above impurities or the above oxygen.

[0422] For example, since the conductor 503a has a function of suppressing the diffusion of oxygen, it is possible to suppress the oxidation of the conductor 503b and the decrease in the conductivity.

[0423] Further, when the conductor 503 also serves as a wiring, it is preferable to use a highly conductive material mainly composed of tungsten, copper, or aluminum for the conductor 503b. In the present embodiment, the conductor 503 is illustrated as a laminate of the conductor 503a and the conductor 503b, but the conductor 503 may have a single-layer structure.

[0424] The insulators 520, 522, and 524 have a function as a second gate insulating film.

[0425] Here, it is preferable to use an insulator containing more oxygen than oxygen satisfying the stoichiometric composition for the insulator 524 in contact with the oxide 530. The oxygen is likely to be released from the film by heating. In this specification and the like, oxygen released by heating may be referred to as "excess oxygen". That is, it is preferable that a region containing excess oxygen (also referred to as an "excess oxygen region") is formed in the insulator 524. By providing such an insulator containing excess oxygen in contact with the oxide 530, oxygen vacancies (V O : also referred to as oxygen vacancy) in the oxide 530 can be reduced, and the reliability of the transistor 500 can be improved. When hydrogen enters the oxygen vacancy in the oxide 530, the defect (hereinafter, may be referred to as V O H) may function as a donor, and electrons as carriers may be generated. In addition, a part of hydrogen may combine with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen tends to have normally-on characteristics. Further, since hydrogen in the oxide semiconductor is likely to move due to stress such as heat and an electric field, if the oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may deteriorate. In one aspect of the present invention, V in the oxide 530 OIt is preferable to reduce H as much as possible to achieve high-purity true or substantially high-purity true. Thus, V O To obtain an oxide semiconductor with sufficiently reduced H, it is important to remove impurities such as moisture and hydrogen in the oxide semiconductor (also referred to as "dehydration" or "dehydrogenation treatment"), and to supply oxygen to the oxide semiconductor to compensate for oxygen deficiencies (also referred to as "oxygen addition treatment"). V O By using an oxide semiconductor with sufficiently reduced impurities such as H in the channel formation region of a transistor, stable electrical characteristics can be imparted.

[0426] As the insulator having an excess oxygen region, specifically, it is preferable to use an oxide material in which some oxygen desorbs upon heating. The oxide that desorbs oxygen upon heating is such that, in TDS (Thermal Desorption Spectroscopy) analysis, the desorption amount of oxygen in terms of oxygen atoms is 1.0×10 18 atoms / cm 3 or more, preferably 1.0×10 19 atoms / cm 3 or more, more preferably 2.0×10 19 atoms / cm 3 or more, or 3.0×10 20 atoms / cm 3 or more, and it is an oxide film. The surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or more and 700°C or less, or 100°C or more and 400°C or less.

[0427] Also, the insulator having the excess oxygen region and the oxide 530 may be subjected to any one or more of heat treatment, microwave treatment, or RF treatment in contact with each other. By performing such treatment, water or hydrogen in the oxide 530 can be removed. For example, in the oxide 530, a reaction occurs in which the VoH bond is cleaved, in other words, "V OThe reaction of "H→Vo + H" occurs, enabling dehydrogenation. Some of the hydrogen generated at this time may combine with oxygen to form H2O and be removed from the oxide 530 or the insulator near the oxide 530. Also, some of the hydrogen may be gettered by the conductor 542a and the conductor 542b.

[0428] In addition, the microwave treatment is preferably performed using, for example, a device having a power source for generating high-density plasma or a device having a power source for applying RF to the substrate side. For example, by using a gas containing oxygen and high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 530 or the insulator near the oxide 530. Also, the microwave treatment may be performed at a pressure of 133 Pa or more, preferably 200 Pa or more, more preferably 400 Pa or more. As the gas introduced into the device for performing the microwave treatment, for example, oxygen and argon are used, and the oxygen flow ratio (O2 / (O2 + Ar)) is 50% or less, preferably 10% or more and 30% or less.

[0429] During the manufacturing process of the transistor 500, it is preferable to perform a heat treatment with the surface of the oxide 530 exposed. The heat treatment may be performed, for example, at 100°C or higher and 450°C or lower, more preferably 350°C or higher and 400°C or lower. The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 530 to create oxygen vacancies (V OReduction of ) can be achieved. Further, the heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas after heat treatment in an atmosphere of nitrogen gas or an inert gas, in order to supplement the desorbed oxygen. Alternatively, after heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, heat treatment may be continuously performed in an atmosphere of nitrogen gas or an inert gas.

[0430] Note that by performing an oxygen addition treatment on the oxide 530, the oxygen deficiency in the oxide 530 can be repaired with the supplied oxygen, in other words, the reaction of "Vo + O → null" can be promoted. Further, by reacting the supplied oxygen with the hydrogen remaining in the oxide 530, the hydrogen can be removed (dehydrated) as H2O. As a result, it is possible to suppress the recombination of the hydrogen remaining in the oxide 530 with the oxygen deficiency to form V O H.

[0431] Further, when the insulator 524 has an excess oxygen region, it is preferable that the insulator 522 has a function of suppressing the diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.) (the oxygen is difficult to permeate).

[0432] It is preferable that the insulator 522 has a function of suppressing the diffusion of oxygen and impurities, so that the oxygen in the oxide 530 does not diffuse to the insulator 520 side. Further, it is possible to suppress the reaction of the conductor 503 with the oxygen in the insulator 524 and the oxide 530.

[0433] The insulator 522 preferably uses, as a single layer or a laminate, an insulator containing a so-called high-k material such as aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulating film. By using a high-k material for the insulator functioning as the gate insulating film, it becomes possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0434] In particular, it is advisable to use an insulator containing one or both oxides of aluminum and hafnium, which is an insulating material having a function of suppressing the diffusion of impurities and oxygen (such that the above-mentioned oxygen is difficult to permeate). As the insulator containing one or both oxides of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses the release of oxygen from the oxide 530 and the incorporation of impurities such as hydrogen from the peripheral portion of the transistor 500 into the oxide 530.

[0435] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. It is also possible to use a laminate of silicon oxide, silicon oxynitride, or silicon nitride on the above-mentioned insulator.

[0436] In addition, the insulator 520 is preferably thermally stable. For example, silicon oxide and silicon oxynitride are suitable because they are thermally stable. Further, by combining an insulator of a high-k material with silicon oxide or silicon oxynitride, an insulator 520 having a laminated structure that is thermally stable and has a high relative permittivity can be obtained.

[0437] Note that in the transistor 500 of FIGS. 23A to 23C, the insulators 520, 522, and 524 are illustrated as a second gate insulating film having a three-layer laminated structure, but the second gate insulating film may have a single-layer, two-layer, or four-layer or more laminated structure. In that case, it is not limited to a laminated structure made of the same material, and a laminated structure made of different materials may also be used.

[0438] The transistor 500 uses a metal oxide that functions as an oxide semiconductor for an oxide 530 including a channel formation region. For example, as the oxide 530, a metal oxide such as an In-M-Zn oxide (the element M is selected from one or more of aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc.) may be used.

[0439] The formation of the metal oxide that functions as an oxide semiconductor may be performed by a sputtering method or an ALD (Atomic Layer Deposition) method. Note that the metal oxide that functions as an oxide semiconductor will be described in detail in other embodiments.

[0440] In addition, for the metal oxide that functions as a channel formation region in the oxide 530, it is preferable to use a metal oxide having a band gap of preferably 2 eV or more, more preferably 2.5 eV or more. Thus, by using a metal oxide having a large band gap, the off-current of the transistor can be reduced.

[0441] By having the oxide 530a under the oxide 530b, the oxide 530 can suppress the diffusion of impurities from the components formed below the oxide 530a to the oxide 530b.

[0442] Note that the oxide 530 preferably has a laminated structure of a plurality of oxide layers with different atomic ratios of each metal atom. Specifically, in the metal oxide used for the oxide 530a, the atomic ratio of the element M in the constituent elements is preferably larger than the atomic ratio of the element M in the constituent elements in the metal oxide used for the oxide 530b. Also, in the metal oxide used for the oxide 530a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 530b. Further, in the metal oxide used for the oxide 530b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 530a.

[0443] Also, it is preferable that the energy of the lower end of the conduction band of the oxide 530a is higher than the energy of the lower end of the conduction band of the oxide 530b. In other words, it is preferable that the electron affinity of the oxide 530a is smaller than the electron affinity of the oxide 530b.

[0444] Here, at the junction of the oxide 530a and the oxide 530b, the energy level of the lower end of the conduction band changes smoothly. In other words, the energy level of the lower end of the conduction band at the junction of the oxide 530a and the oxide 530b can also be said to change continuously or be continuously joined. To achieve this, it is advisable to lower the defect level density of the mixed layer formed at the interface between the oxide 530a and the oxide 530b.

[0445] Specifically, by having a common element (as the main component) other than oxygen in the oxide 530a and the oxide 530b, a mixed layer with a low defect level density can be formed. For example, when the oxide 530b is an In-Ga-Zn oxide, it is advisable to use an In-Ga-Zn oxide, a Ga-Zn oxide, gallium oxide, etc. as the oxide 530a.

[0446] At this time, the main path of the carrier becomes the oxide 530b. By configuring the oxide 530a as described above, the density of defect energy levels at the interface between the oxide 530a and the oxide 530b can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-current.

[0447] On the oxide 530b, a conductor 542a and a conductor 542b that function as a source electrode and a drain electrode are provided. As the conductor 542a and the conductor 542b, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, or an alloy containing the above-described metal element as a component, or an alloy combining the above-described metal elements, etc. are preferably used. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. Further, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when absorbing oxygen. Furthermore, a metal nitride film such as tantalum nitride is preferable because it has a barrier property against hydrogen or oxygen.

[0448] In addition, in FIG. 23B, although the conductors 542a and 542b are shown as a single-layer structure, they may also be a laminated structure of two or more layers. For example, a tantalum nitride film and a tungsten film may be laminated. Also, a titanium film and an aluminum film may be laminated. Further, a two-layer structure in which an aluminum film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, and a two-layer structure in which a copper film is laminated on a tungsten film may be used.

[0449] In addition, there are a three-layer structure in which a titanium film or a titanium nitride film is laminated with an aluminum film or a copper film on top of the titanium film or the titanium nitride film, and then a titanium film or a titanium nitride film is formed thereon, and a three-layer structure in which a molybdenum film or a molybdenum nitride film is laminated with an aluminum film or a copper film on top of the molybdenum film or the molybdenum nitride film, and then a molybdenum film or a molybdenum nitride film is formed thereon. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

[0450] Also, as shown in FIG. 23B, regions 543a and 543b may be formed as low-resistance regions at the interface between the oxide 530 and the conductor 542a (conductor 542b) and in the vicinity thereof. At this time, region 543a functions as one of the source region or the drain region, and region 543b functions as the other of the source region or the drain region. Also, a channel formation region is formed in the region sandwiched between region 543a and region 543b.

[0451] By providing the conductor 542a (conductor 542b) in contact with the oxide 530, the oxygen concentration in region 543a (region 543b) may be reduced. Also, a metal compound layer containing the metal contained in the conductor 542a (conductor 542b) and the components of the oxide 530 may be formed in region 543a (region 543b). In such a case, the carrier density in region 543a (region 543b) increases, and region 543a (region 543b) becomes a low-resistance region.

[0452] The insulator 544 is provided to cover the conductor 542a and the conductor 542b, and suppresses the oxidation of the conductor 542a and the conductor 542b. At this time, the insulator 544 may be provided to cover the side surface of the oxide 530 and be in contact with the insulator 524.

[0453] As the insulator 544, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, etc. can be used. Further, as the insulator 544, silicon oxynitride or silicon nitride can also be used.

[0454] In particular, as the insulator 544, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc., which are insulators containing one or both oxides of aluminum or hafnium. In particular, hafnium aluminate has higher heat resistance than the hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize in the heat treatment in the subsequent process. When the conductor 542a and the conductor 542b are made of a material having oxidation resistance or a material whose conductivity does not significantly decrease even when oxygen is absorbed, the insulator 544 is not an essential component. It may be appropriately designed according to the required transistor characteristics.

[0455] By providing the insulator 544, the phenomenon that impurities such as water and hydrogen contained in the insulator 580 diffuse into the oxide 530b can be suppressed. Further, the oxidation of the conductor 542 (conductor 542a and conductor 542b) caused by the excess oxygen of the insulator 580 can be suppressed.

[0456] The insulator 545 functions as a first gate insulating film. The insulator 545 is preferably formed using an insulator that contains excess oxygen and releases oxygen by heating, similar to the insulator 524 described above.

[0457] Specifically, silicon oxide with excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, and silicon oxide with pores can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0458] By providing an insulator containing excess oxygen as insulator 545, oxygen can be effectively supplied from insulator 545 to the channel formation region of oxide 530b. Also, similar to insulator 524, it is preferable that the concentration of impurities such as water or hydrogen in insulator 545 is reduced. The film thickness of insulator 545 is preferably 1 nm or more and 20 nm or less. Also, the above-described microwave treatment may be performed before and / or after the formation of insulator 545.

[0459] Further, in order to efficiently supply the excess oxygen possessed by insulator 545 to oxide 530, a metal oxide may be provided between insulator 545 and conductor 560. It is preferable that the metal oxide suppresses the diffusion of oxygen from insulator 545 to conductor 560. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of excess oxygen from insulator 545 to conductor 560 is suppressed. That is, it is possible to suppress a decrease in the amount of excess oxygen supplied to oxide 530. Also, oxidation of conductor 560 by excess oxygen can be suppressed. As the metal oxide, a material that can be used for insulator 544 may be used.

[0460] Note that insulator 545 may have a stacked structure, similar to the second gate insulating film. As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulating film. Therefore, by forming an insulator that functions as a gate insulating film with a stacked structure of a high-k material and a thermally stable material, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. Also, a stacked structure that is thermally stable and has a high relative dielectric constant can be formed.

[0461] The conductor 560 that functions as the first gate electrode is shown as a two-layer structure in FIGS. 23B and 23C, but it may be a single-layer structure or a laminated structure of three or more layers.

[0462] For the conductor 560a, it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N2O, NO, NO2), and copper atoms. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). Since the conductor 560a has a function of suppressing the diffusion of oxygen, it is possible to suppress the conductor 560b from being oxidized by the oxygen contained in the insulator 545 and the conductivity from decreasing. As the conductive material having a function of suppressing the diffusion of oxygen, for example, it is preferable to use tantalum, tantalum nitride, ruthenium, or ruthenium oxide. Also, as the conductor 560a, an oxide semiconductor applicable to the oxide 530 can be used. In that case, by forming the conductor 560b by sputtering, the electrical resistance value of the conductor 560a can be decreased to make it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0463] Also, for the conductor 560b, it is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum. Also, since the conductor 560b also functions as a wiring, it is preferable to use a conductor having high conductivity. For example, a conductive material mainly composed of tungsten, copper, or aluminum can be used. Also, the conductor 560b may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0464] Insulator 580 is provided on conductor 542a and conductor 542b via insulator 544. Insulator 580 preferably has an excess oxygen region. For example, as insulator 580, it is preferable to have silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores, or resin. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, silicon oxide and silicon oxide having pores are preferable because an excess oxygen region can be easily formed in a later process.

[0465] Insulator 580 preferably has an excess oxygen region. By providing insulator 580 that releases oxygen upon heating, oxygen in insulator 580 can be efficiently supplied to oxide 530. Note that it is preferable that the concentration of impurities such as water or hydrogen in insulator 580 is reduced.

[0466] The opening of insulator 580 is formed to overlap the region between conductor 542a and conductor 542b. Thereby, conductor 560 is formed to be embedded in the opening of insulator 580 and the region sandwiched between conductor 542a and conductor 542b.

[0467] When miniaturizing a semiconductor device, it is required to shorten the gate length, but it is necessary to prevent the conductivity of conductor 560 from decreasing. Therefore, if the film thickness of conductor 560 is increased, conductor 560 can have a high aspect ratio shape. In the present embodiment, since conductor 560 is provided to be embedded in the opening of insulator 580, even if conductor 560 has a high aspect ratio shape, it can be formed without collapsing conductor 560 during the process.

[0468] Insulator 574 is preferably provided in contact with the upper surface of insulator 580, the upper surface of conductor 560, and the upper surface of insulator 545. By forming insulator 574 by sputtering, an excess oxygen region can be provided in insulator 545 and insulator 580. Thereby, oxygen can be supplied from the excess oxygen region into oxide 530.

[0469] For example, as insulator 574, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium can be used.

[0470] In particular, aluminum oxide has high barrier properties and can suppress the diffusion of hydrogen and nitrogen even in a thin film of 0.5 nm or more and 3.0 nm or less. Therefore, aluminum oxide formed by sputtering can function as an oxygen supply source and also as a barrier film for impurities such as hydrogen.

[0471] Also, it is preferable to provide insulator 581 that functions as an interlayer film on insulator 574. Similar to insulator 524 and the like, insulator 581 preferably has a reduced concentration of impurities such as water or hydrogen in the film.

[0472] Also, conductor 540a and conductor 540b are arranged in the openings formed in insulator 581, insulator 574, insulator 580, and insulator 544. Conductor 540a and conductor 540b are provided to face each other with conductor 560 interposed therebetween. Conductor 540a and conductor 540b have the same configuration as conductor 546 and conductor 548 described later.

[0473] An insulator 582 is provided on an insulator 581. It is preferable to use a material that is barrier - resistant to oxygen and hydrogen for the insulator 582. Therefore, the same material as that of the insulator 514 can be used for the insulator 582. For example, it is preferable to use metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide for the insulator 582.

[0474] In particular, aluminum oxide has a high blocking effect that does not allow the film to permeate both oxygen and impurities such as hydrogen and moisture that are factors causing fluctuations in the electrical characteristics of transistors. Therefore, aluminum oxide can prevent the mixing of impurities such as hydrogen and moisture into the transistor 500 during and after the manufacturing process of the transistor. Also, it can suppress the release of oxygen from the oxides constituting the transistor 500. Therefore, it is suitable for use as a protective film for the transistor 500.

[0475] An insulator 586 is provided on the insulator 582. The same material as that of the insulator 379 can be used for the insulator 586. Also, by applying a material with a relatively low dielectric constant to these insulators, the parasitic capacitance generated between the wirings can be reduced. For example, as the insulator 586, a silicon oxide film or a silicon oxynitride film can be used.

[0476] Conductors 546 and 548, etc., are embedded in the insulator 520, insulator 522, insulator 524, insulator 544, insulator 580, insulator 574, insulator 581, insulator 582, and insulator 586.

[0477] The conductor 546 and the conductor 548 function as plugs connected to the capacitor element 600, the transistor 500, or the transistor 550, or as wirings. The conductor 546 and the conductor 548 can be provided using the same materials as the conductor 328 and the conductor 330.

[0478] Also, after the formation of the transistor 500, an opening may be formed so as to surround the transistor 500, and an insulator having a high barrier property against hydrogen or water may be formed so as to cover the opening. By wrapping the transistor 500 with the above-described insulator having a high barrier property, it is possible to prevent moisture and hydrogen from entering from the outside. Alternatively, a plurality of transistors 500 may be collectively wrapped with an insulator having a high barrier property against hydrogen or water. When forming an opening so as to surround the transistor 500, for example, an opening reaching the insulator 522 or the insulator 514 is formed, and the above-described insulator having a high barrier property is formed so as to contact the insulator 522 or the insulator 514. This is preferable because it can also serve as part of the manufacturing process of the transistor 500. As the insulator having a high barrier property against hydrogen or water, for example, the same material as the insulator 522 or the insulator 514 may be used.

[0479] Subsequently, a capacitor element 600 is provided above the transistor 500. The capacitor element 600 includes a conductor 610, a conductor 620, and an insulator 630.

[0480] Also, a conductor 612 may be provided on the conductor 546 and the conductor 548. The conductor 612 functions as a plug or wiring connected to the transistor 500. The conductor 610 functions as an electrode of the capacitor element 600. Note that the conductor 612 and the conductor 610 can be formed simultaneously.

[0481] For the conductor 612 and the conductor 610, a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, scandium, or a metal nitride film (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film, etc.) composed of the above-described elements can be used. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon oxide can also be applied.

[0482] In the present embodiment, the conductor 612 and the conductor 610 are shown in a single-layer configuration, but the present invention is not limited to this configuration, and a laminated configuration of two or more layers may be used. For example, a conductor having a barrier property, and a conductor having high adhesiveness to a conductor having a barrier property and a conductor having high conductivity may be formed between a conductor having a barrier property and a conductor having high conductivity.

[0483] The insulator 630 can be formed using the same material as other insulators. Further, a material having ferroelectricity may be used as the insulator 630. Examples of the material having ferroelectricity include a mixed crystal of hafnium oxide and zirconium oxide (also referred to as "HZO"), or a material obtained by adding an element X (the element X is silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) to hafnium oxide. Further, a piezoelectric ceramic having a perovskite structure may be used as the insulator 630. For example, as the material having ferroelectricity, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate may be used.

[0484] A conductor 620 is provided so as to overlap with a conductor 610 via an insulator 630. Note that the conductor 620 can be formed of a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high melting point material such as tungsten or molybdenum that achieves both heat resistance and conductivity, and it is particularly preferable to use tungsten. When forming simultaneously with other components such as conductors, a low resistance metal material such as Cu (copper) or Al (aluminum) may be used.

[0485] An insulator 640 is provided on the conductor 620 and the insulator 630. The insulator 640 can be formed using the same material as the insulator 379. Further, the insulator 640 may function as a planarization film that covers the uneven shape below it.

[0486] By using this configuration, in a semiconductor device using a transistor having an oxide semiconductor, miniaturization or high integration can be achieved.

[0487] This embodiment can be appropriately combined with other embodiments shown in this specification and the like.

[0488] (Embodiment 6) In this embodiment, a metal oxide (hereinafter also referred to as an oxide semiconductor) that can be used for the OS transistor described in the above embodiment will be described.

[0489] The metal oxide preferably contains either indium or zinc. It is particularly preferable to contain indium and zinc. In addition to those, it is preferable to contain aluminum, gallium, yttrium, tin, and the like. Further, one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like may be contained.

[0490] <Classification of crystal structures> First, the classification of the crystal structure in the oxide semiconductor will be described with reference to FIG. 24A. FIG. 24A is a diagram for explaining the classification of the crystal structure of an oxide semiconductor, typically an IGZO (metal oxide containing In, Ga, and Zn).

[0491] As shown in FIG. 24A, the oxide semiconductor is roughly classified into "Amorphous", "Crystalline", and "Crystal". Further, "completely amorphous" is included in "Amorphous". Further, CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (Cloud-Aligned Composite) are included in "Crystalline". Note that single crystal, poly crystal, and completely amorphous are excluded from the classification of "Crystalline". Further, single crystal and poly crystal are included in "Crystal".

[0492] Note that the structure within the thick frame shown in FIG. 24A is an intermediate state between "Amorphous" and "Crystal", and belongs to a new boundary region (New crystalline phase). That is, the structure can be rephrased as a structure completely different from "Crystal" and the energetically unstable "Amorphous".

[0493] Note that the crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum. Here, the XRD spectrum obtained from grazing-incidence XRD (GIXD) measurement of the CAAC-IGZO film classified as "Crystalline" is shown in FIG. 24B. Note that the GIXD method is also referred to as the thin-film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained from the GIXD measurement shown in FIG. 24B will be simply referred to as the XRD spectrum. Note that the composition of the CAAC-IGZO film shown in FIG. 24B is in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio]. Also, the thickness of the CAAC-IGZO film shown in FIG. 24B is 500 nm.

[0494] As shown in FIG. 24B, peaks indicating clear crystallinity are detected in the XRD spectrum of the CAAC-IGZO film. Specifically, in the XRD spectrum of the CAAC-IGZO film, a peak indicating c-axis orientation is detected in the vicinity of 2θ = 31°. Note that, as shown in FIG. 24B, the peak in the vicinity of 2θ = 31° is asymmetric about the angle at which the peak intensity was detected.

[0495] Also, the crystal structure of the film or substrate can be evaluated by the diffraction pattern (also referred to as the nano-beam electron diffraction pattern) observed by the nano-beam electron diffraction method (NBED). The diffraction pattern of the CAAC-IGZO film is shown in FIG. 24C. FIG. 24C is a diffraction pattern observed by NBED in which the electron beam is incident parallel to the substrate. Note that the composition of the CAAC-IGZO film shown in FIG. 24C is in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio]. Also, in the nano-beam electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0496] As shown in FIG. 24C, a plurality of spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0497] <<Structure of Oxide Semiconductor>> Note that when focusing on the crystal structure, an oxide semiconductor may be classified differently from that in FIG. 24A. For example, oxide semiconductors can be divided into single crystal oxide semiconductors and other non-single crystal oxide semiconductors. Examples of non-single crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. In addition, non-single crystal oxide semiconductors include polycrystalline oxide semiconductors, pseudo-amorphous oxide semiconductors (a-like OS: amorphous-like oxide semiconductor), amorphous oxide semiconductors, and the like.

[0498] Here, the details of the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described.

[0499] [CAAC-OS] CAAC-OS is an oxide semiconductor having a plurality of crystal regions, and the c-axes of the plurality of crystal regions are oriented in a specific direction. Note that the specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. In addition, a crystal region is a region having periodicity in the atomic arrangement. Note that when the atomic arrangement is regarded as a lattice arrangement, a crystal region is also a region where the lattice arrangements are aligned. Furthermore, CAAC-OS has a region where a plurality of crystal regions are connected in the a-b plane direction, and this region may have strain. Note that strain refers to a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangements are aligned and another region where the lattice arrangements are aligned in a region where a plurality of crystal regions are connected. That is, CAAC-OS is an oxide semiconductor in which the c-axis is oriented and there is no obvious orientation in the a-b plane direction.

[0500] Note that each of the plurality of crystal regions is composed of one or a plurality of minute crystals (crystals having a maximum diameter of less than 10 nm). When a crystal region is composed of one minute crystal, the maximum diameter of the crystal region is less than 10 nm. In addition, when a crystal region is composed of a large number of minute crystals, the size of the crystal region may be about several tens of nm.

[0501] In addition, in an In-M-Zn oxide (where element M is one or more selected from aluminum, gallium, yttrium, tin, titanium, etc.), CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as the In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter referred to as the (M,Zn) layer) are laminated. Note that indium and element M are mutually substitutable. Therefore, the (M,Zn) layer may contain indium. Also, the In layer may contain element M. Note that the In layer may also contain Zn. The layered structure is observed as a lattice image, for example, in a high-resolution TEM image.

[0502] When performing structural analysis on the CAAC-OS film using, for example, an XRD apparatus, in an Out-of-plane XRD measurement using a θ / 2θ scan, a peak indicating c-axis orientation is detected at 2θ = 31° or in the vicinity thereof. Note that the position (the value of 2θ) of the peak indicating c-axis orientation may vary depending on the type and composition of the metal elements constituting CAAC-OS.

[0503] Also, for example, in the electron diffraction pattern of the CAAC-OS film, a plurality of bright spots (spots) are observed. Note that one spot and another spot are observed at point-symmetric positions with the spot of the incident electron beam transmitted through the sample (also referred to as the direct spot) as the center of symmetry.

[0504] When observing the crystal region from the specific direction, the lattice arrangement within the crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. Also, in the above-mentioned strain, there may be lattice arrangements such as pentagons and heptagons. In CAAC-OS, even in the vicinity of the strain, a clear grain boundary cannot be confirmed. That is, it can be seen that the formation of grain boundaries is suppressed due to the strain of the lattice arrangement. This is considered to be because CAAC-OS can tolerate strain due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction and the interatomic bond distance changes due to the substitution of metal atoms, etc.

[0505] A crystal structure in which a clear grain boundary is confirmed is called a so-called polycrystal. Grain boundaries can become recombination centers, and carriers are likely to be trapped, causing a decrease in the on-current of the transistor and a decrease in the field-effect mobility. Therefore, CAAC-OS in which a clear grain boundary is not confirmed is one of the crystalline oxides having a crystal structure suitable for the semiconductor layer of the transistor. To form CAAC-OS, a configuration having Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are preferable because they can suppress the generation of grain boundaries more than In oxide.

[0506] CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries confirmed. Therefore, it can be said that in CAAC-OS, a decrease in electron mobility due to grain boundaries is unlikely to occur. Also, since the crystallinity of the oxide semiconductor may decrease due to the incorporation of impurities or the generation of defects, etc., CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen deficiencies). Therefore, the physical properties of the oxide semiconductor having CAAC-OS are stable. Therefore, the oxide semiconductor having CAAC-OS is heat-resistant and highly reliable. Also, CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, when CAAC-OS is used for the OS transistor, it becomes possible to expand the degree of freedom in the manufacturing process.

[0507] [nc-OS] nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In other words, nc-OS has minute crystals. Since the size of the minute crystals is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the minute crystals are also referred to as nanocrystals. Further, nc-OS does not show regularity in the crystal orientation among different nanocrystals. Therefore, no orientation is observed in the entire film. Thus, depending on the analysis method, nc-OS may not be distinguishable from a-like OS or an amorphous oxide semiconductor. For example, when performing structural analysis on an nc-OS film using an XRD apparatus, in an Out-of-plane XRD measurement using θ / 2θ scan, no peak indicating crystallinity is detected. Further, when performing electron beam diffraction (also referred to as limited field of view electron beam diffraction) using an electron beam having a probe diameter larger than that of the nanocrystals (for example, 50 nm or more) on the nc-OS film, a diffraction pattern such as a halo pattern is observed. On the other hand, when performing electron beam diffraction (also referred to as nano-beam electron beam diffraction) using an electron beam having a probe diameter close to or smaller than that of the nanocrystals (for example, 1 nm or more and 30 nm or less) on the nc-OS film, an electron beam diffraction pattern in which a plurality of spots are observed within a ring-shaped region centered on a direct spot may be obtained.

[0508] [a-like OS] a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor. a-like OS has a loose or low-density region. That is, a-like OS has lower crystallinity compared with nc-OS and CAAC-OS. Further, a-like OS has a higher hydrogen concentration in the film compared with nc-OS and CAAC-OS.

[0509] <<Constitution of Oxide Semiconductor>> Next, the details of the above-described CAC-OS will be described. Note that CAC-OS relates to the material constitution.

[0510] [CAC-OS] CAC-OS is, for example, a component of a material in which the elements constituting the metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof. In the following, in the metal oxide, a state in which one or more metal elements are unevenly distributed and the regions having the metal elements are mixed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof is also referred to as a mosaic state or a patch state.

[0511] Furthermore, CAC-OS becomes a mosaic state by separating the material into a first region and a second region, and the first region is a structure distributed in the film (hereinafter also referred to as a cloud state). That is, CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.

[0512] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Or, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0513] Specifically, the first region is a region mainly composed of indium oxide, indium zinc oxide, etc. The second region is a region mainly composed of gallium oxide, gallium zinc oxide, etc. That is, the first region can be rephrased as a region mainly composed of In. The second region can be rephrased as a region mainly composed of Ga.

[0514] Note that there may be cases where no clear boundary can be observed between the above-mentioned first region and the second region.

[0515] For example, in CAC-OS in In-Ga-Zn oxide, it can be confirmed by EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) that the region mainly composed of In (the first region) and the region mainly composed of Ga (the second region) are unevenly distributed and have a mixed structure.

[0516] When using CAC-OS in a transistor, the conductivity caused by the first region and the insulating property caused by the second region act complementarily, thereby enabling the function of switching (the function of turning on / off) to be imparted to CAC-OS. That is, CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and has a function as a semiconductor in the whole material. By separating the conductive function and the insulating function, both functions can be maximally enhanced. Therefore, by using CAC-OS in a transistor, a high on-current (I on )、high field-effect mobility (μ), and good switching operation can be realized.

[0517] Oxide semiconductors have various structures, each having different characteristics. The oxide semiconductor according to one aspect of the present invention may have two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0518] <Transistor having an oxide semiconductor> Subsequently, the case of using the above-mentioned oxide semiconductor in a transistor will be described.

[0519] By using the above-mentioned oxide semiconductor in a transistor, a transistor with high field-effect mobility can be realized. Also, a highly reliable transistor can be realized.

[0520] For the transistor, it is preferable to use an oxide semiconductor with a low carrier concentration. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 or less, preferably 1×10 15 cm -3 or less, more preferably 1×10 13 cm -3 or less, even more preferably 1×10 11 cm -3 or less, still more preferably 1×10 10 cm -3 or less, and 1×10 -9 cm -3 or more. In the case of reducing the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced and the density of defect levels may be reduced. In this specification and the like, a low impurity concentration and a low density of defect levels are referred to as highly pure intrinsic or substantially highly pure intrinsic. In some cases, an oxide semiconductor with a low carrier concentration may be referred to as a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor.

[0521] Also, since an oxide semiconductor film that is highly pure intrinsic or substantially highly pure intrinsic has a low density of defect levels, the density of trap levels may also be low.

[0522] In addition, the charge trapped in the trap levels of the oxide semiconductor may take a long time to disappear and may behave like a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high trap level density may have unstable electrical characteristics.

[0523] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Further, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0524] <Impurities> Here, the effects of various impurities in the oxide semiconductor will be described.

[0525] When silicon and carbon, which are elements of Group 14, are contained in the oxide semiconductor, defect levels are formed in the oxide semiconductor. For this reason, the concentration of silicon and carbon in the oxide semiconductor and the concentration of silicon and carbon near the interface with the oxide semiconductor (the concentration obtained by secondary ion mass spectrometry (SIMS)) are set to 2×10 18 atoms / cm 3 or less, preferably 2×10 17 atoms / cm 3 or less.

[0526] In addition, when an alkali metal or an alkaline earth metal is contained in the oxide semiconductor, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have normally-on characteristics. For this reason, the concentration of the alkali metal or the alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less.

[0527] In an oxide semiconductor, when nitrogen is contained, electrons as carriers are generated, the carrier concentration increases, and it tends to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen tends to have normally-on characteristics. Or, in an oxide semiconductor, when nitrogen is contained, trap levels may be formed. As a result, the electrical characteristics of the transistor may become unstable. Therefore, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to be less than 5×10 19 atoms / cm 3 less than, preferably less than 5×10 18 atoms / cm 3 hereinafter, more preferably less than 1×10 18 atoms / cm 3 hereinafter, even more preferably less than 5×10 17 atoms / cm 3 or less.

[0528] In addition, hydrogen contained in the oxide semiconductor may react with oxygen bonded to metal atoms to form water, thereby forming oxygen vacancies. When hydrogen enters the oxygen vacancies, electrons as carriers may be generated. Also, a part of hydrogen may bond to oxygen bonded to metal atoms to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics. For this reason, it is preferable that the hydrogen in the oxide semiconductor is reduced as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration obtained by SIMS is set to be less than 1×10 20 atoms / cm 3 less than, preferably less than 1×10 19 atoms / cm 3 less than, more preferably less than 5×10 18 atoms / cm 3 less than, even more preferably less than 1×10 18 atoms / cm 3 or less.

[0529] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be imparted.

[0530] This embodiment can be appropriately combined with other embodiments shown in this specification and the like.

[0531] (Embodiment 7) In this embodiment, as an example of a semiconductor device, an IC chip, an electronic component, an electronic device, etc. will be described.

[0532] <Example of manufacturing method of electronic component> FIG. 25A is a flowchart showing an example of a manufacturing method of an electronic component. An electronic component is also called a semiconductor package or a package for an IC. This electronic component has a plurality of standards and names depending on the terminal extraction direction and the shape of the terminals. Therefore, in this embodiment, an example thereof will be described.

[0533] A semiconductor device composed of transistors is completed by attaching a plurality of components detachable from a printed circuit board through an assembly process (post-process). The post-process can be completed by going through each process shown in FIG. 25A. Specifically, after the element substrate obtained in the previous process is completed (step ST71), the back surface of the substrate is ground. At this stage, the substrate is thinned to reduce warping of the substrate in the previous process and to miniaturize the components. Next, a dicing process for separating the substrate into a plurality of chips is performed (step ST72).

[0534] FIG. 25B is a top view of a semiconductor wafer 7100 before the dicing process is performed. FIG. 25C is a partial enlarged view of FIG. 25B. A plurality of circuit regions 7102 are provided on the semiconductor wafer 7100. In the circuit region 7102, a semiconductor device according to the embodiment of the present invention (for example, a holding circuit, a memory device, an imaging device, an MCU, etc.) is provided.

[0535] The plurality of circuit regions 7102 are each surrounded by a separation region 7104. A separation line (also referred to as a "dicing line") 7106 is set at a position overlapping the separation region 7104. In the dicing process (step ST72), the semiconductor wafer 7100 is cut along the separation line 7106 to cut out the chip 7110 including the circuit region 7102 from the semiconductor wafer 7100. An enlarged view of the chip 7110 is shown in FIG. 25D.

[0536] A conductive layer or a semiconductor layer may be provided in the separation region 7104. By providing a conductive layer or a semiconductor layer in the separation region 7104, ESD that may occur during the dicing process can be mitigated, and a decrease in yield due to the dicing process can be prevented. Also, generally, the dicing process is performed while supplying pure water with a reduced resistivity by dissolving carbon dioxide gas or the like to the cutting part for the purpose of cooling the substrate, removing chips, preventing charging, and the like. By providing a conductive layer or a semiconductor layer in the separation region 7104, the amount of pure water used can be reduced. Therefore, the production cost of the semiconductor device can be reduced. Also, the productivity of the semiconductor device can be increased.

[0537] After performing step ST72, a die bonding process is performed in which the separated chips are individually picked up and mounted and joined on a lead frame (step ST73). The bonding method between the chip and the lead frame in the die bonding process may be selected according to a method suitable for the product. For example, the bonding may be performed with resin or tape. The die bonding process may mount and join the chips on an interposer. In a wire bonding process, the leads of the lead frame and the electrodes on the chip are electrically connected with a thin metal wire (wire) (step ST74). As the thin metal wire, a silver wire or a gold wire can be used. The wire bonding may be either ball bonding or wedge bonding.

[0538] The wire-bonded chip is encapsulated with an epoxy resin or the like, and a molding process is performed (step ST75). By performing the molding process, the inside of the electronic component is filled with resin, damage to the built-in circuit portion and the wires due to mechanical external force can be reduced, and deterioration of characteristics due to moisture and / or dust can also be reduced. The leads of the lead frame are plated. Then, the leads are cut and formed (step ST76). The plating process can prevent the leads from rusting and enable more reliable soldering when later mounted on a printed circuit board. A printing process (marking) is performed on the surface of the package (step ST77). Through the inspection process (step ST78), the electronic component is completed (step ST79). By incorporating the semiconductor device of the above-described embodiment, a small-sized electronic component with low power consumption can be provided.

[0539] A perspective schematic view of the completed electronic component is shown in FIG. 25E. In FIG. 25E, as an example of the electronic component, a perspective schematic view of a QFP (Quad Flat Package) is shown. As shown in FIG. 25E, the electronic component 7000 has leads 7001 and a chip 7110.

[0540] The electronic component 7000 is mounted on, for example, a printed circuit board 7002. A plurality of such electronic components 7000 are combined and electrically connected on the printed circuit board 7002, whereby they can be mounted on an electronic device. The completed circuit board 7004 is provided inside an electronic device or the like. By mounting the electronic component 7000, the power consumption of the electronic device can be reduced. Or, it becomes easier to miniaturize the electronic device.

[0541] The electronic component 7000 can be applied to electronic components (IC chips) in a wide range of fields of electronic devices, such as digital signal processing, software radio, avionics (electronic devices related to aviation such as communication devices, navigation systems, autopilot devices, flight management systems, etc.), ASIC prototyping, medical image processing, speech recognition, cryptography, bioinformatics (bioinformatics), emulators of mechanical devices, and radio telescopes in radio astronomy. Such electronic devices include cameras (video cameras, digital still cameras, etc.), display devices, personal computers (PCs), mobile phones, game machines including portable ones, portable information terminals (smartphones, tablet information terminals, etc.), electronic book terminals, wearable information terminals (watch type, head-mounted type, goggle type, glasses type, armband type, bracelet type, necklace type, etc.), navigation systems, audio playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, printer multifunction devices, automated teller machines (ATMs), vending machines, and home appliances.

[0542] This embodiment can be appropriately combined with other embodiments shown in this specification and the like.

[0543] (Embodiment 8) In this embodiment, an example of an electronic device having a semiconductor device according to an aspect of the present invention will be described. Examples of the electronic device are shown in FIGS. 26A to 26J. Note that FIGS. 26A to 26J show a state in which the electronic component 7000 having a semiconductor device according to an aspect of the present invention is included in each electronic device.

[0544] In various electronic devices, for example, AD conversion for converting various analog information such as acoustic information, imaging information, illuminance information, and temperature information into digital information may be performed. By using the semiconductor device according to one aspect of the present invention in an electronic device, AD conversion with suppressed power consumption increase can be performed. That is, by using the semiconductor device according to one aspect of the present invention in an electronic device, power consumption can be reduced. Further, by using the semiconductor device according to one aspect of the present invention, highly accurate AD conversion can be realized. Further, by using the semiconductor device according to one aspect of the present invention, high-speed AD conversion can be realized.

[0545] [Mobile phone] The information terminal 5500 shown in FIG. 26A is a mobile phone (smartphone), which is a type of information terminal. The information terminal 5500 includes a housing 5510, a display unit 5511, a speaker 5512, a camera 5513, a microphone 5514, etc. As an input interface, a touch panel is provided in the display unit 5511, and an operation switch 5515 is provided in the housing 5510.

[0546] The information terminal 5500 can hold temporary files (for example, caches when using a web browser, etc.) generated when an application is executed. In the information terminal 5500, AD conversion for converting various analog information such as acoustic information, imaging information, and illuminance information into digital information is performed.

[0547] [Wearable terminal] Further, FIG. 26B shows an information terminal 5900, which is an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display unit 5902, operation switches 5903, 5904, a band 5905, etc.

[0548] The information terminal 5900 includes various sensors such as a temperature sensor, a pressure sensor, and an illuminance sensor. In the information terminal 5900, AD conversion for converting analog information obtained by various sensors into digital information is performed.

[0549] [Information terminal] Further, FIG. 26C shows a desktop information terminal 5300. The desktop information terminal 5300 includes a main body 5301 of the information terminal, a display unit 5302, a keyboard 5303, a camera 5304, and the like.

[0550] Similar to the information terminal 5500 described above, the desktop information terminal 5300 performs AD conversion or the like to convert various analog information into digital information.

[0551] In the above description, a smartphone, a wearable terminal, and a desktop information terminal are illustrated in FIGS. 26A to 26C as examples of electronic devices, but information terminals other than smartphones, wearable terminals, and desktop information terminals can also be applied. Examples of information terminals other than smartphones, wearable terminals, and desktop information terminals include, for example, PDAs (Personal Digital Assistants), notebook information terminals, workstations, and the like.

[0552] [Household Appliance] Further, FIG. 26D shows an electric refrigerator-freezer 5800 as an example of a household appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like. For example, the electric refrigerator-freezer 5800 is an electric refrigerator-freezer compatible with IoT (Internet of Things).

[0553] The semiconductor device according to one aspect of the present invention can be applied to the electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 can transmit and receive information such as the food stored in the electric refrigerator-freezer 5800 and the expiration date of the food to and from an information terminal or the like through the Internet or the like. In the electric refrigerator-freezer 5800, AD conversion or the like is performed to convert various analog information such as the temperature inside the refrigerator into digital information.

[0554] In this example, an electric refrigerator has been described as an electric appliance. Other electric appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, IH cookers, water servers, air conditioners and other heating and cooling appliances, washing machines, dryers, audio-visual equipment, etc.

[0555] [Game console] In addition, FIG. 26E shows an example of a game console, a portable game console 5200. The portable game console 5200 includes a housing 5201, a display unit 5202, an operation switch 5203, an illuminance sensor 5204, a microphone 5205, etc.

[0556] Furthermore, FIG. 26F shows an example of a game console, a stationary game console 7500. The stationary game console 7500 includes a main body 7520 and a controller 7522. The controller 7522 can be connected to the main body 7520 wirelessly or by wire. Although not shown in FIG. 26F, the controller 7522 can include a display unit for displaying game images, a touch panel serving as an input interface other than operation switches, a stick, a rotary knob, a slide knob, a microphone, etc. Also, the controller 7522 is not limited to the shape shown in FIG. 26F, and the shape of the controller 7522 can be changed variously according to the genre of the game. For example, in a shooting game such as FPS (First Person Shooter), a trigger can be used as an operation switch, and a controller shaped like a gun can be used. Also, for example, in a music game, etc., a controller shaped like a musical instrument or a music device can be used. Furthermore, the stationary game console may be in a form that does not use a controller but instead includes a camera, a depth sensor, a microphone, etc., and is operated by the gestures and / or voices of the game player.

[0557] Also, the video of the game console described above can be output by a display device such as a television set, a personal computer display, a game display, a head-mounted display, etc.

[0558] Even in a portable game machine 5200 or a stationary game machine 7500, AD conversion or the like for converting various analog information into digital information is performed. By using the semiconductor device according to one aspect of the present invention in the portable game machine 5200 or the stationary game machine 7500, a portable game machine 5200 with low power consumption or a stationary game machine 7500 with low power consumption can be realized. In addition, due to the low power consumption, heat generation from the circuit can be reduced, so that the influence on the circuit itself, peripheral circuits, and modules due to heat generation can be minimized.

[0559] As game machines, which are a type of electronic device, a portable game machine 5200 and a stationary game machine 7500 are shown. However, as the electronic device according to one aspect of the present invention, for example, arcade game machines installed in entertainment facilities (such as game centers and amusement parks), pitching machines for batting practice installed in sports facilities, and the like are also included.

[0560] [Mobile object] The semiconductor device described in the above embodiment can be applied to an automobile, which is a mobile object, and the periphery of the driver's seat of the automobile.

[0561] An automobile 5700, which is an example of a mobile object, is illustrated in FIG. 26G.

[0562] Around the driver's seat of the automobile 5700, an instrument panel is provided that provides various information by displaying a speedometer, tachometer, odometer, fuel gauge, gear state, air conditioner settings, and the like. In addition, a display device for indicating those information may be provided around the driver's seat.

[0563] In particular, by using the display device and the video from an imaging device (not shown) provided outside the automobile 5700, the field of view blocked by pillars and the blind spots of the driver's seat can be compensated, and safety can be enhanced.

[0564] In the vehicle 5700, AD conversion for converting various analog information into digital information is performed. The digital information obtained by the AD conversion is used in systems for performing automatic driving, road guidance, danger prediction, and the like. The semiconductor device according to one aspect of the present invention can perform highly accurate AD conversion. Alternatively, the semiconductor device according to one aspect of the present invention can perform high-speed AD conversion. By using the semiconductor device according to one aspect of the present invention, the calculation processing accuracy of automatic driving, road guidance, danger prediction, and the like can be improved. By using the semiconductor device according to one aspect of the present invention, the calculation processing speed of automatic driving, road guidance, danger prediction, and the like can be increased.

[0565] Note that in the above description, an automobile has been described as an example of a moving body, but the moving body is not limited to an automobile. For example, examples of the moving body include trains, monorails, ships, flying bodies (helicopters, unmanned aerial vehicles (drones), airplanes, rockets), and the like.

[0566] [Camera] The semiconductor device according to one aspect of the present invention can be applied to a camera.

[0567] FIG. 26H shows a digital camera 6240 which is an example of an imaging device. The digital camera 6240 includes a housing 6241, a display unit 6242, an operation switch 6243, a shutter button 6244, and the like. A detachable lens 6246 is attached to the digital camera 6240. Here, the digital camera 6240 is configured such that the lens 6246 can be removed from the housing 6241 and replaced, but the lens 6246 and the housing 6241 may be integrated. Further, the digital camera 6240 may be configured such that a strobe device, a viewfinder, and the like can be separately attached.

[0568] By applying the semiconductor device according to one aspect of the present invention to the digital camera 6240, high-speed AD conversion can be realized. Further, since the power consumption is reduced, heat generation from the circuit can be reduced, so that the influence of heat generation on the circuit itself, peripheral circuits, and modules can be minimized.

[0569] [Video camera] The semiconductor device described in the above embodiment can be applied to a video camera.

[0570] FIG. 26I shows a video camera 6300 which is an example of an imaging device. The video camera 6300 includes a first housing 6301, a second housing 6302, a display unit 6303, an operation switch 6304, a lens 6305, a connection unit 6306, and the like. The operation switch 6304 and the lens 6305 are provided on the first housing 6301, and the display unit 6303 is provided on the second housing 6302. The first housing 6301 and the second housing 6302 are connected by a connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. The video on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.

[0571] By applying the semiconductor device according to one aspect of the present invention to the video camera 6300, high-speed AD conversion can be realized. Further, since the power consumption is reduced, heat generation from the circuit can be reduced, so that the influence of heat generation on the circuit itself, peripheral circuits, and modules can be minimized.

[0572] [ICD] The semiconductor device described in the above embodiment can be applied to an implantable cardioverter defibrillator (ICD).

[0573] FIG. 26J is a schematic cross-sectional view showing an example of an ICD. The ICD body 5400 includes at least a battery 5401, electronic components 7000, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.

[0574] The ICD body 5400 is implanted in the body by surgery, and the two wires are passed through the subclavian vein 5405 and the superior vena cava 5406 of the human body so that one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium.

[0575] The ICD body 5400 has a function as a pacemaker and performs pacing on the heart when the heart rate deviates from the specified range. Also, when the heart rate is not improved by pacing (such as rapid ventricular tachycardia or ventricular fibrillation), treatment by electric shock is performed.

[0576] The ICD body 5400 needs to constantly monitor the heart rate in order to perform pacing and electric shock appropriately. Therefore, the ICD body 5400 is provided with a sensor for detecting the heart rate. Also, the ICD body 5400 can store in the electronic components 7000 data on the heart rate obtained by the sensor and the like, the number of times and time of treatment by pacing, and the like.

[0577] Also, power can be received by the antenna 5404, and the power is charged to the battery 5401. Also, the ICD body 5400 can be made more secure by including a plurality of batteries. Specifically, even if some of the batteries of the ICD body 5400 become inoperable, the remaining batteries can function, so it also functions as an auxiliary power source.

[0578] Also, separately from the antenna 5404 that can receive power, it may have an antenna that can transmit physiological signals, for example, a system for monitoring heart activity that can confirm physiological signals such as pulse, respiratory rate, heart rate, and body temperature with an external monitoring device may be configured.

[0579] By applying the semiconductor device according to one aspect of the present invention to the ICD main body 5400, high-speed AD conversion can be realized. In addition, since the power consumption is reduced, the heat generation from the circuit can be reduced, so that the influence of the heat generation on the circuit itself, the peripheral circuit, and the module can be minimized. Therefore, the reliability of the ICD main body 5400 can be enhanced.

[0580] [Computer] The computer 5600 shown in FIG. 27A is an example of a large computer. A plurality of rack-mounted computers 5620 are stored in the rack 5610 in the computer 5600.

[0581] The computer 5620 can have, for example, the configuration of the perspective view shown in FIG. 27B. In FIG. 27B, the computer 5620 has a motherboard 5630, and the motherboard 5630 has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are respectively connected to the motherboard 5630.

[0582] The PC card 5621 shown in FIG. 27C is an example of a processing board provided with a CPU, a GPU, a semiconductor device, etc. The PC card 5621 has a board 5622. Further, the board 5622 has a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Although semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 are illustrated in FIG. 27C, the description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 described below may be referred to for those semiconductor devices.

[0583] The connection terminal 5629 has a shape that can be inserted into the slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. Examples of the standard of the connection terminal 5629 include PCIe and the like.

[0584] The connection terminals 5623, 5624, and 5625 can be used as interfaces for, for example, supplying power to and inputting signals to the PC card 5621. Further, for example, they can be used as interfaces for outputting signals calculated by the PC card 5621. Examples of the standards of the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), SCSI (Small Computer System Interface), and the like. Also, when outputting video signals from the connection terminals 5623, 5624, and 5625, examples of the standards include HDMI (registered trademark) and the like.

[0585] The semiconductor device 5626 has terminals (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminals into sockets (not shown) provided on the board 5622.

[0586] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected by, for example, performing reflow soldering on the terminals with respect to the wiring provided on the board 5622. Examples of...

Claims

1. A semiconductor device comprising: a comparison unit that compares a current value of a current flowing through one input terminal with a current value of a current flowing through the other input terminal; a first digital-to-analog conversion unit and a second digital-to-analog conversion unit; and a control unit, wherein the output of the first digital-to-analog conversion unit is electrically connected to one input terminal of the comparison unit; the output of the second digital-to-analog conversion unit is electrically connected to the other input terminal of the comparison unit; the comparison unit has a function of comparing a current value of a first signal flowing through the one input terminal with a current value of a second signal flowing through the other input terminal and generating an output signal; the control unit has a function of generating a sign bit according to the output signal, a function of generating a digital signal, and a function of outputting the sign bit and the digital signal; the first digital-to-analog conversion unit has a function of adding a current having a current value corresponding to the digital signal to the current of the first signal; the second digital-to-analog conversion unit has a function of adding a current having a current value corresponding to the digital signal to the current of the second signal; the comparison unit has a function of comparing a current value added to the current of the first signal with a current value added to the current of the second signal and generating the output signal.

2. In claim 1, the sign bit is determined according to a magnitude relationship between the current value of the first signal and the current value of the second signal.

3. In claim 1 or claim 2, the sign bit is a 1-bit digital value.

4. In any one of claims 1 to 3, the digital signal is determined according to a differential current between the first signal and the second signal.

5. In any one of claims 1 to 4, the digital signal is a digital value of 8 bits or more and 16 bits or less.

6. In any one of claims 1 to 5, the comparison unit is a current comparison type comparator.

7. In any one of claims 1 to 6, a semiconductor device that functions as a successive approximation type AD conversion device.

8. In any one of claims 1 to 7, a semiconductor device that functions as a ReLu function.

9. having a pixel portion and a peripheral circuit, the pixel portion having a plurality of pixels having a function of flowing a current to the peripheral circuit, The peripheral circuit has an AD conversion circuit into which the current is input as the first signal. The AD conversion circuit is a display device having the semiconductor device according to any one of claims 1 to 8.

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