Reading front-end circuit of continuous time increment tracking and scaling sensor and implementation method of reading front-end circuit

Abstract

The invention discloses a readout front-end circuit of a continuous time increment tracking zoom sensor and an implementation method of the readout front-end circuit, and belongs to the technical field of integrated circuit design. Preparing a floating transconductance amplifier, and simultaneously realizing current multiplexing and low output point voltage through floating power supply; by directly detecting the output of the fine quantizer, a tracking circuit in the reading front end of the tracking scaling type sensor is simplified, an additional input detection circuit is not introduced, and the digital code of the coarse quantizer is adjusted by utilizing the output of the fine quantizer, so that the dynamic range tracking of a rapid change signal is realized. By adopting the technical scheme of the invention, the sensor readout front-end circuit with high energy efficiency, low noise and high dynamic range is realized, and the sensor readout front-end circuit can adapt to novel edge application scenarios such as the Internet of Things, medical treatment and wearable equipment with a relatively high energy effect on rapid change signals.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit design, relates to the design technology of sensor readout circuits, and particularly relates to a continuous-time incremental tracking zoom sensor readout front-end circuit and an implementation method thereof, and designs and implements a sensor readout front-end circuit structure with high energy efficiency, low noise, and high dynamic range. Background Art

[0002] In edge applications such as the Internet of Things, healthcare, and wearable devices, continuous monitoring of sensors is usually required, and these devices are typically limited by the power of batteries or energy harvesters. Therefore, direct sensor readout front-end circuits are favored because they can significantly simplify the signal conditioning circuit and reduce the device cost. With the development of sensor technology and the expansion of its application scope, emerging edge applications require sensor readout circuits to have low input-referred noise (≤10 μVrms) and medium conversion speed (≥10 kHz). At the same time, in order to read signals with small variation amplitudes while there are artifacts and interferences in the 100 mV range, the readout front-end circuit needs to provide a large dynamic range (DR, Dynamic Range) (≥80 dB).

[0003] Delta-Sigma Modulators (ΔΣMs) can achieve the required dynamic range through oversampling and quantization noise shaping, but achieving a large dynamic range requires a high-order ΔΣ loop or a large oversampling ratio (OSR, Over-Sampling Ratio), which will generate large power consumption. The Zoom architecture combines an energy-efficient successive approximation register (SAR) analog-to-digital converter and a high-resolution ΔΣ modulator, and has great application potential in edge signal readout. In the Zoom architecture, most of the input range is coarsely quantized by the successive approximation register, and the input of the ΔΣ loop is the smaller coarsely quantized residual signal. Therefore, the Zoom architecture can provide a large input range, high energy efficiency, and low input equivalent noise at the same time.

[0004] However, during the conversion of the scaling architecture, signals with a relatively fast change rate may exceed the fine quantization dynamic range of the ΔΣ loop. The Dynamic Zoom architecture performs successive approximation register coarse quantization in each cycle to ensure that the input remains within the fine quantization dynamic range. However, the frequent digital-to-analog converter (DAC) switching during the successive approximation register coarse quantization process limits its energy efficiency. To address this issue, recent sensor readout circuits have adopted Tracking technology. By using a dedicated loop filter monitor or a post-sampling input slope estimator to estimate the change in the input value and updating the fine quantization dynamic range accordingly, the signal can be kept within the fine quantization dynamic range without performing coarse quantization for each fine quantization cycle. However, the former requires adding additional always-on analog comparators to estimate the input value range with multiple comparison thresholds. The latter relies on complex logic and a large inter-stage redundancy to expand the acceptable slope rate. Therefore, both methods incur significant additional energy and area costs.

[0005] In summary, the existing sensor readout front-end circuits designed have the deficiencies of low energy efficiency, high noise, and small dynamic range, and it is difficult to meet the requirements of new edge applications such as the Internet of Things, medical, and wearable devices for sensor readout front-end circuits with high energy efficiency, low noise, and high dynamic range. Summary of the Invention

[0006] Aiming at the deficiencies of the above-mentioned existing technologies, the present invention provides a continuous-time delta-tracking scaling sensor readout front-end circuit and its implementation method, designs and implements a sensor readout front-end circuit with high energy efficiency, low noise, and high dynamic range, and can cope with rapidly changing signals with high energy efficiency, and is adaptable to new edge application scenarios such as the Internet of Things, medical, and wearable devices.

[0007] The continuous-time delta-tracking scaling sensor readout front-end circuit proposed by the present invention is a novel continuous-time delta-type scaling sensor readout front-end circuit. It adopts a fast-tracking logic circuit based on the output detection of a fine quantizer to perform low-overhead and high-response-speed fine quantization dynamic range tracking on rapidly changing input signals. At the same time, the designed floating transconductance amplifier and current-controlled oscillator (CCO) are used as integrators. The floating transconductance amplifier is a quasi-static continuous-time open-loop transconductance amplifier, which can cooperate with the low-voltage-operating current-controlled oscillator integrator to work, improving the energy efficiency of the continuous-time delta-tracking scaling sensor readout front-end circuit. Through the above technologies, the present invention can meet the requirements of new edge applications such as the Internet of Things, medical, and wearable devices for the power consumption, noise, and dynamic range of sensor readout front-end circuits with high energy efficiency, low noise, and high dynamic range.

[0008] The technical solution of the present invention is as follows:

[0009] A method for implementing a continuous-time incremental tracking and scaling sensor readout front-end circuit, which designs a continuous-time incremental tracking and scaling sensor readout front-end circuit without introducing an additional input detection circuit. By using the output of a fine quantizer to adjust the digital code of a coarse quantizer, continuous tracking of the input signal is achieved. A floating transconductance amplifier and a low-voltage current-controlled ring oscillator are used as integrators to improve the overall energy efficiency of the circuit. The implementation method includes the following steps:

[0010] 1) Prepare a floating transconductance amplifier. Use complementary MOS (Metal Oxide Semiconductor Field Effect Transistor) transistors with their drain terminals connected as the input transistors of the floating transconductance amplifier. Add the floating current source proposed by the present invention, which consists of a current source transistor and a current source bias capacitor, to the power supply side of the input transistors to stabilize the operating current and transconductance gain of the amplifier. Add a supply capacitor that is connected across the entire input transistors and the floating current source in the operating state, enabling the amplifier to operate in a floating voltage domain. Add a charging current mirror for charging the current source bias capacitor in the charging state. Add a "virtual" transistor with its source and drain short-circuited between the gate and drain of the input transistors to eliminate the influence of kickback noise. Add a control switch composed of MOS transistors for switching the charging and operating states of the supply capacitor and the current source bias capacitor, and simultaneously periodically turning off the output of the amplifier through the charging of the supply capacitor to provide a dead zone of the amplifier that can be used to eliminate chopping artifacts. The prepared floating transconductance amplifier includes input transistors, a floating current source, a charging current mirror, a "virtual" transistor, a supply capacitor, and a control switch.

[0011] 2) Prepare a multi-bit SAR sensor readout front-end circuit, which includes a coarse quantization digital-to-analog converter (DAC), a comparator, and a coarse quantization digital logic. The output digital code of the coarse quantization digital logic is connected to the digital input of the coarse quantization DAC, the top plate of the coarse quantization DAC is connected to the input of the comparator, and the output of the comparator is connected to the input of the coarse quantization digital logic. Among them, the coarse quantization digital logic includes an asynchronous SAR logic and an asynchronous counter logic that share a data register for performing fast tracking of the fine quantization dynamic range.

[0012] 3) Fabricate a multi-bit incremental ΔΣ sensor readout front-end circuit, which includes four parts: a fine quantization DAC, a transconductance amplifier, an integrator, a quantizer, and a fine quantization digital logic. The output digital code of the fine quantization digital logic is connected to the input of the fine quantization DAC. The top plate of the fine quantization DAC is connected to the input of the transconductance amplifier. The input of the transconductance amplifier is connected to the input of the integrator. The input of the integrator is connected to the input of the quantizer. The output result of the quantizer is connected to the fine quantization digital logic. Among them, the transconductance amplifier uses the floating transconductance amplifier proposed in the present invention, and the integrator uses a low-voltage current-controlled ring oscillator as a time-domain integrator. The fine quantization digital logic includes a fine quantization output detection logic circuit and a tracking control logic circuit, which generates a tracking control signal according to the fine quantization output digital code for controlling the fast tracking of the fine quantization dynamic range.

[0013] The above steps 2) and 3) perform fast tracking of the fine quantization dynamic range, which specifically includes a control process and an execution process. Among them, the control process is implemented in the fine quantization digital logic part in step 3), and the execution process is implemented in the coarse quantization digital logic in step 2). In the coarse quantization digital logic, by fusing an asynchronous SAR logic and an asynchronous bidirectional counter, the SAR conversion and the increase and decrease of the coarse quantization digital code can be controlled, so that the coarse quantization digital code tracks the input signal. In the fine quantization digital logic, through the fine quantization output detection and judgment circuit, a control signal required for the coarse quantization level to track the input signal is provided.

[0014] 4) Connect the charge-sharing DAC top plate of the multi-bit SAR sensor readout front-end circuit and the multi-bit incremental ΔΣ sensor readout front-end circuit to form a shared DAC component. The shared DAC component is composed of two capacitor array top plates with different sizes connected together. Among them, the DAC in the multi-bit SAR sensor readout front-end circuit is a coarse quantization DAC, and the DAC in the multi-bit incremental ΔΣ sensor readout front-end circuit is a fine quantization DAC.

[0015] 5) Take the multi-bit SAR sensor readout front-end circuit as the first stage and the multi-bit incremental ΔΣ sensor readout front-end circuit as the second stage. The two-stage sensor readout front-end circuits are connected through the top plate of the shared DAC component. Connect the tracking control logic of the fine quantization digital logic in the second stage (multi-bit incremental ΔΣ sensor readout front-end circuit) to the tracking execution logic of the coarse quantization digital logic in the first stage (multi-bit SAR sensor readout front-end circuit). Add chopper switches before the input, before the input of the shared DAC component, after the output of the floating transconductance amplifier, and after the output of the comparator, and then the improved continuous-time incremental tracking and scaling sensor readout front-end circuit can be obtained.

[0016] The specific method for fabricating the floating transconductance amplifier is as follows:

[0017] A transconductance amplifier circuit composed of an input tube, a floating current source, a charging current mirror, a "dummy" transistor (Dummy transistor), a power supply capacitor, and a control switch.

[0018] The input tube includes an NMOS (N-channel Metal Oxide Semiconductor Field Effect Transistor) transistor and a PMOS (P-channel Metal Oxide Semiconductor Field Effect Transistor) transistor. The gates of the two transistors are connected together to form the input of the floating transconductance amplifier. The drains of the two transistors are connected together to form the output of the floating transconductance amplifier. Current multiplexing is achieved by connecting two groups of transistors with transconductance gain in series in the current path of the amplifier to improve the noise efficiency of the transconductance amplifier and reduce the operating current required to achieve the target noise range. The input tube uses a thick-gate transistor to reduce gate leakage and allows the gate to establish a bias voltage through a pseudo-resistance biasing circuit composed of transistors in the cut-off region.

[0019] The present invention proposes a floating current source design, which consists of a current source tube and a current source bias capacitor. The current source tube is a PMOS transistor operating in the saturation region, and the current flowing through the current source tube is limited by a high output impedance. The current source bias capacitor is connected between the gate and the source of the current source tube and provides a constant gate-source bias voltage for the current source tube in the working state. The floating current source is connected in series with the source terminal of the PMOS transistor in the input tube, and the current flowing through the input tube is kept constant by the current limiting effect of the current source tube in the working state, thus stabilizing the power consumption and transconductance gain of the floating transconductance amplifier. The charging current mirror uses a PMOS current mirror design to charge the current source bias capacitor in the charging state.

[0020] The source and drain of the "dummy" transistor are short-circuited and do not consume any power. By cross-connecting the gate and the drain of the input tube with the opposite polarity to the input tube, the differential-mode kickback noise generated during the operation of the input tube is converted into common-mode kickback noise, eliminating the influence of kickback noise on the operation of the transconductance amplifier.

[0021] The power supply capacitor is connected to the floating current source and the input tube in the working state to provide power for both. The control switch connects or disconnects the circuits between the power supply capacitor, the current source bias capacitor, the input tube, and the current source tube through NMOS and PMOS transistors operating in the linear region and the cut-off region, realizing the switching between different working phases of the floating transconductance amplifier.

[0022] When the floating transconductance amplifier operates, the input transistor and the floating current source are powered by a supply capacitor, which is completely disconnected from the power supply and ground. Due to the influence of current continuity, the current flowing out of the supply capacitor is the same as the current flowing into the supply capacitor. Therefore, the input transistor will not generate a common-mode current flowing to the output, nor will it change the common-mode bias voltage at the output point. Instead, through the change in the voltage of the supply capacitor with respect to ground, the floating voltage domain provided by the supply capacitor is moved to both ends of the original common-mode voltage at the output point. During the operation of the floating transconductance amplifier, as the supply capacitor supplies energy outward, the voltage difference across the supply capacitor gradually decreases. At this time, the current-source transistor in the floating current source provides a stable gate-source voltage difference through the current-source bias capacitor connected between the source terminal and the gate terminal, and is always biased in the saturation region to provide a high output impedance. The change in the voltage difference across the supply capacitor affects the floating transconductance amplifier mainly by reducing the source-drain voltage difference of the current-source transistor, while having little effect on the voltage difference between the source terminals of the input transistor and the operating current flowing through the input transistor. The transconductance gain during operation can be approximated as a constant value.

[0023] To implement the fine-grained dynamic range fast tracking method in the above steps 2) and 3), the present invention designs a fine-grained dynamic range fast tracking logic circuit based on the detection of the output of the fine-grained quantizer, specifically:

[0024] During the fine-grained quantization process, continuously detect the output digital code of the fine-grained quantizer, estimate the input signal of the fine-grained quantizer based on this, and accordingly move the dynamic range of the fine-grained quantizer to achieve the follow-up of the dynamic range of the fine-grained quantizer with the change of the input signal. The fine-grained dynamic range fast tracking logic circuit consists of a fine-grained output detection logic, a tracking control logic, and a tracking execution logic. The detailed implementation of the fine-grained dynamic range fast tracking logic circuit is as follows:

[0025] A. Fine-grained output detection logic

[0026] The present invention proposes that in the multi-bit ΔΣ sensor readout front-end circuit, the readout digital code is approximately close to the input signal, and there are only small errors caused by non-ideal factors such as shaped quantization noise and thermal noise. The output digital code of the fine-grained quantizer can be directly used as an estimated value of the input of the fine-grained quantizer, and compared with a preset threshold and the maximum output code word of the fine-grained quantizer in the digital domain, so as to realize the detection of the relationship between the current input signal and the fine-grained dynamic range.

[0027] B. Fast tracking control logic

[0028] The logical overhead of fine quantization output detection is relatively low. Therefore, the present invention proposes that fine quantization output detection can be performed in each fine quantization cycle, and the tracking process can be controlled according to the detection result. By reducing the tracking interval, fast tracking of the input signal can be achieved. When the digital code output by the fine quantizer exceeds the tracking threshold, the digital code of the coarse quantizer is increased or decreased in the direction where the digital code of the fine quantizer is located, and the output voltage of the coarse quantization DAC is changed, so as to move the overall dynamic range of the fine quantizer in the direction of the current input signal and keep the dynamic range of the fine quantizer near the input signal. When the digital code output by the fine quantizer reaches the maximum output code word of the fine quantizer, it can be judged that the input has exceeded the dynamic range of the fine quantizer. At this time, the fine quantizer is saturated and cannot effectively represent the range where the input signal is located. In this state, it will be controlled to trigger a coarse quantization SAR conversion process at the next circuit reset. By searching within the complete dynamic range of the coarse quantization, the dynamic range of the fine quantizer is reset near the input signal.

[0029] C. Fast Tracking Execution Logic

[0030] To meet the requirements of the two functions of increasing / decreasing the digital code and SAR conversion proposed for the coarse quantizer in the above process, the fast tracking execution logic proposed by the present invention uses a coarse quantization digital logic design that integrates asynchronous SAR logic and asynchronous bidirectional counter. Based on the asynchronous SAR logic, the data register therein is reused, and clock selection logic and bidirectional carry logic are added to the data register on the basis of the traditional asynchronous SAR logic to form an asynchronous bidirectional SAR counter structure. When performing SAR conversion, the data register in the coarse quantization digital logic selects the sampling clocks of each bit in the asynchronous SAR logic to control the asynchronous SAR conversion process; when performing fine quantization dynamic range tracking, the data register selects the trigger pulse generated by the bidirectional carry logic of the asynchronous counter for the clock, and selects the counting direction according to the input control signal, and at the same time generates a low-order input pulse for asynchronous counting to increase or decrease the coarse quantization digital code, so as to achieve the goal of tracking the input signal in the fine quantization dynamic range.

[0031] The present invention uses the above method to prepare a continuous-time incremental tracking zoom sensor readout front-end circuit, including: a multi-bit SAR sensor readout front-end circuit, a multi-bit incremental ΔΣ sensor readout front-end circuit, and a chopper switch. Among them, the multi-bit SAR sensor readout front-end circuit serves as the first stage of the overall circuit, used for the first-step coarse quantization and shifting the dynamic range of the fine quantizer; the multi-bit incremental ΔΣ sensor readout front-end circuit serves as the second stage of the overall circuit, used for the second-step fine quantization to determine the exact position of the input signal within the dynamic range and continuously detect the change of the input signal during the fine quantization process; the chopper switch is used to periodically invert the signal polarity. The multi-bit SAR sensor readout front-end circuit and the multi-bit incremental ΔΣ sensor readout front-end circuit share a charge-sharing DAC component. The top plate of this component is connected to the input signal through a coupling capacitor. This component consists of two capacitor array top plates of different sizes connected together, and the corresponding capacitor arrays are switched respectively when the two-stage sensor readout front-end circuits work. The multi-bit SAR sensor readout front-end circuit controls the coarse quantization DAC, and the multi-bit incremental ΔΣ sensor readout front-end circuit controls the fine quantization DAC.

[0032] A. The multi-bit SAR sensor readout front-end circuit includes three parts: a coarse quantization DAC, a comparator, and a coarse quantization digital logic. Among them, the coarse quantization digital logic includes the fast tracking execution logic in the fast tracking logic circuit, which is implemented by the asynchronous SAR logic and the asynchronous counter logic sharing a data register.

[0033] B. The multi-bit incremental ΔΣ sensor readout front-end circuit includes four parts: a fine quantization DAC, a transconductance amplifier, an integrator, a quantizer, and a fine quantization digital logic. Among them, the transconductance amplifier uses a floating transconductance amplifier, and the integrator uses a low-voltage current-controlled ring oscillator. The fine quantization digital logic includes the fine quantization output detection logic and the fast tracking control logic in the fast tracking logic circuit, which are implemented by a compressor, a comparator, and a logic judgment circuit.

[0034] C. The chopper switch includes four parts: an input chopper switch, a DAC chopper switch, a transconductance amplifier output chopper switch, and a comparator output chopper switch.

[0035] Furthermore, the multi-bit SAR sensor readout front-end circuit is 7-bit, with 2 bits redundant; the multi-bit incremental ΔΣ sensor readout front-end circuit is 5-bit.

[0036] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0037] The present invention provides a method for implementing a transconductance amplifier with high energy efficiency and high output common-mode range, proposes a floating transconductance amplifier structure, and combines it with a low-voltage current-controlled ring oscillator as an integrator for the fine quantization stage. By supplying power with a floating voltage to avoid common-mode output current and using a floating current source to stabilize the operating current of the amplification stage, this structure has the characteristics of high noise efficiency, simple biasing, no need for common-mode feedback, and being unaffected by the common-mode voltage at the output point. It can effectively cooperate with the low-voltage current-controlled ring oscillator to further improve the energy efficiency of the overall circuit.

[0038] The present invention provides a continuous-time incremental tracking scaling sensor readout front-end circuit and its implementation method, designs a fast tracking logic circuit based on the output detection of a fine quantizer to perform low-overhead and high-response-speed fine quantization dynamic range tracking on fast-changing input signals, and at the same time uses a floating transconductance amplifier and a current-controlled ring oscillator as an integrator. The fast tracking logic circuit based on the output detection of the fine quantizer is a fine quantization dynamic range fast tracking logic circuit applicable to a scaling data conversion circuit based on the output detection of the fine quantizer. It does not introduce additional analog circuit units, makes full use of the low quantization noise characteristics of the multi-bit fine quantizer, directly uses the output codeword of the fine quantizer to estimate the input signal, and avoids the problems of high power consumption and slow tracking response speed existing in the additional analog detection circuit or the prediction circuit for tracking compensation of high input slope after sampling in the traditional tracking technology. The designed continuous-time incremental tracking scaling sensor readout front-end circuit simultaneously meets the application requirements of high energy efficiency, low noise, and high dynamic range, and is applicable to new edge application scenarios such as the Internet of Things, medical, and wearable devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 It is a schematic diagram of the structure and a top-level working phase diagram of the continuous-time incremental tracking scaling sensor readout front-end circuit in the present invention;

[0040] Among them, V in is the voltage signal input of the sensor to be measured, D SAR is the output digital code of the SAR sensor readout front-end circuit, that is, the coarse quantization digital code; D CCO is the output digital code of the incremental ΔΣ sensor readout front-end circuit, that is, the fine quantization digital code. In the top-level working phase, the clock represents the sampling and control signal of the fine quantization stage, and the reset represents the integrator and quantizer reset signal required for the fine quantization stage to achieve incremental conversion, and is also the control signal to enable the coarse quantization stage to perform SAR conversion when SAR conversion is required. It is periodically switched between the reset and the coarse quantization phase and the fine quantization phase under the control of the reset signal.

[0041] Figure 2 It is the circuit diagram and working mode diagram of the fine quantization dynamic range fast tracking logic circuit based on the output detection of the fine quantizer proposed by the present invention;

[0042] The circuit diagram from left to right is the fine quantization output detection circuit, the fast tracking control circuit, and the fast tracking execution circuit. Among them, UP and DN are the original fine quantization digital codes of the three-valued thermometer code. The fine quantization digital codes are converted into binary complement codes through two 14-4 compressors and a complement subtractor. Subsequently, a digital comparator is used to judge the range of the numerical value of the fine quantization digital code in complement code. In the design example, the ratio of the coarse quantization level to the fine quantization digital code is set to 8. Therefore, the range judgment of the fine quantization digital code in the figure is also set to 8. Different control signals for the coarse quantization logic are generated according to the fine quantization digital code in different ranges. The coarse quantization logic uses the SAR logic that integrates the function of an asynchronous bidirectional counter, and can perform SAR conversion according to the control signal generated by the fine quantization level, or perform an increment or decrement operation on the coarse quantization digital code.

[0043] Figure 3 The following is a schematic diagram of the circuit structure of the floating transconductance amplifier proposed by the present invention. This structure is applied to the transconductance amplifier of the fine quantization level in the continuous-time delta tracking scaling sensor readout front-end circuit proposed by the present invention. Among them, V DDA represents the analog power supply, C res represents the power supply capacitor, C b represents the bias capacitor of the current tube, M tail represents the current source tube, V SP and V SN represent the source ends of the input tubes, V IP and V IN represent the input signals, V CCO represents the output bias voltage when the amplifier bias is established, CCO P and CCO N represent the current-controlled ring oscillator in the subsequent circuit.

[0044] Figure 4 The following is a schematic diagram of the operation of the floating transconductance amplifier proposed by the present invention, including the operation phase of the floating transconductance amplifier and the voltage changes at the key nodes. Among them, the sampling clock and the establishment clock are actual control signals, and the operation phase is the periodic operation state generated by the sampling clock and the establishment clock. The node markings in the key nodes are shown in Figure 3 description, V DS，N represents the voltage difference between the source and drain of the NMOS transistor in the input tube, and ro represents the equivalent output impedance of the overall floating transconductance amplifier to the subsequent stage. Specific Embodiments

[0045] The present invention will be further described below in conjunction with the accompanying drawings through specific embodiments, but the scope of the present invention is not limited in any way.

[0046] The present invention provides a method for implementing a transconductance amplifier with high energy efficiency and high output common-mode range, and based on the transconductance amplifier, a continuous-time incremental tracking and scaling sensor readout front-end circuit is implemented. Through the floating current source technology, floating power supply can be used for the transconductance amplifier operating in continuous time. After being fabricated as a floating transconductance amplifier, current multiplexing and low output point voltage are achieved through floating power supply, thereby improving the overall energy efficiency; by directly detecting the output of the fine quantizer, the tracking circuit in the tracking and scaling sensor readout front-end is simplified, and the dynamic range tracking of fast-changing signals is achieved with a small power consumption overhead.

[0047] The overall architecture of the present invention is a continuous-time incremental tracking and scaling sensor readout front-end circuit. The continuous-time incremental tracking and scaling sensor readout front-end circuit proposed by the present invention is composed of a multi-bit SAR sensor readout front-end circuit, a multi-bit incremental ΔΣ sensor readout front-end circuit, and a chopper switch. Among them, the multi-bit SAR sensor readout front-end circuit is the first-stage coarse quantization circuit, the multi-bit incremental ΔΣ sensor readout front-end circuit is the second-stage fine quantization circuit, and the chopper switch periodically flips the signal polarity when the capacitor is working.

[0048] The present invention combines the high energy efficiency of the SAR sensor readout front-end circuit and the low noise of the incremental ΔΣ sensor readout front-end circuit, and expands the overall dynamic range of the circuit in the form of two-stage combination. On the basis of the traditional structure, the present invention improves the input signal tracking technology and the transconductance amplifier that determines the noise efficiency in the fine quantization stage to simultaneously achieve high energy efficiency, low noise, and high dynamic range. The multi-bit SAR sensor readout front-end circuit and the multi-bit incremental ΔΣ sensor readout front-end circuit in the present invention share a charge-sharing DAC component. The top plate of this component is connected to the input signal through a coupling capacitor. This component is composed of two capacitor arrays with different sizes connected at the top plate, and the corresponding capacitor arrays are switched respectively when the two-stage sensor readout front-end circuits are working. The coarse quantization DAC is controlled by the multi-bit SAR sensor readout front-end circuit, and the fine quantization DAC is controlled by the multi-bit incremental ΔΣ sensor readout front-end circuit.

[0049] The following details the components in the continuous-time incremental tracking and scaling sensor readout front-end circuit proposed by the present invention (including: the multi-bit SAR sensor readout front-end circuit, the multi-bit incremental ΔΣ sensor readout front-end circuit, and the chopper switch):

[0050] A. Multi-bit SAR sensor readout front-end circuit

[0051] In specific implementation, the present invention designs and adopts a traditional SAR sensor readout circuit to coarsely quantize the input signal. This part of the circuit includes three parts: a coarse quantization DAC, a comparator, and a coarse quantization digital logic, as Figure 1As shown on the lower side. Based on the traditional structure, the present invention improves the coarse quantization digital logic, including asynchronous SAR logic and asynchronous counter logic sharing a data register, which is used to perform fine quantization dynamic range fast tracking.

[0052] During a complete SAR conversion, the coarse quantization digital logic selects the respective sampling clocks generated by the asynchronous SAR logic as the trigger clocks for the data register. First, it controls the coarse quantization DAC to reset, and switches the coarse quantization digital codes bit by bit. The asynchronous self-generation of the conversion clock is realized through the valid signal output by the comparator and the delay circuit, and the comparator is used to judge the magnitude relationship between the current input signal and the current DAC output voltage. During the conversion process, the DAC output voltage is continuously made close to the input signal, and at the same time, the remaining voltage on the DAC top plate gradually decreases and finally falls within the input dynamic range of the subsequent circuit.

[0053] During the tracking of the coarse quantization digital code, the coarse quantization digital logic selects the bidirectional carry logic output of the asynchronous counter as the trigger clock for the data register, and uses the asynchronous counter structure where the output of the low-order register is connected to the clock of the high-order register. Among them, the clock of the lowest-order register is connected to the counting trigger signal, and the polarity of the connection between the low-order and high-order is changed through the direction signal, thereby selecting to count up or down.

[0054] B. Readout Front-End Circuit of Multi-Bit Incremental ΔΣ Sensor

[0055] In specific implementation, the present invention designs and adopts a readout front-end circuit of a multi-bit incremental ΔΣ sensor to perform fine quantization on the remaining voltage after coarse quantization. The readout front-end circuit part of the multi-bit incremental ΔΣ sensor includes a fine quantization DAC, a transconductance amplifier, an integrator, a quantizer, and a fine quantization digital logic, as Figure 1 shown on the upper side.

[0056] The fine quantization DAC realizes finer and lower-noise quantization through using a smaller unit capacitance than the coarse quantization DAC and ΔΣ modulation. By designing the total unit capacitance of the fine quantization DAC to be greater than the single unit capacitance of the coarse quantization DAC, the dynamic range of the fine quantization will be greater than that of the coarse quantization DAC, providing a redundant range of about 2 bits, and the fine quantization process can still be normally completed when there is a certain error between the fine quantization dynamic range and the input signal.

[0057] The transconductance amplifier adopts the floating transconductance amplifier proposed by the present invention to achieve low-noise amplification of the input signal with high noise efficiency and at low power consumption. The specific design of the floating transconductance amplifier is as follows:

[0058] The floating transconductance amplifier includes an input tube, a floating current source, a charging current mirror, a "virtual" transistor, a power supply capacitor, and a control switch.

[0059] The input tube is Figure 3Each transistor in the lower right is composed of an NMOS transistor and a PMOS transistor. The gates of the two transistors are connected together to form the input of the floating transconductance amplifier; the drains of the two transistors are connected together to form the output of the floating transconductance amplifier. The input transistor will distribute a part of the working current flowing through the input transistor to the positive output path or the negative output path according to the magnitude of the input voltage difference, generating a differential-mode output current between the positive and negative output terminals without generating a common-mode current, so as to achieve the effect of transconductance amplification. Current reuse is achieved by connecting two groups of transistors with transconductance gain in series in the current path of the amplifier to improve the noise efficiency of the transconductance amplifier and reduce the working current required to achieve the target noise range; the input transistor uses a thick-gate transistor to reduce gate leakage and allows the gate to establish a bias voltage through a pseudo-resistance biasing circuit composed of transistors in the cut-off region.

[0060] The floating current source consists of a current source transistor and a current source bias capacitor, as Figure 3 shown in the upper right. Among them, the current source transistor is a PMOS transistor operating in the saturation region, which limits the current flowing through the current source transistor through a high output impedance; the current source bias capacitor C b is connected between the gate and the source of the current source transistor, providing a constant gate-source bias voltage for the current source transistor in the working state; the floating current source is connected in series with the source of the PMOS transistor in the input transistor, and keeps the current flowing through the input transistor constant through the current limiting effect of the current source transistor in the working state, stabilizing the power consumption and transconductance gain of the floating transconductance amplifier. The charging current mirror is Figure 3 the PMOS transistor shown in the upper left. In the charging state, the bias voltage required for the floating current source is generated through the diode-connected PMOS current mirror structure in the charging current mirror and charged into the current source bias capacitor.

[0061] The source and drain of the "virtual" transistor are short-circuited and do not consume any power. By cross-connecting the gate and drain of the input transistor with the opposite polarity to the input transistor, the differential-mode kickback noise generated during the operation of the input transistor is converted into common-mode kickback noise, eliminating the influence of kickback noise on the operation of the transconductance amplifier;

[0062] The power supply capacitor is Figure 3 C in the middle res , which is connected to the floating current source and the input transistor in the working state and provides power for both of them.

[0063] The control switch is Figure 3 each switch in. Among them, the switches in the upper half diagram are implemented by PMOS transistors, and the switches in the lower half diagram are implemented by NMOS transistors, both of which operate in the linear region or the cut-off region, and can connect or disconnect the lines between the power supply capacitor, the input transistor, the current source bias capacitor and the current source transistor, realizing the switching between different working phases of the floating transconductance amplifier.

[0064] When the floating transconductance amplifier operates, the input transistor and the floating current source are powered by a supply capacitor, which is completely disconnected from the power supply and ground. Due to the influence of current continuity, the current flowing out of the supply capacitor is equal in magnitude to the current flowing into the supply capacitor. Therefore, the input transistor will not generate a common-mode current flowing to the output, nor will it change the common-mode bias voltage at the output point. Instead, through the change in the voltage of the supply capacitor with respect to ground, the floating voltage domain provided by the supply capacitor is shifted to both ends of the original common-mode voltage at the output point. During the operation of the floating transconductance amplifier, as the supply capacitor supplies energy outward, the voltage difference across the supply capacitor gradually decreases. At this time, the current-source transistor in the floating current source provides a stable gate-source voltage difference through the current-source bias capacitor connected between the source and the gate, and is always biased in the saturation region to provide a high output impedance. The change in the voltage difference across the supply capacitor affects the floating transconductance amplifier mainly by reducing the source-drain voltage difference of the current-source transistor, and has little effect on the voltage difference between the source terminals of the input transistor and the operating current flowing through the input transistor. The transconductance gain during operation can be approximated as a constant value.

[0065] Compared with the prior art, the operating voltage domain of the floating transconductance amplifier can freely float following the common-mode voltage at the output point, and will not limit the source-drain voltage difference of the input transistor due to the excessive or too low common-mode voltage at the output point. Consequently, it will not affect the output impedance of the floating transconductance amplifier and can be applied to the subsequent circuit with a high input impedance and a fixed input common-mode voltage. Taking a low-voltage current-controlled ring oscillator as an example, the low-voltage current-controlled ring oscillator is biased at an extremely small operating current to achieve a low oscillation frequency, thereby reducing the energy consumption generated by the operation of the ring oscillator itself and the subsequent quantization circuit, and can significantly improve the energy efficiency ratio of the fine quantization process. However, at this time, the input point of the current-controlled ring oscillator will also be biased at an extremely low voltage and exhibit a high input impedance due to the extremely small operating current. If a transconductance amplifier containing an NMOS transistor input transistor is used to drive this current-controlled ring oscillator, the common-mode bias voltage at the output node of the transconductance amplifier will be limited by the current-controlled ring oscillator, thereby restricting the source-drain voltage difference of the NMOS transistor input transistor, forcing the NMOS transistor input transistor to enter the linear region, resulting in a significant reduction in the output impedance. The output current of the transconductance amplifier will be absorbed by the NMOS transistor, and the actual current flowing into the current-controlled ring oscillator is small, that is, the actual gain is small. The traditional scheme only uses a PMOS transistor as the input transistor of the transconductance amplifier, which can provide a high output impedance, but does not perform current multiplexing on the current flowing through the input transistor. Therefore, the energy efficiency and noise efficiency are limited. The floating transconductance amplifier technology proposed by the present invention can maintain the source-drain voltage difference of the NMOS transistor through the floating voltage domain under the condition that the output node voltage is low and the input impedance of the output load is high, so as to maintain the overall output impedance of the floating transconductance amplifier. Furthermore, current multiplexing can be achieved without losing the effective gain, and cooperate with the low-voltage current-controlled ring oscillator to significantly improve the energy efficiency of the overall circuit.

[0066] The integrator uses a low-voltage current-controlled ring oscillator as a time-domain integrator to integrate the current signal output by the transconductance amplifier and convert it into a phase difference between two ring oscillators. The fine quantization digital logic quantizes the phase difference between the ring oscillators into a digital code and outputs it as a fine quantization digital code.

[0067] The fine quantization digital logic also adds the fine quantization output detection logic and the fast tracking control logic in the fast tracking logic circuit. As Figure 2 shown, it extracts, compares, and judges the fine quantization output codewords to generate signals required to control the fine quantization dynamic range tracking, which are used to control the fast tracking execution logic of the coarse quantization level, thereby realizing the continuous tracking of the fine quantization dynamic range of the input.

[0068] C. Chopper Switch

[0069] In specific implementation, four chopper switches are added in the proposed continuous-time incremental tracking scaling sensor readout front-end circuit of the present invention, namely, before the input capacitor, before the DAC switch, after the floating transconductance amplifier, and after the comparator, as Figure 1 shown. By periodically switching the polarity of the chopper switch in the fine quantization period to flip the input signals of each node, the low-frequency input signal can be isolated from the low-frequency flicker noise and DC offset of the DAC switch and the floating transconductance amplifier, and the influence of the flicker noise and DC offset on the output result can be eliminated in the subsequent digital processing process.

[0070] In specific implementation of the present invention, the implementation of the continuous-time incremental tracking scaling sensor readout front-end circuit includes the following steps:

[0071] 1) Prepare a multi-bit SAR sensor readout front-end circuit, which includes three parts: a coarse quantization DAC, a comparator, and a coarse quantization digital logic. The output digital code of the coarse quantization digital logic is connected to the digital input of the coarse quantization DAC, the top plate of the coarse quantization DAC is connected to the comparator input, and the comparator output is connected to the coarse quantization digital logic input. Among them, the coarse quantization digital logic includes an asynchronous SAR logic and an asynchronous counter logic sharing a data register, which are used to perform fast tracking of the fine quantization dynamic range.

[0072] Structurally, a multi-bit SAR sensor readout front-end circuit is used as the coarse quantizer.

[0073] 2) Fabricate a floating transconductance amplifier. Use complementary MOS transistors with their drain terminals connected as the amplifier input transistors. Add a floating current source composed of a current source transistor and a current source bias capacitor on the power supply side of the input transistors to stabilize the operating current and transconductance gain of the amplifier. Add a power supply capacitor that is connected across the input transistors and the floating current source in the operating state to enable the amplifier to operate in a floating voltage domain. Add a current mirror to charge the current source bias capacitor in the charging state. Add MOS transistor switches to switch the power supply capacitor and the current source bias capacitor, and charge the floating power supply capacitor to periodically turn off the output of the amplifier, providing an amplifier dead zone that can be used to eliminate chopper artifacts.

[0074] Structurally, use a floating transconductance amplifier as the transconductance amplifier that plays a key role in the noise performance and noise efficiency in the readout front-end circuit of a multi-bit incremental ΔΣ sensor.

[0075] 3) Fabricate a readout front-end circuit for a multi-bit incremental ΔΣ sensor, which includes four parts: a fine quantization DAC, a transconductance amplifier, an integrator, a quantizer, and fine quantization digital logic. Among them, the transconductance amplifier uses a floating transconductance amplifier, and the integrator uses a low-voltage current-controlled ring oscillator. The fine quantization digital logic includes a fine quantization output detection logic circuit and a tracking control logic circuit, which generates a tracking control signal according to the fine quantization output digital code to control the fast tracking of the fine quantization dynamic range.

[0076] Structurally, use the readout front-end circuit of a multi-bit incremental ΔΣ sensor as the fine quantizer.

[0077] 4) Connect the charge-sharing DAC top plates of the readout front-end circuit of a multi-bit SAR sensor and the readout front-end circuit of a multi-bit incremental ΔΣ sensor to form a shared DAC component. This shared DAC component consists of two capacitor array top plates of different sizes connected together. Among them, the DAC in the readout front-end circuit of the multi-bit SAR sensor is a coarse quantization DAC, and the DAC in the readout front-end circuit of the multi-bit incremental ΔΣ sensor is a fine quantization DAC.

[0078] 5) Use the readout front-end circuit of a multi-bit SAR sensor as the first stage and the readout front-end circuit of a multi-bit incremental ΔΣ sensor as the second stage. Connect the two-stage sensor readout front-end circuits through the top plate of the shared DAC component. Connect the tracking control logic of the fine quantization digital logic in the second stage to the tracking execution logic of the coarse quantization digital logic in the first stage to form a complete fast tracking logic circuit. Add chopper switches before the input, before the input of the shared DAC component, after the output of the floating transconductance amplifier, and after the output of the comparator, and then the improved continuous-time incremental tracking and scaling sensor readout front-end circuit can be obtained.

[0079] As Figure 1As shown, when the continuous-time incremental tracking zoom sensor readout front-end circuit of the present invention is specifically implemented, a 7-bit SAR sensor readout front-end circuit is used for coarse quantization, and a 5-bit incremental ΔΣ sensor readout front-end circuit is used for fine quantization, including 2-bit redundancy between the coarse quantization and the fine quantization levels. In each working cycle, the circuit first resets the fine quantizer. At the same time, if the input exceeds the dynamic range of the fine quantizer in the previous cycle, a coarse quantization SAR conversion is performed in parallel to search for the input signal. After resetting, fine quantization is performed for multiple clock cycles, and during the fine quantization process, the dynamic range of the fine quantizer is continuously controlled by a fast tracking logic circuit to track the change of the input signal. The coarse quantization digital code and the fine quantization digital code obtained in the fine quantization stage are sampled and filtered through a first-order incremental sampling filter, i.e., an accumulator, to obtain the sensor readout digital result output by the overall circuit.

[0080] Specifically, its working mode is as follows:

[0081] 1) Reset and coarse quantization phase

[0082] As Figure 1 shown, at the first clock cycle at the start of each conversion cycle, the reset signal is high, and the integrator and the quantizer output in the fine quantizer will be reset, clearing the residual phase difference in the fine quantizer integrator and the digital code output by the quantizer, and resetting the integrator phase difference and the quantizer output digital code to 0.

[0083] If in the previous conversion cycle, the input signal to the fine quantizer exceeds the dynamic range of the fine quantizer, the fast tracking logic circuit detects this event and generates a SAR enable signal in the reset and coarse quantization phase of the next conversion cycle. At this time, the coarse quantizer will switch to the SAR mode, search for the input signal through an asynchronous SAR conversion process, and place the dynamic range of the fine quantizer near the input signal again. If the input signal remains within the dynamic range of the fine quantizer, the coarse quantizer will maintain the original coarse quantization codeword in this cycle and will not work to reduce the power consumption generated by the SAR conversion process.

[0084] 2) Fine quantization phase

[0085] As Figure 1As shown, during the remaining cycles starting from the second clock cycle in each conversion period, the reset signal is low and the fine quantizer will operate. The floating transconductance amplifier will amplify the residual input signal into a current signal, integrate it on the low-voltage current-controlled ring oscillator integrator, and convert it into an accumulated phase difference. The accumulated phase difference is converted into a phase difference digital pulse signal by the phase detector in the fine quantization logic and sampled by the register as the fine quantization output digital code at the rising edge of the clock. The obtained fine quantization output digital code is fed into the fine quantization DAC for feedback and also fed into the fast tracking logic circuit to determine whether to generate and transfer a control signal to the coarse quantization stage to increase or decrease the coarse quantization codeword.

[0086] As Figure 4 shown, in the fine quantization phase, the operating mode can be further subdivided as follows:

[0087] 1) Charge phase

[0088] In this phase, the connections between the current source transistor and the input transistor of the floating transconductance amplifier and the supply capacitor are disconnected, and the floating transconductance amplifier pauses operation. The supply capacitor of the floating transconductance amplifier is connected to the analog power supply to charge the supply capacitor, charging the voltage difference across the supply capacitor to be close to the analog power supply voltage. At this time, a statically operating current mirror is connected to the current source bias capacitor, charging the gate-source voltage difference required to provide the set current magnitude into the tail current source bias capacitor. At this time, the floating transconductance amplifier is disconnected from the subsequent low-voltage current-controlled ring oscillator integrator, and no output current will be generated. The common-mode voltage value of the output point is maintained by an external bias voltage without being affected by parasitic capacitance coupling. In this phase, since the output of the floating transconductance amplifier has been disconnected from the subsequent stage, the voltage change at the input node will not affect the output result, forming an amplifier dead zone. Therefore, the chopper switch will flip within this phase. The chopper artifacts generated by the chopper switch flipping will be absorbed by the DAC within the dead zone and will not affect the output result of the amplifier.

[0089] 2) Establishment phase

[0090] In this phase, the supply capacitor of the floating transconductance amplifier is completely disconnected from the analog power supply and ground, and the current source transistor and the input transistor will be connected to the supply capacitor. The current source bias capacitor will also be disconnected from the static current mirror and connected between the gate and source of the current source transistor, forming a floating current source structure. At this time, the current provided by the supply capacitor flows through the current source transistor and the input transistor. The input remains connected to the input signal, while the output is still connected to the output point bias voltage. At this time, the source-drain voltage difference of the input transistor of the floating transconductance amplifier gradually builds up, and a stable current and the input transistor gain are formed through the limitation of the current source transistor. When the output point bias voltage is low, the source voltage of the NMOS transistor in the input transistor can drop below the ground voltage to provide a higher source-drain voltage difference for the NMOS to keep the NMOS transistor in the deep saturation region to provide a higher output impedance.

[0091] 3) Integral phase

[0092] In this phase, in addition to establishing the connection of the phase, the output of the floating transconductance amplifier will be connected to the subsequent low-voltage current-controlled ring oscillator integrator. At this time, the differential pressure at the input stage will be converted into the differential-mode output current of the floating transconductance amplifier and flow into the subsequent integrator. At the same time, since the power supply capacitor is completely isolated from the analog power supply and ground and cannot form a current loop, under the limitation of current continuity, no common-mode output current will be generated, and thus the bias point and gain of the subsequent integrator will not be affected. As the phase in which the floating transconductance amplifier actually works and provides gain, this phase will occupy most of the fine quantization period.

[0093] The present invention provides a continuous-time incremental tracking scaling sensor readout front-end circuit and its implementation method, which improves the continuous-time incremental tracking scaling sensor readout circuit, including: a fine quantization dynamic range fast tracking logic circuit based on the output detection of a fine quantizer and a floating transconductance amplifier. The fine quantization dynamic range tracking method designed by the present invention does not introduce additional analog circuit units, makes full use of the low quantization noise characteristics of the multi-bit fine quantizer, directly uses the output codeword of the fine quantizer to estimate the input signal, and avoids the problems of high power consumption and slow tracking response speed existing in the additional analog detection circuit or the prediction circuit for tracking compensation of high input slope after sampling in the traditional tracking technology. At the same time, the floating transconductance amplifier proposed by the present invention has the characteristics of high noise efficiency, simple bias, no need for common-mode feedback, and not being affected by the common-mode voltage at the output point, and can effectively cooperate with the low-voltage current-controlled ring oscillator to further improve the energy efficiency of the overall circuit. Compared with the existing sensor readout front-end circuit, the present invention realizes the characteristics of high energy efficiency, low noise, and high dynamic range, and has broad application prospects in new edge application fields such as the Internet of Things, medical treatment, and wearable devices.

[0094] It should be noted that the purpose of publishing the embodiments is to help further understand the present invention. However, those skilled in the art can understand that various substitutions and modifications are possible without departing from the scope of the present invention and its appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection claimed by the present invention shall be defined by the scope of the claims.

Claims

1. A method for preparing a floating transconductance amplifier, characterized in that, Comprising: Using complementary MOS transistors with their drain terminals connected as the amplifier input transistors, and adding a floating current source composed of a current source transistor and a current source bias capacitor on the power supply side of the input transistors to stabilize the operating current and transconductance gain of the amplifier; Adding a power supply capacitor that is connected across the entire floating current source and the input transistors in the operating state, enabling the amplifier to operate in a floating voltage domain; Adding a charging current mirror for charging the current source bias capacitor in the charging state; Adding a control switch composed of MOS transistors for switching the charging and operating states of the power supply capacitor and the current source bias capacitor, and simultaneously periodically turning off the output of the amplifier through the charging of the power supply capacitor to provide an amplifier dead zone that can be used to eliminate chopper artifacts; The prepared floating transconductance amplifier includes input transistors, a floating current source, a charging current mirror, dummy transistors, a power supply capacitor, and a control switch; The input transistors of the floating transconductance amplifier are powered by the power supply capacitor, being completely disconnected from the power supply and ground; The current flowing out of the power supply capacitor is equal in magnitude to the current flowing into the power supply capacitor. The input transistors do not generate a common-mode current flowing to the output, and do not change the common-mode bias voltage at the output point. Through the change in the voltage of the power supply capacitor with respect to ground, the floating voltage domain provided by the power supply capacitor is shifted to both ends of the original common-mode voltage at the output point. The current source transistor in the floating current source provides a stable gate-source voltage difference through the current source bias capacitor connected between the source and the gate, always being biased in the saturation region to provide output impedance.

2. The method for preparing a floating transconductance amplifier according to claim 1, wherein The input transistors include NMOS transistors and PMOS transistors. The gates of the two types of transistors are connected together to form the input of the floating transconductance amplifier. The drains of the two types of transistors are connected together to form the output of the floating transconductance amplifier. Current multiplexing is achieved by serially connecting two sets of transistors with transconductance gain in the current path of the amplifier. The input transistors use thick-gate transistors to reduce gate leakage, enabling the gate to establish a bias voltage through a pseudo-resistance biasing circuit composed of transistors in the cut-off region; The floating current source includes a current source transistor and a current source bias capacitor; Wherein the current source transistor is a PMOS transistor; the current source bias capacitor is connected between the gate and the source of the current source transistor to provide a constant gate-source bias voltage for the current source transistor. The floating current source is connected in series with the source terminal of the PMOS transistor in the input transistors, and in the operating state, the current flowing through the input transistors is kept constant through the current limiting effect of the current source transistor, stabilizing the power consumption and transconductance gain of the floating transconductance amplifier; The charging current mirror uses a PMOS current mirror to charge the current source bias capacitor in the charging state; The source and drain of the dummy transistors are short-circuited, consuming no power. By cross-connecting the gate and the drain of the input transistors with the opposite polarity to the input transistors, the differential kickback noise generated during the operation of the input transistors is converted into common-mode kickback noise, eliminating the influence of kickback noise on the operation of the transconductance amplifier; The power supply capacitor is connected to the floating current source and the input transistors in the operating state for providing power; The control switch connects or disconnects the power supply capacitor, current source bias capacitor, input transistor, and current source transistor through NMOS and PMOS transistors operating in the linear and cutoff regions, realizing the switching between different operating phases of the floating transconductance amplifier.

3. A method for implementing a continuous-time incremental tracking and scaling sensor readout front-end circuit, characterized in that, To fabricate a floating transconductance amplifier, current multiplexing and low output point voltage are achieved through floating power supply; by directly detecting the output of the fine quantizer, the tracking circuit in the tracking and scaling sensor readout front-end is simplified without introducing additional input detection circuits. By using the output of the fine quantizer to adjust the digital code of the coarse quantizer, dynamic range tracking of fast-changing signals is realized. The steps are as follows: 1) Fabricate a floating transconductance amplifier, including: Use complementary MOS transistors with connected drain terminals as the amplifier input transistors, and add a floating current source composed of a current source transistor and a current source bias capacitor on the power supply side of the input transistors to stabilize the operating current and transconductance gain of the amplifier. Add a power supply capacitor connected across the input transistors and the floating current source in the operating state, enabling the amplifier to operate in a floating voltage domain. Add a charging current mirror for charging the current source bias capacitor in the charging state. Add a control switch composed of MOS transistors for switching the charging and operating states of the power supply capacitor and the current source bias capacitor, and simultaneously periodically turning off the output of the amplifier through the charging of the power supply capacitor to provide a dead zone for the amplifier that can be used to eliminate chopping artifacts. The fabricated floating transconductance amplifier includes input transistors, a floating current source, a charging current mirror, dummy transistors, a power supply capacitor, and a control switch. The input transistors of the floating transconductance amplifier are powered by a power supply capacitor, completely disconnected from the power supply and ground; the currents flowing out of and into the power supply capacitor are of the same magnitude, and the input transistors do not generate common-mode current flowing to the output, without changing the common-mode bias voltage at the output point; through the change in the voltage of the power supply capacitor with respect to ground, the floating voltage domain provided by the power supply capacitor is shifted to both ends of the original common-mode voltage at the output point; the current source transistor in the floating current source provides a stable gate-source voltage difference through the current source bias capacitor connected between the source and gate terminals, always biased in the saturation region to provide output impedance. Then, perform fast tracking of the fine quantization dynamic range, including the execution process of step 2) and the control process of step 3). 2) Fabricate a multi-bit SAR sensor readout front-end circuit, including a coarse quantization DAC, a comparator, and coarse quantization digital logic; the output digital code of the coarse quantization digital logic is connected to the digital input of the coarse quantization DAC, the top plate of the coarse quantization DAC is connected to the input of the comparator, and the output of the comparator is connected to the input of the coarse quantization digital logic; among them, the coarse quantization digital logic includes asynchronous SAR logic and asynchronous counter logic sharing a data register, used to perform fast tracking of the fine quantization dynamic range. 3) Fabricate a multi-bit incremental ΔΣ sensor readout front-end circuit, which includes a fine quantization DAC, a floating transconductance amplifier, an integrator, a quantizer, and a fine quantization digital logic; the output digital code of the fine quantization digital logic is connected to the input of the fine quantization DAC, the top plate of the fine quantization DAC is connected to the input of the transconductance amplifier, the input of the transconductance amplifier is connected to the input of the integrator, the input of the integrator is connected to the input of the quantizer, and the output result of the quantizer is connected to the fine quantization digital logic; the fine quantization digital logic includes a fine quantization output detection logic circuit and a tracking control logic circuit, which generates a tracking control signal according to the fine quantization output digital code for controlling the fast tracking of the fine quantization dynamic range. 4) Connect the charge sharing DAC top plate of the multi-bit SAR sensor readout front-end circuit and the multi-bit incremental ΔΣ sensor readout front-end circuit to form a shared DAC component; among them, the DAC in the multi-bit SAR sensor readout front-end circuit is a coarse quantization DAC, and the DAC in the multi-bit incremental ΔΣ sensor readout front-end circuit is a fine quantization DAC. 5) Use the multi-bit SAR sensor readout front-end circuit as the first stage and the multi-bit incremental ΔΣ sensor readout front-end circuit as the second stage, and connect the two-stage sensor readout front-end circuits through the top plate of the shared DAC component; connect the tracking control logic of the fine quantization digital logic in the second stage to the tracking execution logic of the coarse quantization digital logic in the first stage; then add a chopper switch to obtain a continuous-time incremental tracking and scaling sensor readout front-end circuit.

4. The method for implementing a continuous-time incremental tracking zoom sensor readout front-end circuit according to claim 3, wherein, In step 1), in the fabricated floating transconductance amplifier: The input transistors include NMOS transistors and PMOS transistors. Connect the gates of the two types of transistors together to form the input of the floating transconductance amplifier; connect the drains of the two types of transistors together to form the output of the floating transconductance amplifier; realize current multiplexing by connecting two groups of transistors with transconductance gain in series in the current path of the amplifier; the input transistors use thick gate transistors to reduce gate leakage, so that the gate establishes a bias voltage through a pseudo-resistance biasing circuit composed of transistors in the cut-off region. The floating current source includes a current source transistor and a current source bias capacitor. Among them, the current source transistor is a PMOS transistor; the current source bias capacitor is connected between the gate and the source of the current source transistor to provide a constant gate-source bias voltage for the current source transistor; the floating current source is connected in series with the source terminal of the PMOS transistor in the input transistor, and keeps the current flowing through the input transistor constant through the current limiting effect of the current source transistor during the working state, and stabilizes the power consumption and transconductance gain of the floating transconductance amplifier. The charging current mirror uses a PMOS current mirror to charge the current source bias capacitor in the charging state. The source and drain of the virtual transistor are short-circuited and do not consume any power. By cross-connecting the gate and drain of the input transistor with the opposite polarity to the input transistor, the differential-mode kickback noise generated during the operation of the input transistor is converted into common-mode kickback noise, eliminating the influence of the kickback noise on the operation of the transconductance amplifier. The power supply capacitor is connected to the floating current source and the input transistor during the working state to provide power. The control switch connects or disconnects the power supply capacitor, the current source bias capacitor, the input transistor, and the current source transistor through NMOS and PMOS transistors operating in the linear region and the cut-off region, realizing the switching between different operating phases of the floating transconductance amplifier.

5. The method for implementing a continuous-time incremental tracking zoom sensor readout front-end circuit according to claim 3, characterized in that, Perform fine quantization dynamic range fast tracking, where the control process is specifically implemented in the fine quantization digital logic part in step 3), and the execution process is specifically implemented in the coarse quantization digital logic in step 2); In the coarse quantization digital logic, by fusing the asynchronous SAR logic and the asynchronous bidirectional counter, the SAR conversion and the increase and decrease of the coarse quantization digital code can be controlled, enabling the coarse quantization digital code to track the input signal; in the fine quantization digital logic, through the fine quantization output detection and judgment circuit, the control signal required to make the coarse quantization level track the input signal is provided.

6. The method for implementing a continuous-time delta tracking and scaling sensor readout front-end circuit according to claim 3, characterized in that, Design a fine quantization dynamic range fast tracking logic circuit based on the fine quantization output detection to realize the fine quantization dynamic range fast tracking in steps 2) and 3); The fine quantization dynamic range fast tracking logic circuit based on the fine quantization output detection includes: fine quantization output detection logic, tracking control logic, and tracking execution logic.

7. The method for implementing a continuous-time incremental tracking and scaling sensor readout front-end circuit as claimed in claim 3, wherein In step 3), a low-voltage current-controlled ring oscillator is used as the time-domain integrator for the integrator.

8. The method for implementing a continuous-time delta tracking and scaling sensor readout front-end circuit as claimed in claim 3, wherein In step 4), the shared DAC component is composed of the top plates of two capacitor arrays with different sizes, namely the multi-bit SAR sensor readout front-end circuit and the multi-bit incremental ΔΣ sensor readout front-end circuit, connected together.

9. The method for implementing a continuous-time incremental tracking and scaling sensor readout front-end circuit according to claim 3, wherein In step 5), specifically, chopper switches are added before the input, before the input of the shared DAC component, after the output of the floating transconductance amplifier, and after the output of the comparator.

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