Ultra-low power consumption comparer based on time domain

Abstract

A ultralow power dissipation analog to digital converter based on the time domain belongs to the field of the ultralow power dissipation analog to digital converter, characterized in that, on the basis of the available voltage-time converter VTC, an inversion signal CLKN and a feedback signal of reference output or a NOR gate NOR1 are controlled by a clock control signal CCLK, to cause the discharging process with different speed of the capacitance C1, the capacitance C2 to be interrupted, thereby accordingly advancing the working speed of the comparator.

Description

technical field [0001] The technical field of direct application of "ultra-low power comparator based on time domain" is the circuit design of ultra-low power analog-to-digital converters. The proposed circuit is an important module that can be applied to the main high-speed low-power ADC structure. Background technique [0002] Wireless sensor networks (WSN) have more and more applications in social and natural environments. Due to the advantages of reliability and accuracy of wireless sensor networks, it is especially focused on the fields of military, national security, medical and environmental observation. Generally, wireless sensor networks are composed of a large number of sensor nodes, which makes power consumption an important constraint in the design of sensor networks. Therefore, it is required that each module in the sensor node must consume very low energy. [0003] An analog-to-digital converter (ADC) is generally integrated in the WSN node to convert the ana...

AI Technical Summary

Problems solved by technology

Representative works include, a time-domain based comparator proposed by Andrea Agnes et al. (See references Andrea Agnes, Edoardo Bonizzoni, Piero Malcovati and Franco Maloberti, "A 9.4-ENOB 1V 3.8μW 100kSs SAR ADC with Time_domain comparator ", 2008 IEEE International Solid-State Circuits Conference). Although the time-domain comparator proposed by Andrea Agnes can achieve very low power consumption, it has two major disadvantages: first, the maximum speed of this comparator is only 1.875MHz .This makes the highest sampling rate of the ADC only 100KS / s

The second problem is that a lot of energy is wasted during the comparison; this is because the VTC continues to discharge after the comparator has made the comparison

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