1698results about "Conductive pattern layout details" patented technology

The invention relates to the technical field of printed embedded PCBs, and discloses an embedded PCB and a manufacturing method thereof.The embedded PCB comprises a daughter board, a first dielectric layer and a first circuit layer which are sequentially arranged in a stacked mode in the first direction, a device is embedded in the daughter board, the device is located on the side, close to the first dielectric layer, of the daughter board, and the first dielectric layer is located on the first circuit layer. One side, close to the first dielectric layer, of the device is provided with a first part, and the first part is provided with a first protection part; a first connection hole is formed in the first dielectric layer, a first conductive part is filled in the first connection hole, the first protection part is connected and electrically conducted with the first conductive part, and the first conductive part is connected and electrically conducted with the first circuit layer. The embedded PCB and the manufacturing method thereof provided by the invention are used for improving the problem of poor hole filling in the electroplating hole filling process in the related technology.

A network of Intermediate Device Structure (IDS) members communicatively coupled, mounted to elevated structure / s within urban settings, each configured to operate by a processor / controller with resident code, and in real time receive sensed environmental inputs from each IDS' vicinity, remote data / instruction / s processing the inputs with resident code parameters generating outputs that are configured to mitigate / avert intermittent environmental events harmful / hazardous to humans. The IDS's include a launch and charging pad that hosts a UAV, which patrols an area within communication range of at least one of the IDSs so the UAV, perhaps with AI-engine assistance, can detect events in the area patrolled by the UAV.

The invention discloses a structure and a manufacturing method of a circuit board with interconnection of any layers of through holes, two ends of an isolation strip which needs to be insulated between layers at the through holes of the circuit board are respectively provided with a concave etching position, the concave etching positions serve as isolation rings, and the concave etching positions are formed after an isolation disc arranged on an inner-layer core plate is etched in a concave mode; the manufacturing method comprises the following steps that a circuit board is provided, a drilling position is arranged on the circuit board, and the drilling position is a position needing to be drilled in subsequent processing; the two ends of the interlayer isolation strip needing insulation at the drilling position of the circuit board are each provided with an isolation disc with the outer diameter larger than the outer diameter of the drilling position. A through hole is drilled in the position, corresponding to the drilling position, of the circuit board, so that the isolation disc on the inner layer is exposed in the through hole, then the isolation disc in the hole is removed through concave etching, and a concave etching position serving as an isolation ring is formed; and after the circuit board is subjected to copper deposition and electroplating, a structure of interconnection of any layers of the through holes is formed. According to the method, a plurality of signals can be transmitted in the same hole, and the purpose of interconnection of any layer in the through hole can be achieved.

The invention relates to the technical field of circuit board manufacturing, and discloses a circuit board manufacturing method, an impedance compensation method and a circuit board, and the circuit board manufacturing method comprises the steps: obtaining an inner-layer circuit design drawing of the circuit board; dividing the inner-layer circuit design drawing into a preset number of areas; calculating the residual copper rate of each region; and according to a deviation value between the residual copper rate of each region and a preset standard residual copper rate, adjusting the line width of the line in the corresponding region of the inner-layer line design drawing so as to prepare the inner-layer line of the circuit board by using the adjusted inner-layer line design drawing. The problem of inconsistent impedance caused by dielectric thickness change is solved, and high-speed signal transmission of the circuit board is more stable and reliable.

The present invention provides a semiconductor apparatus achieving interconnection by using an on-chip all-optical switching network module and a manufacturing method therefor. The semiconductor apparatus comprises: a circuit board, which has a plurality of electrical connection paths; an on-chip all-optical switching network module, which is disposed on the circuit board, the on-chip all-optical switching network module comprising a photonic chip and a plurality of analog electrical chips for transceiving which are arranged above the photonic chip, the photonic chip comprising a plurality of communication nodes, a plurality of optical connection paths, and at least one on-chip optical switch which are in corresponding communication connection with the plurality of analog electrical chips for transceiving, and the on-chip optical switch being configured to alter the connection topology among the plurality of communication nodes; and a plurality of computing modules, which are arranged on the circuit board and, by means of the electrical connection paths on the circuit board, are in corresponding communication connection with the plurality of analog electrical chips for transceiving of the on-chip all-optical switching network module, so that the connection topology among the plurality of computing modules can be altered by the on-chip optical switch.

An electronic device includes a substrate, a through hole, a buffer layer, a first circuit structure, and an electronic component. The substrate includes a first side and a second side opposite to the first side. The through hole penetrates the substrate. The buffer layer is disposed on the first side of the substrate, the second side of the substrate, and an inner wall of the through hole. The first circuit structure is disposed on the first side. The electronic component is disposed on the first circuit structure. The buffer layer includes a plurality of layers.

The invention discloses an integration and optimization method of a multilayer circuit board in a photovoltaic inverter, and the method comprises at least seven layers of functional stacked structures which are an electromagnetic shielding layer, a power device layer, a first insulating dielectric layer, a control circuit layer, a second insulating dielectric layer, a heat dissipation substrate layer and a mechanical strengthening layer from top to bottom in sequence. Wherein the power device layer adopts a three-dimensional embedded packaging technology to integrate an IGBT module and a SiC MOSFET module, and a gate drive circuit of the power device layer is embedded into a first insulating dielectric layer in a coplanar waveguide structure; the heat dissipation substrate layer is provided with a micro-channel array with gradient apertures, and the inner wall of each micro-channel is subjected to anodic oxidation treatment to form an Al2O3 ceramic layer with the thickness of 20-50 microns.

An antenna assembly includes a stack and an antenna structure. The stack includes at least one electrically conductive layer structure and at least one electrically insulating layer structure, and a component, at least partially embedded in the stack. At least a portion of the electrically conductive layer structure is provided at the external side of the stack and is configured to act at least as part of an electromagnetic wave coupling structure. The component is coupled to the electromagnetic wave coupling structure. The antenna structure provides an opening to a channel. The stack and the antenna structure are connected so that the electromagnetic wave coupling structure and the opening to the channel face each other.

A quasi-planar transformer can include a first winding comprising one or more turns of wire, a second winding comprising one or more turns of a conductive trace disposed on a printed circuit board, and a magnetic core positioned with respect to the first and second windings so as to provide a magnetic flux path coupling the first and second windings. The first winding can be a primary winding having a first half wound in a clockwise direction on a first side of the printed circuit board and a second half wound in a counterclockwise direction on a second side of the printed circuit board, wherein the first and second halves are formed of a single continuous wire. The single continuous wire can pass through an opening in the printed circuit board. The first and second halves of the primary winding can be secured to the printed circuit board.

The invention discloses an optimized high-speed differential via hole structure, which is characterized in that high-speed differential via holes are arranged in each wiring layer, each wiring layer is provided with a corresponding anti-pad, and corresponding wires are laid in the high-speed differential via holes; marking the part of the wire in each suspension area outside the corresponding anti-bonding pad close to the wiring layer as a suspension wire, marking the part of the wire in the high-speed differential via hole as a via hole wire, thickening the suspension wire, and controlling the suspension wire to be thicker than the via hole wire; and reducing the size of the anti-bonding pad in each non-adjacent wiring layer, and controlling the size of the anti-bonding pad in each non-adjacent wiring layer to be smaller than the size of the anti-bonding pad in each adjacent wiring layer. According to the invention, through combined use of the thickened suspension line, reduction of the non-adjacent wiring layer anti-bonding pad and increase of the adjacent wiring layer anti-bonding pad, the impedance of each part is effectively adjusted, and the impedance requirement of high-speed signal transmission is met; and the optimized mode is high in universality, simple and efficient.

A printed circuit board according to an embodiment comprises: an insulating layer; a circuit pattern disposed on the upper surface of the insulating layer; a support layer which is disposed on the upper surface of the insulating layer to expose the upper surface of the circuit pattern and is in contact with the sides of the circuit pattern; and a protective layer disposed on the upper surfaces of the support layer and the circuit pattern, wherein the upper region of the insulating layer comprises a first region and a second region, and the protective layer comprises an open region exposing the upper surfaces of the support layer and the circuit pattern that are disposed in the first region, and the support layer comprises a first upper surface positioned at the highest level among the upper surfaces of the support layer and a second upper surface positioned at the lowest level among the upper surfaces of the support layer, the second upper surface being lower than the first upper surface, and the protective layer comprises a first portion which contacts the upper surface of the circuit pattern of the first region and a second portion which contacts the upper surface of the support layer of the first region, and the second portion of the protective layer contacts the second upper surface of the support layer and includes a first lower surface which is lower than the upper surface of the circuit pattern.

The invention relates to the technical field of printed circuit board manufacturing, and discloses a manufacturing method of a printed circuit board and the printed circuit board, and the manufacturing method of the printed circuit board comprises the steps: providing a substrate which comprises a dielectric layer and a metal layer, and arranging a first region and a BGA region on one surface, deviating from the dielectric layer, of the metal layer, the metal layer corresponding to the first area is provided with a plurality of shunting grooves, and the metal layer corresponding to the BGA area is provided with a plurality of BGA holes; the substrate is electroplated, an electroplated layer is formed, the electroplated layer comprises a first electroplated part, a plurality of second electroplated parts and at least one third electroplated part, the first electroplated part is located on the inner wall of the BGA hole, and the diversion grooves are filled with the second electroplated parts; and carrying out thinning treatment on the third electroplating part. According to the manufacturing method of the printed circuit board and the printed circuit board provided by the invention, the problem that the plated copper in the BGA area is not easy to remove when the surface copper thickness of the BGA area is increased by adopting a local thickening process in the related technology can be improved.

The invention discloses a multi-layer circuit board structure based on an AMB technology and a preparation technology, and relates to the field of circuit board preparation, and the preparation technology comprises the following steps: providing a plurality of substrates with coating surfaces, and scanning the coating surfaces through a second laser beam to preheat the substrates, spraying welding flux on the coating surface through a spray head with a first ultrasonic generation module to form a welding flux layer; the surface of the solder layer is scanned through a third laser beam, so that the surface of the solder layer is softened, the solder layer is automatically spread and leveled, and a semi-solid solder layer is formed after cooling; and a plurality of substrates are stacked and fixed through a positioning clamp, then each solder layer is scanned through a fourth laser beam, the solder layers are vibrated by a second ultrasonic generation module, and after the solder layers are cooled and solidified to form welding spots, the multilayer circuit board structure is obtained. Through combination of laser and ultrasonic waves, the thickness of the solder layer is uniform, and the surface is smooth; bubbles and impurities in the solder layer are eliminated through laser and ultrasonic combined melting, and the problems of uneven coating and accumulation and bubbling are avoided.

A single circuit board assembly for forming a vehicle-motor interface, the single circuit board assembly includes a first side of a board with logic modules located thereon. The single circuit board assembly also includes a second side of the board with power modules located thereon. The board comprises a plurality of layers, the plurality of layers having at least one through via and at least one buried via defined therein, wherein the at least one through via extends through all of the plurality of layers, the at least one buried via extending through less than all of the plurality of layers.

A printed circuit board (PCB) includes a solder resist layer including at least one of an opening and a depression and a solder resist patch disposed in at least one of the opening and the depression to have an interface with the solder resist layer in at least one of the opening and the depression.

A layout of signal traces includes a first set of signal traces and a second set of signal traces that are used for transmitting a first differential signal and a second differential signal respectively. Each set of signal traces includes a first part, a second part, and a third part along the direction of signal transmission. Different parts of the same signal trace as a whole is not straight. All the first parts are in a first signal layer and parallel. The second parts of the two sets of signal traces are in a second signal layer and the first signal layer, respectively, and are across each other. The second part of the first / second set of signal traces is coupled with the first and third parts of the first / second set of signal traces. All the third parts are in the first signal layer and parallel.

A semiconductor package according to an embodiment includes a first insulating layer; a first circuit pattern disposed on the first insulating layer and including a first pad; a first molding layer disposed on an upper surface of the first insulating layer; a through electrode including a first conductive coupling part disposed on the first pad and having a first width and a through part disposed on the first conductive coupling part and having a second width smaller than the first width, and passing through of the first molding layer; and a second conductive coupling part disposed on the through part of the through electrode; wherein the first width of the first conductive coupling part is smaller than a third width of the second conductive coupling part.

A wiring substrate according to one embodiment includes a plurality of wiring layers and a plurality of insulating layers alternately stacked in a stacking direction. The plurality of wiring layers include a first wiring layer closest to a surface on one side in the stacking direction of the wiring substrate and a second wiring layer second closest to the surface. A distance from the surface to the first wiring layer is larger than a distance from the first wiring layer to the second wiring layer.

The present disclosure relates to flexible printed circuit boards (FPCBs) for augmented reality (AR) eyewear. Disclosed examples provide an FPCB with air gaps for enhanced bending flexibility and an Electromagnetic Interference (EMI) film for consistent ground reference, enabling high-speed signal transmission with controlled impedance. The FPCB may include asymmetrical dielectric thicknesses and a crosshatch pattern in the ground reference layer to further support signal integrity and mechanical durability.

The disclosure relates to a circuit board. A circuit board according to an embodiment of the disclosure may comprise a base layer positioned in a first portion of the circuit board and a second portion of the circuit board different from the first portion of the circuit board, a power line positioned in the first portion of the circuit board, a signal line positioned in the second portion of the circuit board, a shielding layer spaced apart from the power line and the signal line, and a cover layer disposed between the base layer and the shielding layer. The cover layer may include a cover base layer positioned in the first portion and the second portion of the circuit board, a conductive layer positioned in the first portion of the circuit board to correspond to the power line, and disposed between the cover base layer and the shielding layer, and an insulating layer positioned in the second portion of the circuit board to correspond to the signal line, and disposed between the cover base layer and the shielding layer.

According to the printed circuit board and the manufacturing method for the same-layer local multiple-copper-thickness circuit pattern of the printed circuit board, the same-layer high-frequency signal circuit on the printed circuit board is patterned step by step, and the multiple-copper-thickness circuit is accurately constructed in the same circuit layer in combination with the two-time pattern electroplating process and the voltage conversion process. Specifically, a layer of surface copper foil is additionally covered on the surface of the copper foil of the copper-clad substrate to form a voltage-transferring substrate, the surface copper foil is used as a connecting layer between a first circuit layer and a second circuit layer, and two surfaces of the surface copper foil are independently electroplated twice, so that the copper thickness distribution of different circuit areas is accurately controlled, and the voltage-transferring effect is improved. And finally, a plurality of signal circuit patterns with coexisting copper thicknesses are constructed in the surface copper layer on the inner-layer voltage conversion substrate, so that the fineness and reliability of the signal circuit are ensured to meet the high-frequency signal transmission requirement, the layout flexibility of the signal circuit on the printed circuit board is improved, the impedance matching of the signal circuit is ensured, and the signal loss is reduced at the same time.

The invention relates to a system and method for implementing a scalable system. A multi-chip system (100) and structure for modular extension is described. In some embodiments, bonding strips (150) are used to couple adjacent chips (102, 104). For example, a communication bar (150) may be used to couple a logic chip (104), and a memory bar (150) may be used to couple a plurality of memory chips (102) to the logic chip (104).

A voltage converting circuit comprises a multi-layer printed-circuit-board stack having an input terminal and a reference terminal, first and second switching elements connected to each other at an output terminal and a parallel-plate capacitor connected with the first and the second switching elements; the stack comprises a top conductive layer provided with said input, reference and output terminals and with a plurality of power-conducting traces, a first and a second metal plane forming said electrodes of the parallel-plate capacitor, a first and a second signal layer having first and second signal-routing traces, wherein the first and the second metal plane are arranged between the top conductive layer and two signal layers, and wherein the top conductive layer and the first metal plane are separated from each other by an insulating layer of the stack only.

A strain gauge includes a flexible substrate, a resistor, and electrodes. Each electrode includes first patterns juxtaposed at predetermined intervals and electrically connected to each other. Second patterns of which longitudinal directions are toward a same direction as a longitudinal direction of each of the first patterns are disposed between opposing electrodes. The second patterns are electrically floating dummy patterns. The second patterns of which the longitudinal directions are toward a same direction as the longitudinal direction of each first pattern are disposed, the second patterns being interposed between first patterns opposite each other that are among given first patterns that constitute one of the electrodes and given first patterns that constitute another electrode. The plurality of second patterns are interposed between first patterns opposite each other that are among given first patterns that constitute one of the electrodes and given first patterns that constitute another electrode.

A multilayer board structure includes a plurality of light emitting devices, each light emitting device of the plurality of light emitting devices having a plurality of electrodes formed on a terminal surface thereof, and a multilayer board including a plurality of stacked substrates and implemented with the plurality of light emitting devices. An uppermost substrate of the plurality of stacked substrates has a surface formed with metal layers coupling electrodes of the plurality of light emitting devices. Remaining substrates of the plurality of stacked substrates, other than the uppermost substrate, have surfaces formed with metal layers, respectively. A number of metal layers located directly below the electrodes of the plurality of light emitting devices is the same for each of the electrodes.

The invention belongs to the technical field of electronics, and particularly relates to a low parasitic inductance and miniaturized power packaging structure which comprises a PCB intermediate layer, a power supply unit and a chip unit, the power supply unit and the chip unit are electrically connected with the PCB intermediate layer, and the PCB intermediate layer comprises a plurality of circuit layers; the power supply circuit is arranged in the multi-layer circuit layer, one end of the power supply circuit is electrically connected with the power supply unit, and the other end of the power supply circuit is electrically connected with the chip unit; and the control circuit is arranged in the multi-layer circuit layer, one end of the control circuit is electrically connected with the chip unit, and the other end of the control circuit is electrically connected with the control end. The packaging structure integrally forms a three-dimensional commutation loop and a compact layout, more power devices can be integrated in a limited space, and the power density can be greatly improved while the size is reduced.

A phased array antenna system includes a flexible printed circuit board formed of a flexible material. The flexible printed circuit board includes a component layer, an antenna layer, and a phase matching layer between the component layer and the antenna layer. A control unit is coupled to the component layer. A plurality of antenna elements are coupled to the antenna layer. A plurality of signal paths extend through the component layer, the phase matching layer, and the antenna layer. Each of the plurality of signal paths connects the control unit to a respective one of the plurality of antenna elements. The control unit provides an independent phase controllable source, which allows beams emitted from the antenna elements to be steered.

The invention provides a high-frequency multilayer circuit board processing method and a high-frequency multilayer circuit board. The high-frequency multilayer circuit board processing method comprises the following steps: obtaining an inner-layer core board, a prepreg and a copper foil, and carrying out lamination treatment on the inner-layer core board, the prepreg and the copper foil to obtain a laminated board body; wherein the number of the inner-layer core plates is multiple; carrying out drilling treatment on the laminated plate body; carrying out riveting treatment on the laminated plate body after drilling; fusing the riveted laminated board body to obtain a semi-finished product of the high-frequency multilayer circuit board; performing film coating treatment on the semi-finished product of the high-frequency multilayer circuit board; laminating the semi-finished product of the high-frequency multi-layer circuit board coated with the film; and carrying out post-processing treatment on the laminated semi-finished product of the high-frequency multilayer circuit board. According to the processing method of the high-frequency multilayer circuit board, the high-frequency multilayer circuit board is relatively high in use reliability.

An embodiment of the disclosure provides a circuit substrate and a tiled electronic device. The circuit substrate includes a substrate and first to third metal layers. The first metal layer is disposed on the substrate and includes first and second connection lines, and first and second scan lines. The first and second connection lines are electrically connected to the first and second scan lines, respectively. The second scan line includes two separate line segments respectively located at opposite sides of the first connection line. The second metal layer is disposed on the substrate and includes a first data line. The first data line is overlapped with the first connection line. The third metal layer is disposed on the substrate and includes a bridge line. The bridge line is electrically connected to the line segments. The second metal layer is disposed between the first and third metal layers.