Optimized high-speed differential via hole structure, electronic equipment and system

Abstract

The invention discloses an optimized high-speed differential via hole structure, which is characterized in that high-speed differential via holes are arranged in each wiring layer, each wiring layer is provided with a corresponding anti-pad, and corresponding wires are laid in the high-speed differential via holes; marking the part of the wire in each suspension area outside the corresponding anti-bonding pad close to the wiring layer as a suspension wire, marking the part of the wire in the high-speed differential via hole as a via hole wire, thickening the suspension wire, and controlling the suspension wire to be thicker than the via hole wire; and reducing the size of the anti-bonding pad in each non-adjacent wiring layer, and controlling the size of the anti-bonding pad in each non-adjacent wiring layer to be smaller than the size of the anti-bonding pad in each adjacent wiring layer. According to the invention, through combined use of the thickened suspension line, reduction of the non-adjacent wiring layer anti-bonding pad and increase of the adjacent wiring layer anti-bonding pad, the impedance of each part is effectively adjusted, and the impedance requirement of high-speed signal transmission is met; and the optimized mode is high in universality, simple and efficient.

Description

Technical Field

[0001] The present invention relates to the technical field of high-speed digital PCB design, and particularly to an optimized structure of high-speed differential vias, an electronic device, and a system. Background Art

[0002] PCB is short for Printed Circuit Board, which is one of the important components of the electronics industry. Conductive patterns, such as copper foils, are printed or etched on an insulating substrate to support and connect various electronic components, realizing electrical connections between circuits. High-speed digital PCB refers to a printed circuit board specifically designed to handle high-speed signal transmission, and is widely used in high-end electronic products such as computers, communication devices, and medical instruments.

[0003] In order to ensure the reliable transmission of high-speed signals above 25 Gbps, such as 25 Gpbs, 32 Gpbs, 56 Gbps, and 112 Gbps, etc., it is required that the physical transmission channel of the PCB has very small impedance fluctuations. As the largest impedance discontinuity point on the PCB board, further optimizing the structure of such vias will bring great benefits to the transmission of high-speed signals above 25 Gbps. However, traditional differential vias do not clearly define high-speed differential vias. Due to the inertia of design, if the differential vias used for high-speed signals with a rate of 25 Gbps and above still follow the differential vias of 10 Gbps rate without discrimination and further optimization, this will significantly affect the signal performance of rates above 25 Gbps.

[0004] Currently, when optimizing high-speed differential vias, for example, when optimizing a certain specific model of multi-layer PCB device with high-speed differential vias, firstly, the original process can be changed to a higher-level process to meet the transmission requirements, but the cost often increases significantly and may affect the overall layout, and even requires re-designing each stack-up and actual wiring, and the workload may be very large; secondly, based on parameters such as the PCB node constant, via size, and preset anti-pad size corresponding to the device, as an existing model, strict calculation of the new anti-pad size is carried out to obtain the optimized size required for the anti-pad, but the calculation process is also very cumbersome and lacks universality, and each time a different actual device is encountered, it needs to be re-designed. The preset anti-pad size refers to the default isolation distance preset for specific types of vias or component pins during the design of multi-layer PCBs.

[0005] That is to say, these measures currently taken have at least the following two problems: 1) High cost and large workload may be involved; 2) The process is cumbersome and lacks universality. Summary of the Invention

[0006] In view of the above two problems, the object of the present invention is to propose an optimized structure of high-speed differential vias, an electronic device and a system. By combining the thickening of the floating lines, the reduction of the anti-pads in the non-adjacent routing layers and the increase of the anti-pads in the adjacent routing layers, the impedance of each part can be effectively adjusted to meet the impedance requirements during high-speed signal transmission. At the same time, without changing the process, the optimized method has high versatility, simplicity and efficiency.

[0007] It is achieved by the following technical solutions: First, an optimized structure of high-speed differential vias is proposed An optimized structure of high-speed differential vias is applied to a multi-layer PCB. The multi-layer PCB includes a plurality of adjacent routing layers and a plurality of non-adjacent routing layers that are parallel to each other. The high-speed differential vias are provided in each routing layer and corresponding anti-pads are provided in each layer. Corresponding traces are laid in the high-speed differential vias; the part of the trace in the floating area outside the corresponding anti-pad in each adjacent routing layer is denoted as the floating line, the part of the trace in the high-speed differential via is denoted as the via line, the floating line is thickened, and the floating line is controlled to be thicker than the via line; the size of the anti-pad in each non-adjacent routing layer is reduced, and the size of the anti-pad in each non-adjacent routing layer is controlled to be smaller than the size of the anti-pad in each adjacent routing layer.

[0008] Preferably, the size of the anti-pad in each adjacent routing layer is increased to improve the impedance of each adjacent routing layer.

[0009] Preferably, the increased sizes of the anti-pads in each adjacent routing layer are the same.

[0010] Preferably, the reduced sizes of the anti-pads in each non-adjacent routing layer are the same.

[0011] Preferably, the plurality of adjacent routing layers at least include two adjacent first adjacent routing layers and two adjacent second adjacent routings, and a plurality of non-adjacent routing layers are between the two adjacent first adjacent routing layers and the two adjacent second adjacent routings.

[0012] Preferably, the number of layers of the plurality of non-adjacent routings is greater than the number of layers of the plurality of adjacent routing layers.

[0013] Secondly, an electronic device is proposed. The electronic device is internally provided with a multi-layer PCB, and the multi-layer PCB adopts the structure of the high-speed differential vias as described above.

[0014] In addition, a system is also proposed. The system is internally provided with a controller, and the controller is connected to an electronic device as described above.

[0015] The beneficial effects of the present invention compared with the prior art are: The technical solution of the present invention effectively adjusts the impedance of each part by combining the use of thickened suspended lines, reduced anti-pads on non-adjacent wiring layers, and increased anti-pads on adjacent wiring layers, so as to meet the impedance requirements during high-speed signal transmission. At the same time, there is no need to change the process, and the optimized method has high versatility, simplicity and efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic structural diagram of an optimized high-speed differential via in a multi-layer PCB; Figure 2 It is a schematic structural diagram of widening the trace in the suspended area outside the anti-pad; Figure 3 It is a schematic structural diagram of reducing the anti-pad on the non-adjacent wiring layer; Figure 4 It is a schematic structural diagram of increasing the anti-pad on the adjacent wiring layer; Figure 5 It is a schematic diagram of comparing the impedance results after optimizing the high-speed differential via in different ways. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0017] Next, the technical solutions in the embodiments of the present invention will be described in detail in conjunction with the attached Figures 1 to 5 , in the embodiments of the present invention.

[0018] As Figure 1 shown, it is a schematic structural diagram of an optimized high-speed differential via in a multi-layer PCB. The multi-layer PCB includes a plurality of parallel adjacent wiring layers and a plurality of non-adjacent wiring layers. One or more high-speed differential vias are arranged in each wiring layer and corresponding anti-pads are arranged on each layer. Corresponding traces are laid in the high-speed differential vias. Taking two adjacent high-speed differential vias in the middle as an example, 10 in the figure represents the increased anti-pad on the adjacent wiring layer, 20 represents the thickened trace in the suspended area on the anti-pad, 30 represents the plane layer of each non-adjacent wiring layer, 40 represents the reduced anti-pad in the plane layer of each non-adjacent wiring layer, and 50 represents the plane board of each adjacent wiring layer.

[0019] As Figure 2 shown, it is a schematic structural diagram of widening the trace in the suspended area outside the anti-pad; as Figure 3 shown, it is a schematic structural diagram of reducing the anti-pad on the non-adjacent wiring layer; as Figure 4 shown, it is a schematic structural diagram of increasing the anti-pad on the adjacent wiring layer; combined with Figures 1 to 4 , for the optimization of any high-speed differential via, there are three optimization methods: Optimization 1, Optimization 2, and Optimization 3. Figure 3 and 4When the respective vertical arrows are centered on the center point of a high-speed differential via, they are used to characterize the plane where they are located. And in the case of multiple high-speed differential vias, the centers of the multiple high-speed differential vias are on a straight line.

[0020] For the three optimization methods, the part of the trace in the suspended area outside the anti-pad corresponding to each adjacent trace layer is denoted as the suspended trace, and the part of the trace in the high-speed differential via is denoted as the via trace. Optimization 1 is to thicken the suspended trace, controlling the suspended trace to be thicker than the via trace, so as to compensate for the problem of high impedance in the suspended area and reduce the impedance corresponding to the trace in the suspended area. Optimization 2 is to reduce the size of the anti-pad in each non-adjacent trace layer to be smaller than the preset anti-pad size, to compensate for the relatively high impedance problem in these layers and effectively reduce the impedance of each non-adjacent trace layer; the multiple adjacent trace layers include at least two adjacent first adjacent trace layers and two adjacent second adjacent traces. Between the two adjacent first adjacent trace layers and the two adjacent second adjacent traces are multiple non-adjacent trace layers. Reducing the impedance in the middle is actually equivalent to reducing the distance of the trace at both ends of the via, which is more convenient for high-speed signal transmission. Optimization 3 is to increase the size of the anti-pad in each adjacent trace layer to be larger than the preset anti-pad size, and also make the size of the anti-pad in each non-adjacent trace layer smaller than the size of the anti-pad in each adjacent trace layer, so as to effectively compensate for the problem of low impedance in each adjacent trace layer and increase its impedance effectively.

[0021] In this embodiment, there are five combined usage methods for the three optimization methods in actual application, including: a. Optimization 1 is used alone; b. Optimization 2 is used alone; c. Optimization 1 and Optimization 2 are used in combination; d. Optimization 1 and Optimization 3 are used in combination; e. Optimization 1, Optimization 2, and Optimization 3 are used in combination.

[0022] As Figure 5 shown, it is a schematic diagram of the impedance result comparison after optimizing a high-speed differential via in different ways, showing the impedance comparison curves after using the above five combined methods for the same high-speed differential via respectively. Among them, the blue is the original impedance curve of the high-speed differential via without any optimization, and the red is the corresponding improved impedance curve. It can be seen that each method can optimize the impedance, thus better meeting the transmission requirements of high-speed signals. And the effect of using the three optimizations together is the best.

[0023] It should be emphasized that Optimization 3 cannot be used alone. If Optimization 3 is to be used, it must be combined with at least Optimization 1; because if the dangling lines outside the anti-pad are not thickened and only the anti-pad of the adjacent trace layer is increased, more traces will be left dangling, resulting in a higher impedance mutation of the dangling part of the trace. The impedance mutation of the dangling trace will become the determining factor, making the overall impedance continuity worse rather than better.

[0024] In this embodiment, the increased size of the anti-pad in each adjacent trace layer is the same, and the reduced size of the anti-pad in each non-adjacent trace layer is the same. Controlling the same size change is convenient for improving the coherence of impedance.

[0025] In this embodiment, the number of non-adjacent trace layers is greater than the number of adjacent trace layers.

[0026] Secondly, an electronic device is proposed. The electronic device is internally provided with a multi-layer PCB, and the multi-layer PCB adopts the structure of the high-speed differential via as described above.

[0027] In addition, a system is also proposed. The system is internally provided with a controller, and the controller is connected to an electronic device as described above.

[0028] In summary, the present invention effectively adjusts the impedance of each part by combining the thickening of the dangling line, the reduction of the anti-pad of the non-adjacent trace layer, and the increase of the anti-pad of the adjacent trace layer, so as to meet the impedance requirements during high-speed signal transmission; at the same time, without changing the process, the optimization method has high versatility, is simple and efficient, and has significant progressiveness.

[0029] The above embodiments are only used to illustrate the technical idea of the present invention, and the protection scope of the present invention cannot be limited thereby. Any modification made on the basis of the technical solution according to the technical idea proposed by the present invention falls within the protection scope of the present invention.

Claims

1. An optimized structure of high-speed differential vias, which is applied to a multi-layer PCB, is characterized in that The multi-layer PCB includes a plurality of adjacent trace layers and a plurality of non-adjacent trace layers that are parallel. High-speed differential vias are provided in each trace layer and corresponding anti-pads are provided in each layer. Corresponding traces are laid in the high-speed differential vias. The part of the trace in the suspended area outside the corresponding anti-pad in each adjacent trace layer is denoted as the suspended line, the part of the trace in the high-speed differential via is denoted as the via line, the suspended line is thickened, and the suspended line is controlled to be thicker than the via line; the sizes of the anti-pads in each non-adjacent trace layer are reduced, and the sizes of the anti-pads in each non-adjacent trace layer are controlled to be smaller than the sizes of the anti-pads in each adjacent trace layer.

2. The structure of an optimized high-speed differential via according to claim 1, wherein The sizes of the anti-pads in each adjacent trace layer are increased to improve the impedance of each adjacent trace layer.

3. The structure of an optimized high-speed differential via according to claim 2, wherein, The increased sizes of the anti-pads in each adjacent trace layer are the same.

4. An optimized structure of a high-speed differential via according to claim 1, characterized in that The reduced sizes of the anti-pads in each non-adjacent trace layer are the same.

5. An optimized high-speed differential via structure according to claim 1, characterized in that, The plurality of adjacent trace layers include at least two adjacent first adjacent trace layers and two adjacent second adjacent traces. Between the two adjacent first adjacent trace layers and the two adjacent second adjacent traces are a plurality of non-adjacent trace layers.

6. The structure of an optimized high-speed differential via according to claim 1, wherein The number of layers of the plurality of non-adjacent traces is greater than the number of layers of the plurality of adjacent trace layers.

7. An electronic device, characterized in that, The electronic device is internally provided with a multi-layer PCB, and the multi-layer PCB adopts the optimized high-speed differential via structure described in any one of claims 1 to 6.

8. A system, characterized in that, The system is internally provided with a controller, and the controller is connected to an electronic device as described in claim 7.

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