A device comprises a discrete-time linear
equalizer circuit. The discrete-time linear
equalizer circuit includes a sample-and-hold switching logic that incorporates several switched-
capacitor circuits. The multiple switched-
capacitor circuits include at least one switched-
capacitor circuit for a precursor tap, one switched-capacitor circuit for a cursor tap, and one switched-capacitor circuit for a trailing tap.A
clock-controlled switching logic circuit is used to connect a capacitor in the circuit with the
switched capacitor of the predecessor tap to a negative
signal input for a first period, a capacitor in the circuit with the
switched capacitor of the cursor tap to a positive
signal input for a second period, and a capacitor in the circuit with the
switched capacitor of the trailing tap to the negative
signal input for a third period. The
clock-controlled switching logic circuit is also used to connect the capacitors of the circuits with the switched capacitors in parallel for a fourth period.