59results about How to "Improve interconnect reliability" patented technology

The present invention relates to a method for connecting an integrated circuit chip to a circuit substrate. The method includes the step of pre-applying adhesive directly to a bumped side of an integrated circuit chip. The method also includes the steps of removing portions of the adhesive from the tips of the solder bumps to expose a contact surface, and pressing the bumped side of the integrated circuit chip, which has previously been coated with adhesive, against the circuit substrate such that the bumps provide an electrical connection between the integrated circuit chip and the circuit substrate. The adhesive is removed from the tips of the solder bumps using a solvent assisted wiping action. The pre-applied adhesive on the chip forms a bond between the integrated circuit chip and the circuit substrate.

An integrated circuit (IC) package for an IC device, and a method of making the same. The IC package includes an interconnect assembly with at least one printed compliant layer, a plurality of first contact members located along a first major surface, a plurality of second contact members located along a second major surface, and a plurality of printed conductive traces electrically coupling a plurality of the first and second contact members. The compliant layer is positioned to bias at least the first contact members against terminals on the IC device. Packaging substantially surrounds the IC device and the interconnect assembly. The second contact members are accessible from outside the packaging.

An area array integrated circuit (IC) package for an IC device. The IC package includes a first substrate with conductive traces electrically coupled to the IC device. An interconnect assembly having a first surface is mechanically coupled to the first substrate. The interconnect assembly includes a plurality of contact members electrically coupled to the conductive traces on the first substrate. A second substrate is mechanically coupled to a second surface of the interconnect assembly so that the first substrate, the interconnect assembly, and the second substrate substantially surround the IC device. The second substrate includes conductive traces that are electrically coupled to the contact members in the interconnect assembly.

A method of fabricating a semiconductor device, having an interim reduced-oxygen Cu-Zn alloy thin film (30) electroplated on a blanket Cu surface (20) disposed in a via (6) by electroplating, using an electroplating apparatus, the Cu surface (20) in a unique chemical solution containing salts of Zn and Cu, their complexing agents, a pH adjuster, and surfactants; and annealing the interim electroplated Cu-Zn alloy thin film (30); filling the via (6) with further Cu (26); annealing and planarizing the interconnect structure (35); and a semiconductor device thereby formed. The reduction of electromigration in copper interconnect lines (35) is achieved by decreasing the drift velocity in the copper line (35)/via (6), thereby decreasing the copper migration rate as well as the void formation rate, by using an interim conformal Cu-rich Cu-Zn alloy thin film (30) electroplated on a Cu surface (20) from a stable chemical solution, and by controlling the Zn-doping thereof, which improves also interconnect reliability and corrosion resistance.

The invention discloses a superconducting quantum bit chip, comprising a quasi-one-dimensional network chain structure layout superconducting quantum bit array and a manipulating and reading microwavecircuit, wherein each mesh unit comprises n qubits, and m (m and n are natural numbers, n>m>=2) shared qubits between adjacent networks are used for interconnection between mesh units; Each superconducting qubit in the mesh unit is coupled to the same coplanar superconducting microwave cavity for interconnection of qubits in the network. Each qubit is coupled to a coplanar superconducting microwave cavity and further coupled to a coplanar microwave transmission line, and is connected to an external circuit for qubit state reading. The present application can effectively prevent the possibility of qubit interconnection breakpoints, greatly improve interconnection reliability, increase the flexibility of error correction coding design, effectively reduce the complexity of qubit manipulationand reading circuits, and has an important scientific research and industrial application prospect.

The difficulties encountered in conventional LED multiple chip modules where wire bonding is used to connect the chips to electrodes can be overcome by using an interconnect to connect the chip to electrodes in a module where the interconnect is supported at points along its length other than at endpoints thereof, by a carrier either directly or indirectly. This improves reliability of the interconnect over conventional designs. Preferably, the contacts of the chips, and the electrodes are all within, or do not extend beyond, two parallel planes that are 400 microns apart for a compact design.

An airgap interconnect structure with hood layer and methods for forming such an airgap interconnect structure are disclosed. A substrate having a dielectric layer with a plurality of interconnects formed therein is provided. Each interconnect is encapsulated by a barrier layer. A hardmask is formed on the dielectric layer and patterned to expose the dielectric layer between adjacent interconnects where an airgap is desired. The dielectric layer is etched to form a trench, wherein the etching process additionally etches at least a portion of the barrier layer to expose a portion of the side surface of each adjacent copper interconnect. A hood layer is electrolessly plated onto an exposed portion of the top surface and the exposed portion of the side surface to reseal the interconnect. A gap-sealing dielectric layer is formed over the device, sealing the trench to form an airgap.

Increasing standoff height for surface mount components mounted to a laminate by image screening at least one standoff structure in a footprint area on the laminate surface. The standoff structure may comprise a filled epoxy and curing agents and may be cured by thermal treatment or by exposure to actinic radiation. The use of legend ink as a standoff structure offers a method and a structure for improving component standoff height without additional processing operations or cost.

The present invention relates to a method for connecting an integrated circuit chip to a circuit substrate. The method includes the step of pre-applying adhesive directly to a bumped side of an integrated circuit chip. The method also includes the steps of removing portions of the adhesive from the tips of the solder bumps to expose a contact surface, and pressing the bumped side of the integrated circuit chip, which has previously been coated with adhesive, against the circuit substrate such that the bumps provide an electrical connection between the integrated circuit chip and the circuit substrate. The adhesive is removed from the tips of the solder bumps using a solvent assisted wiping action. The pre-applied adhesive on the chip forms a bond between the integrated circuit chip and the circuit substrate.

A method of reducing electromigration in a dual-inlaid copper interconnect line (3) by filling a via (6) with a Cu-rich Cu-Zn alloy (30) electroplated on a Cu surface (200 from a stable chemical solution, and by controlling the Zn-doping thereof, which also improves interconnect reliability and corrosion resistance, and a semiconductor device thereby formed. The method involves using a reduced-oxygen Cu-Zn alloy as fill (30) for the via (6) in forming the dual-inlaid interconnect structure (35). The alloy fill (30) is formed by electroplating the Cu surface (20) in a unique chemical solution containing salts of Zn and Cu, their complexing agents, a pH adjuster, and surfactants, thereby electroplating the fill (30) on the Cu surface (20); and annealing the electroplated Cu-Zn alloy fill (30); and planarizing the Cu-Zn alloy fill (30), thereby forming the dual-inlaid copper interconnect line (35).

The invention belongs to the technical field of materials, and provides a directional interconnection method for Cu6Sn5-base single-crystal lead-free solder joints for high-temperature packaging. The method comprises the steps of firstly, preparation of a Cu6Sn5-base single-crystal block body, secondly, cutting of the Cu6Sn5-base single-crystal block body, thirdly, surface pretreatment of a Cu-base welding disc, and fourthly, interconnection of Cu6Sn5-base single-crystal welding blocks. The elasticity modulus of the Cu6Sn5-base single-crystal lead-free interconnected solder joints prepared with the method is 235% of that of common Sn-base brazing filler metal, the conductivity of the Cu6Sn5-base single-crystal lead-free interconnected solder joints is 52.4% that of the Sn-base brazing filler metal, and the heat conductivity of the Cu6Sn5-base single-crystal lead-free interconnected solder joints is 57.8% that of the Sn-base brazing filler metal. The method has the beneficial effects of being low in cost, resistant to high temperature, high in reliability of interconnection of the solder joints and a Cu-base welding disc, high in creep-resistance, and capable of being used for a long time under the severe condition. The method has the beneficial effects of being simple in working principle, low in cost, rapid in single-crystal preparation and high in quality.

Methods to increase metal interconnect reliability are provided. Methods include forming a conformal barrier layer within an opening in a semiconductor device structure and forming a copper alloy material above the conformal barrier layer. Next, removing the copper alloy material that extends beyond the opening. Removing native oxide from a top surface of the copper alloy material. Further, annealing or applying a plasma treatment to the copper alloy material. Finally, forming a capping layer above the copper alloy material. Notably, near the top of the copper alloy material, smaller copper grain growth may be present. Furthermore, more non-copper alloy atoms are present near the top of the copper alloy material than the bulk of the copper alloy material.

The invention discloses a millimeter-wave air slot differential integrated antenna. The millimeter-wave air slot differential integrated antenna comprises five parts, namely, a differential feeding network, a radiation module, a directed radiation module, a bond wire compensation network and a back cavity air slot; each of the radiation module and the directed radiation module is composed of an even number of radiating patch units which are in bilateral symmetry; signals are divided and transmitted to each radiating patch unit through a differential line and a one-to-many T-shaped structure; the back surface ground part of the antenna is partially etched; an air cavity is formed in a base, so that the bandwidth of the antenna can be extended; the antenna is connected with a chip through bond wires; in order to compensate the inductive effect of the bond wires, a capacitive patch is arranged between the bond wires, so that an L(inductor)-C(capacitor)-L(inductor) network can be formed, and therefore, interconnection loss of the antenna and the chip can be reduced; and in order to extend the bandwidth of the antenna, parasitic patches are arranged beside the radiating patch units. According to the millimeter-wave air slot differential integrated antenna of the invention, a dielectric material of which the height is consistent with the height of the chip is adopted to design the antenna, and therefore, the sticking, bonding and packaging of the antenna and the chip can be benefitted.

The invention refers to a kind of network interconnecting management method based on asynchronous transfer mode. The method includes: at first, sets up the interconnecting path of ATM net appliances;then, ATM net appliance carries on the setup of network topological diagram through the finding process of adjoining net appliance; at the same time, it also includes the update and maintenance of topological diagram; finally, carries on the ATM interconnection management according to the network topological diagram. The invention provides user of convenience to the ATM network management.

The invention discloses a printed circuit board. The printed circuit board mainly comprises multiple first structures and second structures which are overlapped in a lamination manner, wherein the first structures and the second structures are arranged at intervals; the first structures and the second structures are formed in a hot-pressing manner; the first structures mainly consist of circuit carriers; conductive convex blocks and circuit layers are embedded in the circuit carriers; the conductive convex blocks are electroplated on the circuit layers; the second structures mainly consist of insulating dielectric plates; conductive blocks are embedded in the insulating dielectric plates; and the circuit layers on the adjacent two first structures are connected through the conductive blocks. Compared with the prior art, the printed circuit board provide by the invention enables fine circuits to satisfy special impendence characteristic requirement; meanwhile, the prepared circuit is high in conductivity and low in cost; the first structures and the second structures are overlapped in a crossed manner in sequence, so that the printed circuit at any layer can be formed by one-time lamination; and therefore, the printed circuit board is high in production efficiency and capable of reducing the production time and the production cost.

There is disclosed a conductive particle used for an anisotropic conductive connection material for establishing conductive interconnection between e.g. a substrate and an electrical component. The conductive particle includes a base particle (2) exhibiting electrical conductivity at least on its surface and a continuous insulating resin film (3) formed by welding of fine particles (3a) of an insulating resin that composes the resin film. The surface of the base particle is coated with the continuous insulating resin film. There are formed voids at least between neighboring fine particles.

A method to form a titanium nitride (TiN) hard mask in the Damascene process of forming interconnects during the fabrication of a semiconductor device, while the type and magnitude of stress carried by the TiN hard mask is controlled. The TiN hard mask is formed in a multi-layered structure where each sub-layer is formed successively by repeating a cycle of processes comprising TiN and chlorine PECVD deposition, and N₂/H₂ plasma gas treatment. During its formation, the stress to be carried by the TiN hard mask is controlled by controlling the number of TiN sub-layers and the plasma gas treatment duration such that the stress may counter-balance predetermined external stress anticipated on a conventionally made TiN hard mask, which causes trench sidewall distortion, trench opening shrinkage, and gap filling problem.

The invention discloses an electronic device integrating a near-field communication NFC antenna, wireless charging and a display screen. The electronic device comprises a near-field communication NFCantenna and/or wireless charging antenna and display screen integrated assembly, a main printed circuit board PCB and a battery. The near-field communication NFC antenna and/or wireless charging antenna and display screen integrated assembly comprises a display screen assembly and a near-field communication NFC antenna and/or wireless charging antenna assembly. The display screen assembly comprises a flexible printed circuit board FPC and a display module. The flexible printed circuit board FPC comprises an area for providing a driving IC or a touch control IC, a connector for interconnectingwith the main printed circuit board PCB and a protruding portion area. The near-field communication NFC antenna and/or wireless charging antenna assembly is arranged on the protruding portion area ofthe flexible printed circuit board FPC. The electronic device can effectively utilize the space of the device, improves integration level, reduces metal spring assemblies, reduces assembly link and saves cost.

The invention discloses a local large-area welding plate-level interconnection integration method for an airtight packaging unit, in particular to a local large-area welding plate level interconnection integration method for a bonding pad enhanced airtight packaging unit. Manufacturing of an enhanced bonding pad on a substrate is completed through an HTCC process; airtight packaging is realized through multi-temperature gradient welding of the packaging substrate, the composite enclosure frame and the cover plate; high-reliability plate-level interconnection of the airtight packaging unit andthe system mother board is completed through a tin-lead solder ball/solder column and composite enclosure frame structure combined welding method.

The invention relates to a copper interconnection forming method. The method includes: forming low dielectric material layers on a semiconductor substrate; etching a through hole and a groove on the low dielectric material layers respectively; forming a diffusion barrier layer in the through and the groove; forming a Cu layer and a Cu alloy layer on the diffusion barrier layer; and reflowing and annealing the Cu alloy layer to enable alloy elements in the Cu alloy layer to be diffused into the lower Cu layer, so that electromigration reliability of copper interconnection is improved effectively.