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Size-filtered multimetal structures

a multi-metal structure and filtering technology, applied in the direction of semiconductor devices, semiconductor/solid-state device details, electrical devices, etc., can solve the problems of requiring compromise among various device performance requirements, the integration of various metallic device components within the same level of metal interconnect structure,

Inactive Publication Date: 2013-02-21
IBM CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present patent describes a method for creating a structure with two different metallic materials in a dielectric layer on a substrate. The method includes forming two trenches with different widths, depositing a blocking material layer to fill both trenches, and then removing the blocking material layer in one trench while keeping it in the other. The resulting structure has two metallic materials with different compositions and widths. The method can be used to create an eFuse, which is an electrically programmable fuse. The technical effect of this patent is the creation of a structure with two different metallic materials in a dielectric layer on a substrate, which can be used for various applications such as eFuse programming.

Problems solved by technology

Thus, integration of various metallic device components within the same level of metal interconnect structure may require compromise among various device performance requirements.

Method used

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Embodiment Construction

[0019]As stated above, the present disclosure relates to size-filtered multimetal structures in which metal lines having different widths have different metallic compositions, an electrically programmable fuse (eFuse) employing a different material for a metallic fuselink than for a metallic anode and a metallic cathode, and methods of manufacturing the same, which are now described in detail with accompanying figures. It is noted that like and corresponding elements mentioned herein and illustrated in the drawings are referred to by like reference numerals.

[0020]Referring to FIGS. 1A and 1B, an exemplary structure according to an embodiment of the present disclosure includes a substrate 10 and a dielectric layer 20 formed thereupon. The substrate 10 can be a semiconductor substrate including at least one semiconductor device such as a field effect transistor, or can be a combination of a semiconductor substrate and at least one metal interconnect structure. A metal interconnect str...

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Abstract

A size-filtered metal interconnect structure allows formation of metal structures having different compositions. Trenches having different widths are formed in a dielectric material layer. A blocking material layer is conformally deposited to completely fill trenches having a width less than a threshold width. An isotropic etch is performed to remove the blocking material layer in wide trenches, i.e., trenches having a width greater than the threshold width, while narrow trenches, i.e., trenches having a width less than the threshold width, remain plugged with remaining portions of the blocking material layer. The wide trenches are filled and planarized with a first metal to form first metal structures having a width greater than the critical width. The remaining portions of the blocking material layer are removed to form cavities, which are filled with a second metal to form second metal structures having a width less than the critical width.

Description

BACKGROUND[0001]The present disclosure relates to interconnect level structures and particularly to size-filtered multimetal structures in which metal lines having different widths have different metallic compositions, an electrically programmable fuse (eFuse) employing a different material for a metallic fuselink than for a metallic anode and a metallic cathode, and methods of manufacturing the same.[0002]Interconnect level structures, which are also referred to as back-end-of-line (BEOL) interconnect structures, are employed in semiconductor chips to provide horizontal and vertical electrical connections among various semiconductor devices and / or between semiconductor devices and input / output pads that are connected to pins on a packaging substrate. Metal lines provide horizontal electrical connection, and metal vias provide vertical interconnection. Metal lines and metal vias are embedded in dielectric layers, which are located on a semiconductor substrate on which various semico...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L23/525H01L21/28H01L21/20H01L23/48
CPCH01L23/5256H01L21/76877H01L23/528H01L2924/0002H01L2924/00
Inventor HORAK, DAVID V.KOBURGER, III, CHARLES W.PONOTH, SHOMYANG, CHIH-CHAO
Owner IBM CORP
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