System for automatically converting hardware language VHDL (Vhsic Hardware Description Language) into MSVL (Modeling, Simulation and Verification Language)

Abstract

The invention relates to a system for automatically converting a hardware language VHDL (Vhsic Hardware Description Language) into an MSVL (Modeling, Simulation and Verification Language). The system can convert a VHDL language program file into an MSVL language program file; the conversion system comprises a file analysis module, a lexical analysis module, a syntactic analysis, an information storage module, a translation module and a translation result character string connection module. After a VHDL program is converted into an MSVL program, model construction and property description use the same language, so that verification is carried out in the same logic framework and indirect model detection on the VHDL language program is conveniently realized. In the converting process, the VHDL program is converted into the semantic equivalent MSVL program by making conversion rules of different grammatical structure through a plurality of additional auxiliary means, so that correctness of a source VHDL program can be ensured by carrying out simulation, model construction and verification on the equivalent MSVL program.

Description

technical field [0001] The present invention relates to lexical analysis and grammatical analysis in the technical field of hardware description language VHDL and the technical field of compiling principles, in particular to an automatic conversion system from VHDL to MSVL, which is used to convert hardware circuit programs described by VHDL into semantically equivalent MSVL codes . Background technique [0002] The full name of VHDL is Very-High-Speed ​​Integrated Circuit Hardware Description Language, which was born in 1982. At the end of 1987, VHDL was recognized as a standard hardware description language by IEEE and the US Department of Defense. Since IEEE-1076 (version 87 for short), each EDA company has launched its own VHDL design environment one after another, or announced that its own design tools can interface with VHDL. In 1993, IEEE revised VHDL, expanded the content of VHDL from a higher level of abstraction and system description capabilities, and announced ...

AI Technical Summary

Problems solved by technology

[0006] In addition, the modeling, simulation, and verification language MSVL and the ha...

Images