The invention discloses a TMSVL (timed modeling
simulation verification logic) real-
time system modeling method belonging to the field of formal modeling and verifying. According to the method, the TMSVL extended from the MSVL (modeling
simulation verification logic) can model and verify the real-
time system in the same logic frame. The TMSVL real-
time system modeling method comprises the following steps: initializing a
system clock, establishing a TMSVL model of the
system and simplifying the TMSVL model. According to the method, the
system clock with an explicit formulation of time variables is defined, the basic TMSVL sentences and common
delay, overtime and interruption concepts in the real-time system can be defined and the TMSVL operational
semantics are provided according to the system
clock. After the real-time system is described by the TMSVL sentences, the operational
semantics can simplify the TMSVL sentences so as to form a practical model of the system. The TMSVL real-time system modeling method disclosed by the invention is extended from the MSVL, has all advantages of the MSVL, can represent relative and absolute time constraints, and is suitable for modeling, simulating and verifying the real-time system.