Broadband arbitrary reference adaptive clock synchronization device

Abstract

The invention relates to the field of clock synchronization, in particular to a broadband arbitrary reference adaptive clock synchronization device. An input signal is amplified and shaped to generate two paths of signals, one path of signals is sent to an FPGA, the other path of signals is sent to an orthogonal power divider and then is mixed with a local oscillator signal through an orthogonal modulator to obtain a frequency mixing signal, the frequency mixing signal passes through a fixed frequency divider to obtain a frequency division signal, the frequency division signal and a DDS output signal are subjected to phase discrimination to generate error voltage, and the error voltage passes through a low-pass filter to control a crystal oscillator. The output of the crystal oscillator passes through the coupler to generate two paths of signals, one path is used as a global system clock, the other path passes through the fixed frequency multiplier to obtain a frequency-doubled signal, the frequency-doubled signal passes through the filter amplifier to the power divider, the power divider divides the frequency-doubled signal into two paths of signals, one path is used as a reference clock, and the other path is used as a reference clock; a corresponding frequency point generation output signal is generated under the control of the FPGA, and the other path of signal is used as a local oscillator signal of the quadrature modulator after passing through the amplifier. The invention is applicable to the self-adaptive clock synchronization device.

Description

Technical Field

[0001] The present invention relates to the field of clock synchronization, and particularly to a broadband arbitrary reference adaptive clock synchronization device. Background Art

[0002] Clock synchronization is an important part of electronic technology and communication technology. It has a wide range of applications in fields such as device co-reference, device cascading, etc. With the diversification of requirements, the traditional fixed 10MHz reference clock of instruments has been difficult to meet the needs of users. More and more application scenarios require the reference clock to achieve broadband adaptive coverage. Therefore, it is becoming increasingly important to design a synchronization circuit with broadband arbitrary reference.

[0003] Conventional instruments usually require an external reference clock input, most of which are a fixed 10MHz or 100MHz. Most instruments will have a high-performance local clock built-in, such as 100Mhz, and then use an integer phase detector to lock 10MHz or 100MHz to the built-in clock frequency. This method is simple and low-cost, but its disadvantages are also obvious. It only supports fixed frequency points, and due to the very narrow loop filter usually, its synchronization range is also limited.

[0004] Such as Figure 1 In the traditional clock synchronization scheme of the shown instrument, an integer phase detector is mostly used, and a relatively narrow filter is used to achieve synchronization with the external reference. Its reference output is equal to an integer multiple of the reference input, and the loop filter parameters are fixed. These limitations make it difficult for this scheme to meet the new requirements of broadband reference adaptability. Summary of the Invention

[0005] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a broadband arbitrary reference adaptive clock synchronization device, which realizes clock synchronization with broadband arbitrary reference adaptability.

[0006] The present invention adopts the following technical solutions to achieve the above purpose. The present invention provides a broadband arbitrary reference adaptive clock synchronization device, which includes an amplification and shaping circuit unit 1, a quadrature power divider 2, a quadrature modulator 3, a fixed frequency divider 4, a phase detector 5, a low-pass filter 6, a crystal oscillator 7, a coupler 8, a fixed frequency multiplier 9, a filter amplifier 10, a power divider 11, a DDS (Direct Digital Synthesizer) module 12, an amplifier 13, and an FPGA (Field-Programmable Gate Array) module 14; The input wideband reference signal is shaped by the amplification and shaping circuit unit 1 to generate two signals. One of the signals is sent to the FPGA module 14 for frequency counting, and the other signal is sent to the quadrature power divider 2 to generate two orthogonal signals which are output to the quadrature modulator 3. The two orthogonal signals are mixed with the local oscillator signal by the quadrature modulator 3 to obtain the mixed signal F4. The mixed signal F4 is divided by the fixed frequency divider 4 to obtain the divided signal F5. The divided signal F5 and the output signal F3 from the DDS module 12 are phase-detected to generate an error voltage, which is processed by the low-pass filter 6 to control the crystal oscillator 7 in real time. The output of the crystal oscillator 7 passes through the coupler 8 to generate two output signals. One of the output signals is used as the global system clock, and the other output signal is multiplied by the fixed multiplier 9 to obtain the multiplied signal F2. The multiplied signal F2 is processed by the filter amplifier 10 and then output to the power divider 11. The power divider 11 divides the multiplied signal F2 into two signals. One of the signals of the multiplied signal F2 is used as the reference clock of the DDS module 12, and under the control of the FPGA module 14, it generates corresponding frequency points to generate the output signal F3. The other signal of the multiplied signal F2 is used as the local oscillator signal of the quadrature modulator 3 after passing through the amplifier 13.

[0007] Further, the output signal F3 of the DDS module is F3 = F2(FTW / 2 b ) = N*F1*(FTW / 2 b ), where F2 = N*F1. In the formula, FTW is the frequency control word of the DDS, b is the number of bits of the DDS module 12, and F1 is one of the output signals used as the global system clock.

[0008] Further, the quadrature modulator 3 is mixed with the local oscillator signal to obtain the mixed signal F4, F4 = F2 + Fref. The mixed signal F4 is divided by the fixed frequency divider 4 to obtain the divided signal F5, F5=(F2 + Fref) / R. Then F5=(N*F1 + Fref) / R. In the formula, Fref represents the input reference frequency, N is the multiplication factor of the fixed multiplier 9, and R is the division factor of the fixed frequency divider 4.

[0009] Further, when the FPGA module 14 completes the synchronization configuration of the DDS module, the output signal F3 of the DDS module is equal to the divided signal F5, then: F5=(N*F1 + Fref) / R = N*F1*(FTW / 2 b ); Fref = R*N*F1*(FTW / 2 b ) - N*F1.

[0010] The beneficial effects of the present invention are: The present invention introduces the self - mixing technology. The frequency - doubled signal F2 obtained after frequency - doubling the output frequency is introduced into the reference port of the phase - detector to achieve self - mixing with the reference frequency Fref, and then the divided - frequency signal F5 is obtained through a fixed frequency divider. Through this operation, not only the input operating frequency bandwidth is reduced, but also the reference frequency is increased, the equivalent frequency - doubling times are reduced, and the phase noise is improved.

[0011] In the feedback loop of the present invention, the output of the DDS is used as the feedback frequency, and the high resolution of the DDS is used to ingeniously achieve any required input frequency.

[0012] The present invention uses an orthogonal power divider and an orthogonal modulator for reference modulation, ingeniously avoiding the local oscillator and image frequencies. If a traditional mixing and filtering scheme is adopted, it will be very difficult to design the filter to achieve the suppression of frequencies deviated from 1 MHz.

[0013] The present invention introduces an FPGA module to perform real - time counting on the input reference Fref and dynamically configure the output frequency of the DDS, realizing the adaptive configuration of the input reference without manual intervention. Description of the Drawings

[0014] Figure 1 is the block diagram of the clock synchronization circuit structure of the conventional instrument and equipment provided by the present invention; Figure 2 is the block diagram of a broadband arbitrary reference adaptive clock synchronization device provided by the present invention. Detailed Embodiments

[0015] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0016] The present invention provides a broadband arbitrary reference adaptive clock synchronization device, as Figure 2 shown, including an amplification and shaping circuit unit 1, an orthogonal power divider 2, an orthogonal modulator 3, a fixed frequency divider 4, a phase - detector 5, a low - pass filter 6, a crystal oscillator 7, a coupler 8, a fixed frequency - multiplier 9, a filter amplifier 10, a power divider 11, a DDS module 12, an amplifier 13, and an FPGA module 14; The input wideband reference signal is shaped by the amplification and shaping circuit unit 1 to generate two signals. One of the signals is sent to the FPGA module 14 for frequency counting, and the other signal is sent to the quadrature power divider 2 to generate two orthogonal signals which are output to the quadrature modulator 3. The two orthogonal signals are mixed with the local oscillator signal by the quadrature modulator 3 to obtain the mixed signal F4. The mixed signal F4 is divided by the fixed frequency divider 4 to obtain the divided signal F5. The divided signal F5 and the output signal F3 from the DDS module 12 are phase-detected to generate an error voltage which is processed by the low-pass filter 6 to control the crystal oscillator 7 in real time. The output of the crystal oscillator 7 passes through the coupler 8 to generate two output signals. One of the output signals is used as the global system clock, and the other output signal is multiplied by the fixed frequency multiplier 9 to obtain the multiplied signal F2. The multiplied signal F2 is processed by the filter amplifier 10 and then output to the power divider 11. The power divider 11 divides the multiplied signal F2 into two signals. One of the signals of the multiplied signal F2 is used as the reference clock of the DDS module 12, and under the control of the FPGA module 14, it generates corresponding frequency points to generate the output signal F3. The other signal of the multiplied signal F2 is used as the local oscillator signal of the quadrature modulator 3 after passing through the amplifier 13.

[0017] The specific process of the synchronization configuration is as follows: The first step: The controller FPGA module 14 performs frequency counting on the input frequency to complete the confirmation of the input frequency value to obtain Fref; The second step: The controller FPGA module 14 calculates the output frequency F5 of the fixed frequency divider 4 according to the calculated input frequency value Fref, and then configures the output frequency F3 of the DDS according to the calculated value of F5 such that F3 = F5 to complete the synchronization configuration.

[0018] The working principle of the present invention is as follows: F2 = N * F1, and the output of the DDS is F3 = F2 * FTW / 2 b = N * F1 * FTW / 2 b , where FTW is the frequency control word of the DDS, b is the number of bits of the DDS module, and the output of the quadrature modulator 3 is F4 = F2 + Fref. The output after passing through the fixed frequency divider 4 is F5 = (F2 + Fref) / R. After arrangement: F5 = N * F1 + Fref / R; In the formula, N is the multiplication factor of the fixed frequency multiplier 9, and R is the division factor of the fixed frequency divider 4; When the FPGA module 14 completes the configuration of the DDS module, F3 = F5. Therefore, F5 = N * F1 + Fref / R = N * F1 * FTW / 2 b . After arrangement, Fref = R * N * F1 * FTW / 2 b - N * F1; As can be seen from the F5 calculation formula, the bandwidth of the original broadband reference is reduced by 1 / R after passing through the fixed frequency divider 4. At the same time, due to the introduction of the internal clock F2 for self-mixing, the phase detection frequency is increased while reducing the bandwidth to avoid significant phase noise deterioration. On the other hand, it can be seen from the Fref calculation formula that the resolution of any reference is determined by the DDS. When a high-bit DDS is selected, almost any resolution can be achieved.

[0019] In an embodiment of the present invention, the input frequency is 1 MHz - 100 MHz, its bandwidth is as high as 100 MHz, the frequency division coefficient R of the fixed frequency divider 4 is 40, the output frequency F1 of the oven-controlled crystal oscillator 7 is a fixed value of 100 MHz, and the frequency multiplication coefficient N of the fixed frequency multiplier 9 is 10. Therefore, the range of the phase detection frequency F5 is 25.05 - 27.5 MHz. It can be seen that the reference change range is less than 2.5 MHz after frequency division, which effectively reduces the circuit design pressure. The DDS is AD9912 with a bit width of 48 bits, which can achieve a resolution of 4 uHz. This embodiment can preferably output a constant 100 MHz synchronous clock automatically according to any external Fref value.

[0020] The above are only the preferred embodiments of the present invention. It should be understood that the present invention is not limited to the form disclosed herein, should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be changed within the scope of the concept described herein through the above teachings or the technology or knowledge in related fields. And any changes and modifications made by those skilled in the art without departing from the spirit and scope of the present invention should fall within the protection scope of the appended claims of the present invention.

Claims

1. A broadband arbitrary reference adaptive clock synchronization device, characterized in that It includes an amplification and shaping circuit unit (1), a quadrature power divider (2), a quadrature modulator (3), a fixed frequency divider (4), a phase detector (5), a low-pass filter (6), a crystal oscillator (7), a coupler (8), a fixed frequency multiplier (9), a filter amplifier (10), a power divider (11), a DDS module (12), an amplifier (13), and an FPGA module (14); The input broadband reference signal is shaped by the amplification and shaping circuit unit (1) to generate two signals. One of the signals is sent to the FPGA module (14) for frequency counting, and the other signal is sent to the quadrature power divider (2) to generate two orthogonal signals, which are output to the quadrature modulator (3). The two orthogonal signals are mixed with the local oscillator signal by the quadrature modulator (3) to obtain a mixed signal F4. The mixed signal F4 is divided by the fixed frequency divider (4) to obtain a divided signal F5. The divided signal F5 is phase-detected with the output signal F3 from the DDS module (12) to generate an error voltage, which is processed by the low-pass filter (6) to control the crystal oscillator (7) in real time. The output of the crystal oscillator (7) passes through the coupler (8) to generate two output signals. One of the output signals is used as the global system clock, and the other output signal is multiplied by the fixed frequency multiplier (9) to obtain a multiplied signal F2. The multiplied signal F2 is processed by the filter amplifier (10) and then output to the power divider (11). The power divider (11) divides the multiplied signal F2 into two signals. One of the signals of the multiplied signal F2 is used as the reference clock of the DDS module (12), and under the control of the FPGA module (14), it generates corresponding frequency points to generate the output signal F3. The other signal of the multiplied signal F2 passes through the amplifier (13) and is used as the local oscillator signal of the quadrature modulator (3).

2. The broadband arbitrary reference adaptive clock synchronization device according to claim 1, characterized in that The output signal F3 of the DDS module (12) is F3 = F2(FTW / 2 b ) = N*F1*(FTW / 2 b ), where F2 = N*F1. Here, FTW is the frequency control word of the DDS module, b is the number of bits of the DDS module (12), and F1 is an output signal serving as the global system clock.

3. The broadband arbitrary reference adaptive clock synchronization device according to claim 2, wherein The quadrature modulator (3) mixes with the local oscillator signal to obtain a mixed signal F4, F4 = F2 + Fref. The mixed signal F4 is divided by the fixed frequency divider (4) to obtain a divided signal F5, F5 = (F2 + Fref) / R, then F5 = (N*F1 + Fref) / R, where Fref represents the input reference frequency, N is the multiplication factor of the fixed frequency multiplier (9), and R is the division factor of the fixed frequency divider (4).

4. The broadband arbitrary reference adaptive clock synchronization device according to claim 3, characterized in that, When the FPGA module (14) completes the synchronous configuration of the DDS module (12), the output signal F3 of the DDS module (12) is equal to the divided signal F5, then: F5 = (N * F1 + Fref) / R = N * F1 * (FTW / 2 b ); Fref = R * N * F1 * (FTW / 2 b ) - N * F1。

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