79results about How to "Improve electrical performance parameters" patented technology

The invention relates to a high potential gradient zinc oxide pressure-sensitive resistor material and a preparation process thereof. The high potential gradient zinc oxide pressure-sensitive resistor material with uniform particle sizes is obtained by weighing a main material ZnO, a doping oxide, and a product rare earth oxide obtained by carrying out thermal decomposition on a rare earth oxalate or/and carbonate or/and hydroxide according to proportions, carrying out high energy wet grinding, drying, presintering at 200-800DEG C, carrying out high energy dry grinding, and sintering at 800-1100DEG C. The preparation process of the invention has the advantages of simplicity, low cost, environmental protection and low energy consumption, and the prepared zinc oxide pressure-sensitive resistor material can be used for preparing high quality lightning arrester products for ultrahigh electric power systems.

The invention, which relates to the technical field of the solar energy, discloses a wet etching process and equipment, and a solar cell and manufacturing method thereof. Therefore, problems of etching black line occurrence and square resistance increasing according to the existing wet etching process can be solved; and elimination of the phosphorosilicate glass layer and the back junction is realized and an objective of back polishing is achieved, thereby improving the conversion efficiency of the solar cell. The wet etching process comprises the following steps that: first corrosive liquid is used for carrying out corrosion on the lower surface and the side surface of a solar cell so as to remove the phosphorosilicate glass layer at the lower surface and the side surface of the solar cell, wherein the first corrosive liquid is a hydrofluoric acid solution; alkali liquor is used for carrying out corrosion on the lower surface of the solar cell so as to remove the PN junction at the lower surface of the solar cell and realize the polishing effect of the lower surface f the solar cell; and second corrosive liquid containing hydrofluoric acid is used for carrying out corrosion on the solar cell, thereby removing the phosphorosilicate glass layer at the upper surface of the solar cell.

The invention discloses a vegetable insulating oil treating full-set process which includes the following steps: 1 conducting alkali refining, washing, decoloration and deodorization on vegetable oil; 2 filtering and dehydrating refined vegetable oil; 3 adsorbing the dehydrated vegetable oil, dehydrating the adsorbed vegetable oil and adding antioxidant into the oil. The step 3 includes (1) adding the oil subjected to vacuum dehydration into an adsorption container, utilizing argil as an adsorbent, adding 2-4% of argil, meanwhile heating the oil to enable the oil temperature to reach 45-70 DEG C, stirring the mixture for 2-4h with the rotating speed as 55-75 r/min and utilizing a slag extractor to conduct argil filtering treatment on the oil; (2) further filtering the vegetable oil, enabling the oil to pass through a filter screen and enter the vacuum dehydration process and repeating the step (2); (3) pumping the vegetable oil into a cooling stirring tank, conducting quick stirring at the speed of 30-60 r/min, adding an additive and maintaining the stirring speed for 3-5h. By means of the technical scheme, the obtained insulation oil reaches the standard for transformer oil, excellent vegetable insulation oil is obtained, and the oil can be greatly popularized in use.

The invention discloses an epitaxial growing method of an LED. The method comprises the steps of processing a substrate, growing a low-temperature buffer layer GaN, growing an undoped GaN layer, growing an N-type GaN layer doped with Si, growing an InAlGaN/SiAlN superlattice layer, growing a luminous layer, growing a P-type AlGaN layer, growing a P-type GaN layer doped with Mg and conducting cooling. According to the technical scheme, the InAlGaN/SiAlN superlattice layer is introduced after growing of the N-type GaN layer doped with Si and before growing of the luminous layer, and due to the introduction of the InAlGaN/SiAlN superlattice layer, the N-layer current distribution of the LED is improved, and the luminous intensity of the LED is improved.

The invention relates to a TFT-LCD array substrate and a manufacturing method thereof. The array substrate comprises a grid wire, a data wire, a pixel electrode and a thin film transistor. The array substrate is characterized in that the thin film transistor comprises a grid electrode connected with the grid wire and a source electrode connected with the data wire; at least one through hole is formed on the grid electrode or a through groove is formed on at least one side of the grid electrode; and a semiconductor layer which is connected with the pixel electrode and the source electrode respectively is filled in the through hole or the through groove. The array substrate changes a 'planar type' TFT structure which is universally adopted in the prior art, changes the planar structure into a spatial structure, and has the characteristics of simple and compact structure, good parameter property, simple manufacturing process and the like. The array substrate realizes the effect of increasing the starting current and has certain improvement on other electrical parameters, and the spatial structure of the array substrate reduces the planar size and increases the spatial utilization rate so as to increase the opening ratio.

The present invention discloses a LED epitaxy superlattice growth method. The method comprises in order: processing a substrate, growing a low-temperature buffer layer GaN, growing an un-doping GaN layer, growing an N-type GaN layer doping Si, growing an InAlN/Mg2N3 superlattice layer, growing a luminescent layer, growing a P-type AlGaN layer, growing a P-type GaN layer doping Mg, and performing cooling. The InAlN/Mg2N3 superlattice layer is introduced after the growth of the N-type GaN layer doping Si and prior to the growth of the luminescent layer so as to extend the LED current, improve the LED luminous efficiency and allow the electrical parameters of the LED to be better.

The invention relates to a manufacture method of a high-efficiency cell with a front emission junction and backside tunneling oxidation and passivation contact. Texturing is carried out after removing a damage layer of a silicon chip, a B-doped P+ emission junction of a low surface concentration is formed, an ultrathin tunneling oxide layer SiO2 and a P-doped polysilicon layer are grown in the back side of the silicon chip after edge insulation and backside polishing, an alumina layer is deposited in the surface of the P+ emission junction, a hydrogenated amorphous silicon nitride passivation antireflection layer is grown in the front side of the silicon chip in a PECVD or magnetron sputtering method, a Ag/Al slurry is printed in the front side of the silicon chip, a full aluminum backfield Al-BSF structure is formed in the back side of the silicon chip, and a drying furnace is used to implement drying. Compared with the prior art, the ultrathin tunneling oxide SiO2 layer (<2nm) and the P-doped silicon layer are used to reduce metal-semiconductor surface combination in the backside greatly, and the manufacture method has the obvious advantage that electric performance parameters can be improved greatly on the basis that the method is compatible with a traditional cell manufacturing technology.

The invention belongs to the technical field of low-temperature and superconducting application and particularly relates to a low-temperature insulating structure of a gas-cooled lead. The structure provided by the invention comprises a vacuum flange and a three-layer insulating structure which is arranged on the outer surface of the gas-cooled lead, wherein the three-layer insulating structure comprises a lead inner protective layer, a low-temperature insulating layer and an outer protective layer which are sequentially arranged from interior to exterior; and the vacuum flange is connected with the gas-cooled lead which is arranged at the inner core of the three-layer insulating structure through bolts. The low-temperature insulating structure provided by the invention can stand a 5min power frequency voltage test of a more than 35kV voltage class, a thunder impulse voltage test, a partial discharge test, a 15min alternating current withstand voltage test, a direct current withstand voltage test and the like, has the advantages of excellent electric property parameters, reasonable electric field and magnetic field distribution, low heat leakage and integral vacuum tightness withstand voltage properties with a stainless steel liquid nitrogen container, and can be used for improving the stability of a system and greatly lowering the investment cost.

The invention discloses a preparation method of a series-parallel thin film battery assembly. The method is mainly characterized in that a piece of TCO conductive glass is equally divided into two parts, which are the same in area, through a laser etching line, wherein the two parts are a series conductive portion and a parallel conductive portion, the series conductive portion is used for carrying out laser scribing on series sub-batteries, the parallel conductive portion is used for carrying out laser scribing on parallel sub-batteries, the series sub-batteries and the parallel sub-batteries are respectively connected by using a drainage strip and a bus bar, and then the series conductive portion and the parallel conductive portion are connected so as to manufacture the required series-parallel thin film battery assembly. According to the preparation method disclosed by the invention, a defect that the film uniformity is poor after large-area film plating is considered, characteristics of a series circuit and a parallel circuit are combined, and problems brought about by film difference and series connection of the sub-batteries are solved. Optimization for electrical parameters is carried out in allusion to a characteristic of high voltage or high current in the electrical parameters of a thin film battery, thereby avoiding influences imposed on such factors as inverter model selection and power station design in power station construction in a later period.

The invention relates to a back emitter junction back-surface tunnel oxidation and passivation contact efficient battery production method, comprising: removing the damage layer of a silicon wafer and making velvets; and then performing edge insulation and back polishing; growing an ultra-thin tunnel oxide layer SiO2 on the back of the silicon wafer; using the PECVD method or other CVD methods to grow a B-doped polysilicon layer on the ultra-thin tunnel oxide layer SiO2; depositing an aluminum oxide layer on the surface of the B-doped polysilicon layer; growing a hydrogenated amorphous silicon nitride passivation antireflective layer on the front surface of the silicon wafer; and finally, printing Ag slurry on the front surface of the silicon wafer to form an all-aluminum back-field A1-BSF structure at the back surface. Compared with the prior art, the method could replace the N type back emitter crystalline silicon battery back point contact mechanism through the utilization of an ultra-thin tunnel oxide layer SiO2 and a B-doped polysilicon layer. Such a composed layer could greatly reduce the composition of the back surface metal and the semiconductor surface.

The invention provides a solar panel preparing method, which comprises the steps of: a, preparing a-Si:H film on the surface of a silicon chip after texturing; b, treating the silicon chip containing the a-Si:H film on the surface obtained in the step a at 800 to 900 DEG C for 60 to 120 min; and c, carrying out corrosion treatment on the surface of the silicon chip treated through high temperature. The solar panel preparing method has the advantages that a layer of a-Si:H film is deposited on the back surface of the silicon chip after the texturing, the problems of many impurities and micro defects in the silicon chip can be perfectly solved, the electrochemical performance such as the service life, the photoelectric conversion efficiency and the like of solar panels is improved, in addition, good back side and body passivation effects can be realized, the current and voltage (I-V) character of solar batteries is improved, and simultaneously, the process is simple and is easy to implement.

The invention discloses a preparation method of an epitaxial wafer for an 8-inch high-power IGBT component. The method includes following steps: preparing a substrate: selecting an 8-inch substrate with a p-doped middle resistance, wherein the resistivity is 3-25 ohm*cm, and a back-sealing structure is in a polycrystalline (Poly) back-sealing mode; HCl polishing: selecting the HCl flow of 1-2 L/min at the temperature lower than 1080 DEG C with the polishing time of 2 minutes, and performing purging with high-flow H2 for 3 minutes after completion of polishing; and epitaxial growth: selecting at least three layers of epitaxial process conditions, wherein a silicon source employs ultra-high-purity trichlorosilane, the epitaxial growth of each layer employs the same growth temperature and growth rate, an epitaxial layer with flat resistivity is grown on a first layer, an intermediate transition layer is grown on an intermediate layer through introduction of a doping source with a variabledoping flow, and a high-resistance epitaxial layer is grown on a final layer. According to the method, the growth of the epitaxial layer of each layer employs the same growth rate and growth temperature so that the controllability of epitaxial parameters of products in a batch production process is facilitated.

The invention relates to a high-vacuum surface-mounted miniature tuning fork quartz crystal resonator and a manufacturing method thereof. The resonator comprises a ceramic base, a miniature tuning fork wafer and a metal cover plate; the ceramic base is formed by sequentially superposing a ceramic bottom plate, a ceramic backing plate, a ceramic ring plate and a kovar alloy ring from bottom to top,wherein the bottom of the ceramic bottom plate is provided with a metal pad, and a left protruding bonding pad and a right protruding bonding pad are arranged on the ceramic backing plate. The resonator is manufactured through a high-vacuum baking degassing process, a sealing nitrogen parallel seam welding process and a high-vacuum laser spot welding process. The manufacturing method is simple and rapid, and the manufactured resonator is reliable in quality, long in service life and excellent in electrical performance.

The invention belongs to the technical field of manufacturing of electrolytic capacitors, and particularly discloses a method for removing an adhesive in an anode block of a solid electrolytic capacitor. Treatment is carried out through the following 11 steps of dissolving, spaying, drying, compression, reciprocating sifting, first elution, standing, second elution, third elution, boiling and drying in all, so that the adhesive and a solvent can be removed clean without a residue, improvement of electric performance parameters of the capacitor is facilitated, meanwhile, fine powder particles blocked in micropores and powder particles adhered to the surface of an anode blank are also burst through, the capacity extraction rate of the capacitor is improved, and the probability of crystallization when an anode is formed is reduced. According to the method, increase of the content of impurities of carbon and oxygen in the tantalum blank is effectively suppressed, the porosity in the tantalum blank is improved and the stability and the reliability of the tantalum electrolytic capacitor are improved.

The invention discloses a radiation unit positioning clamp for connecting a first radiation arm and a second radiation arm in each dipole. The radiation unit positioning clamp comprises a base; the base is provided with a first inverted fastener and a third inverted fastener for being clamped and fixed on the first radiation arm; the base is also provided with a second inverted fastener and a fourth inverted fastener for being clamped and fixed on the second radiation arm; the base is also provided with a boss; the boss is provided with positioning grooves correspondingly matched with a first clamping part and a second clamping part; and the boss is clamped and fixed on the first radiation arm and the second radiation arm through match between the positioning grooves and the first clamping part and the second clamping part. By adopting the radiation unit positioning clamp provided by the embodiment of the invention, shape and position offset of the radiation arm can be effectively corrected from multiple directions, and reliable fixing and deformation correction roles are played for the radiation unit.

The invention relates to a winding type all-solid-state super capacitor and a preparation method thereof. The winding type all-solid-state super capacitor comprises bottom layer metal foil, a bottom layer metal foil coating, top layer metal foil, a top layer metal foil coating, a winding central spindle, a shell, a conductive silver paste coating, an electrode outgoing line and adhesive tape; the bottom layer metal foil, the bottom layer metal foil coating, the top layer metal foil, the top layer metal foil coating, the winding central spindle and the adhesive tape compose a winding type super capacitor core. The preparation method of the winding type all-solid-state super capacitor comprises the steps: 1, preparing dielectric/electrolyte composite powder; 2, preparing composite powder/organic adhesive paste; 3, preparing the top layer metal foil coating; 4, preparing the bottom layer metal foil coating; 5, aligning the center of the bottom layer metal foil coating and the center of the top layer metal foil coating and leaving a margin at different sides, and preparing the winding type super capacitor core after being winded on the winding central spindle, wrapped and fixed with the adhesive tape; 6 putting the winding type super capacitor core into the shell and then packaging and drying to finish the preparation.

The invention provides an assembling device of a microwave isolator. The assembling device comprises a workbench and pressing mechanisms. The assembling device is characterized in that side plates are arranged on the front and back ends of the workbench, the workbench is supported by the front and back side plates, a central great-circle guide slot is arranged in the central part of the workbench transversely, auxiliary small-circle guide slots are arranged on the left and right sides of the central great-circle guide slot transversely, screwed holes are arranged on the front or back side plate transversely, and the pressing mechanisms penetrate through the transverse screwed holes of the side plate to form a screw transmission pair which can move along the direction of the central great-circle guide slot. The centring, positioning and fastening of a central conductor and a microwave ferrite are realized, and the electric performance parameters of the microwave isolator are increased. Dozens of central conductors and microwave ferrite components can be bound once so that the centring accuracy and positioning accuracy of the microwave isolator are increased significantly, the one-time pass rate is greatly improved, the assembly time is significantly shortened, the cost is reduced, the consistency of the production is greatly improved, and the assembling device is in particular applicable to the mass production of microwave isolators.

The invention provides a P-type polysilicon double-sided solar cell making method. Through front-end production processing on a polysilicon wafer, a surface damage layer and an oxide layer of the polysilicon wafer are removed; a wet chemical method or a dry method is used for thermal oxidation on the surface of the processed polysilicon wafer, and a passivation oxide layer is formed; an Al2O3 layer is deposited on the back surface of the polysilicon wafer to form field passivation effects; the polysilicon wafer is annealed; a plasma enhanced chemical vapor deposition method is adopted to deposit a silicon nitride passivation anti-reflection layer on the surface of the polysilicon wafer; and a metal Ag/Al gate electrode is printed on a laser groove of the silicon nitride passivation anti-reflection layer on the back surface of the polysilicon wafer, an Ag electrode is printed on the front surface of the polysilicon wafer, and good contact is ensured to be formed between the electrode and the silicon wafer. A plurality of silicon nitride stacks with different refractive indexes are adopted to passivate the front surface and the back surface, the passivation effects are enhanced, light reflection on the front and back surfaces is reduced, and the electrical performance parameters of the polysilicon solar cell are greatly improved.

The present invention provides a semiconductor device, a method for manufacturing the same, and an electronic device. The method comprises cleaning a semiconductor wafer in a phosphoric acid tank to remove a silicon nitride hard mask layer; and cleaning the semiconductor wafer in a hot water tank filled with an oxidant to remove phosphoric acid residues on the semiconductor wafer. The manufacturing method can solve the problem that a polycrystalline silicon gate corrodes in a silicon nitride removal process after the polycrystalline silicon etching so as to result in an increase in the sidewall roughness of the polycrystalline silicon gate and a decrease in the characteristic dimension (CD) of the polycrystalline silicon gate, thereby improving the electrical parameters and yield of the products. The semiconductor device and the electronic device have similar advantages.

The invention discloses a four-port suction cup combined antenna. The four-port suction cup combined antenna comprises an antenna cover, a bottom cover, a retaining sleeve, a cable protector, a firstport feeding cable, a second port feeding cable, a third port feeding cable and a fourth port feeding cable. A 3G band circuit board is fixedly installed at the middle portion of the internal portionof the antenna cover, ABS support columns are respectively installed at two sides of the 3G band circuit board, one WlAN frequency circuit board is fixedly installed at the outer side of each supportcolumn, one GPS frequency circuit board is fixedly installed at the upper end of the 3G band circuit board, the GPS frequency circuit boards are fixed on a round plastic board, the two ends of the round plastic board are respectively fixedly matched with the upper end of the corresponding WlAN frequency circuit boards. The four-port suction cup combined antenna is simple in structure and small insize, can provide a good radiation performance index, and can be matched with the connection end in a transceiver device.