Grids and method of manufacture

A manufacturing method and grid technology, applied in semiconductor/solid-state device manufacturing, electrical components, semiconductor devices, etc., can solve problems such as the inability to accurately control the line width at the bottom of the grid, and overcome the limitation of photolithography resolution, electrical properties, etc. The effect of stable parameters and high reliability

Inactive Publication Date: 2008-06-04
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
  • Description
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  • Application Information

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Problems solved by technology

[0009] Therefore, the object of the present invention is to provide a gate and its manufacturing method to solve the problem that the bottom line width of the formed gate cannot be accurately controlled in the existing gate manufacturing method

Method used

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  • Grids and method of manufacture
  • Grids and method of manufacture
  • Grids and method of manufacture

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Experimental program
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Embodiment Construction

[0024] In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0025] Figure 7 It is a flow chart of an embodiment of the method for forming a gate with a groove at the bottom of the present invention.

[0026] Such as Figure 7 As shown, firstly, a semiconductor substrate is provided ( S100 ). The semiconductor base is one of polysilicon, single crystal silicon, amorphous silicon, silicon on insulating layer, silicon germanium composition and gallium arsenide. Doping N-type impurities or P-type impurities into the semiconductor substrate to form a conductive channel of the device. The surface of the semiconductor substrate has a thin oxide layer, the thickness of the oxide layer is 1 to 100 nm, and the formation method of the oxide layer is high temperature thermal oxidation or deposition. T...

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Abstract

The invention relates to a method for manufacturing a grid. The method includes the following steps: a fundus of a semiconductor is provided; a first dielectric layer is generated on the fundus of the semiconductor; at least one second dielectric layer is generated on the first dielectric layer; a groove is generated between the first dielectric layer and the second dielectric layer, and the bottom of the groove exposes the surface of the fundus; the second dielectric layer is removed; an conductive layer is generated both in the groove of the first dielectric layer and on the first dielectric layer; an optical resist layer is reelingly coated on the conductive layer, and a graphic presentation is carried out to generate a grid graph which is arranged above the groove of the first dielectric layer; the conductive layer and the first dielectric layer which are not covered by the grid graph are removed in a corrosion way. The method can control the generated linewidth on the bottom of the grid more accurately.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a gate (notched gate) with a groove at the bottom and a manufacturing method thereof. Background technique [0002] With the development of the semiconductor manufacturing process, the integration of semiconductor devices is getting higher and higher, and the size is getting smaller and smaller, which requires the line width in the semiconductor manufacturing process to be made smaller and smaller. Usually, the size of the gate in a semiconductor device represents the process level of the semiconductor device manufacturing process. Reducing the gate of a semiconductor device first requires improving the resolution of the photolithography process, such as using a short-wavelength light source and advanced mask correction technology. But this requires a lot of economic and time costs. An existing method for reducing the line width of the gate is to form a groov...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/28H01L21/336H01L29/78H01L29/423
Inventor 张海洋陈海华黄怡马擎天
Owner SEMICON MFG INT (SHANGHAI) CORP
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