10 results about "Butterfly network" patented technology

The present invention relates to a circuit including a plurality of routers arranged as a 2D flattened array, each router in the 2D flattened array comprises: a routing network configured to route data between the router and other routers in the 2D flattened array, an input interface configured to receive data from a memory, and an output interface configured to output data to the memory. The 2D flattened array implements a logical butterfly network, and is configurable as a gather circuit, operable to gather high-magnitude tensor data from a dense tensor into a condensed tensor, or a scatter circuit, operable to scatter tensor data from the condensed tensor into a sparse uncondensed tensor based on a given mask.

This disclosure provides a data processing method, apparatus, and computer device based on butterfly networks, relating to the fields of artificial intelligence and hardware acceleration technology. The solution is as follows: In a switchable data processing architecture including an inverse butterfly network, a preprocessing module, a post-processing module, and a control signal generation module, when switching to aggregation operation, the preprocessing module inputs the first input data into the inverse butterfly network, the control signal generation module outputs the first control signal to complete data processing, and the post-processing module directly outputs the aggregation result. When switching to distribution operation, the preprocessing module performs input position mapping and filling on the second input data to obtain the third input data, the control signal generation module outputs the adapted second control signal to complete data processing, and the post-processing module performs rearrangement on the intermediate results to output the distribution result. This reduces hardware resource consumption, lowers control complexity and processing latency, and improves the hardware deployment adaptability of neural network sparse computing while ensuring functional integrity.

This application proposes a method, apparatus, electronic device, and storage medium for arranging vector elements. The method includes: acquiring vector elements to be processed, and determining the levels of each switching node (SN) unit in a butterfly network based on the number of vector elements to generate the butterfly network; wherein the butterfly network is used to arrange the vector elements; determining the input-output mapping relationship between the levels of each switching node (SN) unit in the butterfly network; determining the target state of the SN unit in each level based on the input-output mapping relationship; arranging the vector elements based on the target state, and performing data processing based on the arranged vector elements. Therefore, this scheme enables the arranged vector elements to be transmitted non-blockingly in the butterfly network, thereby enabling the mapping of complex and variable large model workloads onto vector hardware to achieve efficient data processing execution.

The application provides a non-privacy and privacy reasoning scheduling method based on a reconfigurable chip, which comprises the following steps: determining whether the privacy requirement of a neural network reasoning task is privacy reasoning; if yes, performing a first scheduling step; otherwise, performing a second scheduling step; in the first scheduling step, analyzing an arithmetic logic unit required by the privacy reasoning, combining a reconfigurable multiplier and an adder by a data layout converter to form the arithmetic logic unit, and reconfiguring an interconnection network of a processing unit array into a butterfly network or a SIMD data path to obtain a reconfigurable chip and perform a reasoning step; in the second scheduling step, setting a slice as a tensor mode by the data layout converter, independently and parallelly working all the slices, performing a multiply-accumulate operation by each slice, transmitting data between processing units PEs through horizontal and vertical links to form a pulsating data stream, forming a pulsating array by the processing unit array, obtaining the reconfigurable chip, and performing the reasoning step; and in the reasoning step, performing the neural network reasoning task by the reconfigurable chip to obtain a reasoning result.

The invention provides a non-privacy and privacy reasoning scheduling method based on a reconfigurable chip, which comprises the following steps of: judging whether a privacy demand of a neural network reasoning task is privacy reasoning, if so, executing a first scheduling step, otherwise, executing a second scheduling step; a first scheduling step: analyzing an arithmetic logic unit required by privacy reasoning, combining and reconstructing a multiplier and an adder by a data layout converter to form the arithmetic logic unit, reconstructing an interconnection network of a processing unit array into a butterfly network or an SIMD (Single Instruction Multiple Data) data path to obtain a reconstructed chip, and executing a reasoning step; in the second scheduling step, the data layout converter sets the slices into a tensor mode, all the slices independently work in parallel, each slice executes multiplication and addition accumulation operation, data are transmitted between processing units PE through horizontal and vertical links, a pulsation data stream is formed, a pulsation array is formed by a processing unit array, a reconstructed chip is obtained, and the reasoning step is executed; and a reasoning step: executing the neural network reasoning task by the reconstruction chip to obtain a reasoning result.

The invention provides a processor, a vector convergence method, computer equipment and a storage medium, and belongs to the technical field of chips and semiconductors. The processor comprises a butterfly network and a switch control circuit; in any level of sub-network, the plurality of switching nodes in the sub-network are not connected; for the ith-level sub-network and the (i + 1) th-level sub-network, the jth switching node in the ith-level sub-network is respectively connected with the jth switching node and the nth switching node in the (i + 1) th-level sub-network, and the nth switching node in the ith-level sub-network is respectively connected with the nth switching node and the jth switching node in the (i + 1) th-level sub-network, the difference between n and j is 2i-1; and the switch control circuit is respectively connected with each switching node in the butterfly network. According to the processor, the wiring complexity is low, the layout cost is saved, and effective elements in the vector can be quickly converged.

A digital data processor includes a multi-stage butterfly network, which is configured to, in response to a look up table read instruction, receive look up table data from an intermediate register, reorder the look up table data based on control signals comprising look up table configuration register data, and write the reordered look up table data to a destination register specified by the look up table read instruction.

A multilayer butterfly network is shown that is operable to transform and align a plurality of fields from an input to an output data stream. Many transformations are possible with such a network which may include separate control of each multiplexer. This invention supports a limited set of multiplexer control signals, which enables a similarly limited set of data transformations. This limited capability is offset by the reduced complexity of the multiplexor control circuits. This invention used precalculated inputs and simple combinatorial logic to generate control signals for the butterfly network. Controls are independent for each layer and therefore are dependent only on the input and output patterns. Controls for the layers can be calculated in parallel.

The application discloses a control bit generation method and device of an inverse butterfly network adopting a dynamic programming strategy, and solves the problem of poor flexibility of the control bit generation method of the inverse butterfly network in the prior art. The method comprises the following steps: obtaining preset data; determining the inverse butterfly network, the number of stages of the inverse butterfly network and the number of switching units in each stage of the inverse butterfly network according to the preset data; obtaining node extraction position information of a plurality of extraction nodes, a plurality of output nodes and a plurality of exclusive or operation results; traversing the inverse butterfly network, and calculating the switching position information corresponding to the plurality of extraction nodes in each stage; determining the exclusive or operation result corresponding to the extraction node; judging whether the exclusive or operation result is equal to a judgment value, if yes, setting the control bit of the switching unit position corresponding to the exclusive or operation result to 1, and saving the control bit in a control bit storage list; and the flexibility of generating the corresponding control bit algorithm of the inverse butterfly network according to the extraction demand is realized, and the efficiency is improved.

The application provides a vector element arrangement method and device, electronic equipment and a storage medium. The method comprises: obtaining a to-be-processed vector element, and determining the levels of each exchange node SN unit included in a butterfly network based on the number of vector elements, to generate the butterfly network; wherein the butterfly network is used for arranging the vector elements; determining the input-output mapping relationship between the levels of each exchange node SN unit included in the butterfly network; determining the target state of the SN unit in each level based on the input-output mapping relationship; and arranging the vector elements based on the target state, to perform data processing based on the arranged vector elements. Thus, the arranged vector elements can be transmitted in the butterfly network without blocking, so that complex and variable large model workloads can be mapped to vector hardware, to realize efficient execution of data processing.