Address generation for multiple access of memory

Abstract

A memory bank has a plurality of memories. In an embodiment, a forward unit applies logical memory addresses to the memory bank in a forward twofold access order, a backward unit applies logical memory addresses to the memory bank in a backward twofold access order, and a half butterfly network (at least half, and barrel shifters in 8-tuple embodiments) is disposed between the memory bank and the forward unit and the backward unit. A set of control signals is generated which are applied to the half or more butterfly network (and to the barrel shifters where present) so as to access the memory bank with an n-tuple parallelism in a linear order in a first instance, and a quadratic polynomial order in a second instance, where n=2, 4, 8, 16, 32,... This access is for any n-tuple of the logical addresses, and is without memory access conflict. In this manner memory access may be controlled data decoding.

Description

technical field [0001] The teachings herein relate generally to wireless communication systems, methods, apparatus / apparatus, and computer software for such wireless communication systems, and the example embodiments relate to turbo decoder memory access and architectures for such turbo decoders. Background technique [0002] E-UTRAN is a wireless communication system evolved from the Universal Mobile Telecommunications System (UMTS) Terrestrial Radio Access Network system. As currently proposed in 3GPP (3rd Generation Partnership Project) TS 36.212, there will be 188 different turbo frames for turbo codes. Channel codes are applied at the transmitting device to establish protection of the data (user data or control data) against various errors caused by interfering factors in the wireless air interface channel. In turn, the encoded data needs to be decoded at the receiver to recover the original data at the receiver. Turbo codes are commonly used for data protection betwe...

AI Technical Summary

Problems solved by technology

[0005] Higher ASIC clock rates are limited by higher power consumption, limitations in the semiconductor technology used to make the ASIC, and higher end-user prices for devices with high clock rate ASICs

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