16 results about "Back-to-back connection" patented technology

An AC-AC converter is provided. The AC-AC converter includes a primary circuit, a secondary circuit, a transformer, a resonant tank, and a controller. The primary circuit includes four bidirectional switches, each including upper and lower switches connected back-to-back and capable of operating in four quadrants in a voltage-current plane. The first and fourth bidirectional switches operate synchronously, and the second and third bidirectional switches operate synchronously. When the input voltage is greater than a predefined threshold voltage, the first and second lower switches are maintained in an on state, and the first and second upper switches operate with PWM signals and are complementary to each other. When the input voltage is smaller than an additive inverse of the predefined threshold voltage, the first and second upper switches are maintained in the on state, and the first and second lower switches operate with PWM signals and are complementary to each other.

The invention relates to the technical field of power system application, and discloses a unified control method, system, equipment and medium for a flexible interconnection device based on a multi-voltage-level direct-current power distribution network, and the method comprises the steps that the flexible interconnection device is composed of two alternating-current / direct-current converters which are connected back to back, one side adopts direct-current voltage and reactive power control, and the other side adopts direct-current voltage and reactive power control; and the other side adopts active power and reactive power control. Decoupling control is carried out on d-axis current and q-axis current under a synchronous rotating coordinate system, a d-axis current reference value of a PQ side is superposed to a voltage outer ring output of a UdcQ side, and a unified current inner ring reference instruction is generated. According to the method, a feed-forward compensation item is introduced into a current inner loop to offset inter-axis coupling, continuous smooth adjustment of bidirectional power flow can be achieved without switching a control mode, voltage fluctuation of a direct-current bus is effectively restrained, and the dynamic response and global stability of a system are improved.

This application provides a multi-output flyback converter and power supply system, relating to the field of power supply technology. The multi-output flyback converter includes a control module, a transformer, a primary-side switching module, and multiple synchronous rectifier modules. The primary-side switching module is connected to the primary winding of the transformer, and each synchronous rectifier module is connected to each secondary winding of the transformer. Each synchronous rectifier module includes two back-to-back connected switching transistors. The control module is connected to the control terminals of the primary-side switching module, the control terminals of the two switching transistors in each synchronous rectifier module, and the output terminal of each synchronous rectifier module. The control module is used to adjust the duty cycle of the primary-side switching module according to the actual output voltage of the actively regulated output path; and to adjust the duty cycle of the switching transistors in each non-actively regulated output path according to the actual output voltage of each non-actively regulated output path, thereby eliminating cross-regulation between the outputs.

Described herein is a circuitry for use with an inductive sensor. The inductive sensor comprises: a transmitter coil and two back-to-back connected receiver coils for receiving signals induced by a magnetic field generated by the transmitter coil when excited; and a movable conductive target for influencing the magnetic field. In particular, the circuitry is configured for generating a sequence of pulses for discontinuously exciting the transmitter coil.

In an experimental environment including a test system that adds an ASE noise to signal light between a transmitting transponder and a receiving transponder connected in a back-to-back manner, OSNR of the signal light and BER of the signal light received by the receiving transponder are measured while changing a ratio of the signal light to the ASE noise, SNRASE_test of the signal light to which the ASE noise is added is obtained, and total SNRTOT including the test system and the transponders is obtained. SNRTRX indicating an amount of the noise in the transponders is obtained. In a commercial environment in which the test system is provided at upstream of the receiving transponder between the transmitting transponder and the receiving transponder connected via an optical transmission network, the same measurement as in the experimental environment is performed, and GSNR of the optical transmission network is obtained.

Techniques for load current sensing in common-drain power FET switches are described. In an example embodiment, a power field effect transistor (FET) device includes back-to-back power FETs connected to a common drain node. The power FET device also includes a first replica FET coupled to the common drain node and configured to provide a sense current representative of a load current flowing through the power FET device. The power FET device also includes a second replica FET coupled to the common drain node and configured to provide a sense voltage representative of a voltage of the common drain node. A current sense circuit coupled to the first replica FET and the second replica FET may be configured to use the sense voltage from the second replica FET to draw the sense current through the first replica FET.

The application relates to a battery control method and device, a battery management system, a storage medium and a computer program product. In the case that overcurrent occurs in a target battery, first, a switch device on the power receiving side of two back-to-back connected switch devices is turned on, and a switch device on the power supply side is operated in a heating mode. Then, in the case that the overcurrent operation of the target battery meets preset shutdown conditions, the two switch devices are simultaneously turned off. In the above scheme, when overcurrent occurs, instead of directly turning off the switch devices, one of the switch devices is continuously turned on, and the other switch device is controlled to operate in a heating mode. The surge energy is absorbed through heating and dissipated in the packaging structure of the switch device until the preset shutdown conditions are met, the two switch devices are turned off, soft shutdown control of the switch devices is realized, the influence of the induced electromotive force generated by the parasitic inductance on the switch devices is slowed down, and the switch devices are prevented from being broken down.

The invention provides a capacitive coupling chopping instrument amplifier based on improved pseudo resistor bias. The capacitive coupling chopping instrument amplifier comprises main operational amplifiers GM1 and GM2, a ripple suppression module and two groups of closed-loop bias pseudo resistors. The closed-loop bias pseudo resistors adopt complementary CMOS structures (DNW-NMOS and PMOS are connected in a back-to-back manner) and are matched with the unity gain auxiliary operational amplifier to form a dynamic compensation network, the first closed-loop bias pseudo resistor is connected with the positive input end and the negative output end of the GM1, the second closed-loop bias pseudo resistor is connected with the negative input end and the positive output end of the GM1, and the second closed-loop bias pseudo resistor is connected with the negative input end and the positive output end of the GM1. The unity gain auxiliary operational amplifier detects and compensates the voltage difference between the two ends of the pseudo resistor in real time and suppresses direct current offset and offset voltage, and an open-loop bias pseudo resistor is integrated in the ripple suppression module, so that high-frequency ripples can be filtered out, and stable common-mode bias signals can be provided for the GM2. According to the design, the linearity and the high-pass cut-off frequency stability of the amplifier are remarkably improved by optimizing the pseudo resistance bias structure, and the amplifier is suitable for collecting weak low-frequency signals such as bio-electricity signals.

This invention discloses a cascaded synchronous aging topology and control method for half-bridge modules. The topology includes at least one aging basic unit, which consists of two half-bridge modules connected back-to-back. The first half-bridge module operates in BOOST mode, and the second half-bridge module operates in BUCK mode. Each half-bridge module includes a power switch and a bus capacitor. The DC input ports of the first and second half-bridge modules are connected via switching devices. The input of each aging basic unit is connected to a DC source, and the output is connected to a DC feedback load. Adjacent aging basic units are connected via a voltage regulator and an inductor. This invention achieves consistent operating conditions for multi-module cascaded aging by optimizing the topology and precisely controlling the duty cycle and carrier phase. It also adds a fault protection mechanism to prevent fault propagation, reduces the number of contactors used, and lowers control complexity and equipment costs.

This invention provides a back-to-back double-layer Schottky diode and its fabrication method, belonging to the field of semiconductor microwave frequency doubling technology. It includes: a first Schottky diode and a second Schottky diode connected back-to-back; wherein, the first cathode of the first Schottky diode is connected to a first busbar via a first lead, and the second cathode of the second Schottky diode is connected to the first busbar via a first conductive adhesive; the first anode of the first Schottky diode is connected to a second busbar via a second lead, and the second anode of the second Schottky diode is connected to the second busbar via a second conductive adhesive. This invention, by synchronously busing the electrodes of two back-to-back Schottky diodes, essentially forms two single diodes in parallel or symmetrical configuration in the circuit, providing strong support for achieving high power carrying capacity and high output power in frequency multipliers and mixers.

The invention relates to a common-mode voltage elimination method based on a three-phase four-bridge-arm flexible interconnection device, the flexible interconnection device comprises a first converter and a second converter which are connected back to back, the first converter and the second converter are respectively located at a rectification side and an inversion side, and the method comprises the following steps: increasing each duty ratio of the second converter by T at the same time, obtaining various new duty ratios of the second converter; alternately sorting the duty ratios of the first converter and the new second converter from large to small; decomposing each duty ratio after the alternate sorting; the decomposed duty ratios are corrected, and virtual duty ratios on the two sides are obtained; under the constraint that the difference value between the virtual duty ratios on the two sides is kept unchanged, the amplitude of the virtual duty ratios is adjusted, so that the conduction number of the upper bridge arms on the two sides of the flexible interconnection device is matched in real time to eliminate the common-mode voltage. Compared with the prior art, the method has the advantages that the calculated amount is small, and common-mode voltage elimination is rapidly achieved.

The invention discloses a high-power low-heating power distribution device, which comprises two back-to-back NMOS (N-channel Metal Oxide Semiconductor) tubes connected in series between the positive end of an input power supply and the positive end of a load, the source electrodes of the two tubes are connected with each other, the grid electrodes of the two tubes are connected with each other, and the drain electrode of one tube is connected with the positive end of the power supply while the drain electrode of the other tube is connected with the positive end of the load; and the NMOS tubes are connected in series between the negative end of the input power supply and the negative end of the load and adopt a back-to-back structure and are completely symmetrical. According to the layout, a bidirectional symmetrical electronic switch path is formed, and mechanical contacts or additional capacitors are not needed. The double NMOS tubes are connected back to back, so that leakage current can be bidirectionally cut off, a reverse conducting path is thoroughly blocked, static power consumption and heat productivity are fundamentally reduced, and the circuit is particularly suitable for a high-power scene; a mechanical relay is replaced by a pure semiconductor switch, the problems of action life limitation and vibration sensitivity are eliminated, and the reliability is remarkably improved; the symmetrical design enables the on-off synchronism of the positive and negative ends to be extremely high, control errors caused by potential deviation are avoided, the structure is simple, the requirement of passive devices is low, and the cost and fault points are reduced.

A voltage delivery network includes a first unity gain amplifier and a second unity gain amplifier configured in a back-to-back connection topology to receive a first voltage and a second voltage at a first node and a second node, respectively, and jointly output a third voltage at a third node. The network delivery network further includes a first resistor inserted between the third node and the second node; and a first capacitor inserted between the second node and a DC (direct current) node.

The invention discloses an anti-radiation analog switch structure with overvoltage transmission capability, which belongs to the field of integrated circuits and comprises NMOS (N-channel Metal Oxide Semiconductor) transistors mn1 to mn3, PMOS (P-channel Metal Oxide Semiconductor) transistors mp1 to mp2, switches K1 to K3, diodes D1 and D2 and phase inverters INV1-INV3, through processing in an mn2 and mn3 source body short circuit mode, holes stored in the HVPwell can be timely extracted by a body electrode through ohmic contact under any condition, and the problem that the holes and electrons cannot be completely extracted due to built-in potential in source body separation bias is avoided; the mn2 and the mn3 are connected in a back-to-back manner, so that positive and negative pressure transmission work can be completed. According to the invention, a better electric leakage level can be obtained after a total dose irradiation test. Therefore, the original overvoltage blocking capability is maintained, and the low leakage level of the whole circuit after irradiation is ensured at the same time.

A multi-output switching power supply and a control method thereof are provided. The multi-output switching power supply comprises: a power conversion module performing power conversion on an input signal according to a drive signal to obtain a first output signal; a power distribution module converting the first output signal into plurality of output signals according to a plurality of distribution signals; a control circuit generating the drive signal based on feedback of the output signal from the first power distribution unit, and generating a plurality of distribution signals based on feedback of output signals from other power distribution units. Each power distribution unit comprises a first transistor and a second transistor connected back-to-back, with each distribution signal controlling switching states of corresponding first transistor and second transistor. The present disclosure can improve work efficiency of the multi-output switching power supply, reduce heat generation during operation, and lower system costs.

An energy storage apparatus includes a cell, a relay which cuts off a current of the cell, a bypass circuit connected in parallel with the relay, and a management device. The bypass circuit includes two back-to-back connected FETs. When an abnormality of the cell is detected by the management device, the management device opens the relay, closes one FET of the two FETs, and opens the other FET, and permits a discharge or a charge of the cell through a path passing through a parasitic diode of the FET. When the discharge or the charge is being performed through the path passing through the parasitic diode, if a current I and an energization time T of the FET(s) reach a predetermined condition or the temperature of the FET(s) reaches a predetermined condition, the management device 150 closes the relay 53 and the other FET(s) that is open.