12 results about "Open-circuit test" patented technology

The invention provides a biphase composite magnetic material magnetically controlled reactor electromagnetic transient simulation method, device and equipment and a medium, and relates to the technical field of power equipment magnetic material testing and electromagnetic transient simulation. According to the invention, the test winding is arranged on the excitation winding of the magnetically controlled reactor, and multi-dimensional means of obtaining total iron loss through an open circuit test, obtaining magnetic hysteresis loss through a frequency reduction test, obtaining copper loss and leakage reactance through a short circuit test and the like are combined, so that separation of magnetic hysteresis loss, eddy current loss and additional loss can be realized; a high-fidelity hysteresis loop and a magnetic conductivity change rule are obtained, and the nonlinear characteristic and hysteresis response of the magnetic core can be accurately captured, so that the predictive capability of equipment performance and the sensing capability of an operation state are improved.

The utility model relates to the field of ignition coil production, in particular to an ignition coil open circuit test device which comprises a bottom plate. The upper end of the bottom plate is provided with a test module, the upper end of the test module is provided with mounting support plates in bilateral symmetry, the upper sides of the front ends of the mounting support plates are provided with mounting grooves, the mounting grooves are internally provided with the sliding frame, and the right end of the sliding frame is provided with a first motor; a first lead screw is rotationally connected into the sliding frame. The first motor drives the first lead screw to rotate, the sliding frame is used for limiting rotation of the movable base and driving the movable base and a connecting part to move, the electric push rod drives the connecting base and the fountain pen to move to complete marking of the ignition coil, the second motor drives the second lead screw to rotate, and rotation of the main sliding base is limited through the main movable frame. And the main sliding seat and the clamping module are driven to move to realize automatic plugging of the connecting line, so that marking and plugging operations are synchronously completed.

The invention relates to the technical field of sensing product testing, in particular to a super-large array packaging conductivity testing device which comprises a wafer testing table, an open circuit testing plate and a short circuit testing plate, an objective table is installed at the top of the wafer testing table, and a swing arm positioning seat is installed at the top of the wafer testing table and on the back face of the objective table. The outer wall of the swing arm positioning seat is provided with a test probe, the top of the wafer test bench and the back surface of the swing arm positioning seat are provided with a main control unit, and the outer wall of the main control unit is connected with the swing arm positioning seat through a test line. According to the super-large array packaging conductivity testing device, the open circuit testing plate and the short circuit testing plate in the device are used for testing the to-be-tested product, and the problems that an existing testing device and an existing testing method cannot directly point-contact the two ends for measurement, the accuracy of a testing result is poor, the efficiency is low, and the product is prone to being damaged are solved.

1. The name of the design product: pin interrupt simulator. 2. The use of the design product: for simulating and testing the open circuit test and micro-interrupt test in the electrical performance of automotive electronic components, which is a test equipment specially meeting the standards of vehicle manufacturers. 3. The design points of the design product: in shape. 4. The picture or photo that best indicates the design points: front view. 5. The bottom surface of the design product is the part that is not easy to see or cannot be seen during use, so the top view is omitted.

The invention relates to a configurable segmented wiring structure of an FPGA (Field Programmable Gate Array) and a test method of the configurable segmented wiring structure. According to the wiring structure, a grouping twisted connection mode is adopted, segmented wiring is divided into a plurality of wiring groups, wiring in the groups is crossed through different metal layers to achieve cyclic alternation of various lengths, connection is controlled through a configurable switch, wiring configuration of any length from 1 to n can be achieved, and modular cascade expansion of a CLB array is supported. According to the testing method based on the structure, an open-circuit test and a short-circuit exhaustion test for all physical adjacent wiring are respectively carried out in a mode of applying an excitation signal after pre-charging and floating and reading back a response, the testing time can be shortened to about 51% of that of a traditional full exhaustion test while the 100% wiring function test coverage rate is guaranteed, and the testing efficiency is improved. And the test efficiency is obviously improved. According to the invention, the flexibility, the scale expansibility and the test economy of FPGA wiring are effectively improved.

The invention relates to the field of electronic circuit production testing, and provides a multi-node circuit short circuit testing method. The method is used for detecting whether an abnormal short circuit exists between any two nodes in a multi-node circuit to be detected. Comprising the following steps: in a multi-node circuit, acquiring untested nodes as current to-be-tested nodes, and short-circuiting all untested nodes behind the current to-be-tested nodes to form short-circuit combined nodes; measuring the impedance between the current node to be measured and the short-circuit combined node; if the connection condition corresponding to the current node to be tested and the short-circuit combined node is determined to be an open circuit according to the impedance, testing the next node which is not tested; and if the connection condition corresponding to the current to-be-tested node and the short-circuit combined node is determined to be short circuit according to the impedance, independently performing impedance retest on each node in the current to-be-tested node and the short-circuit combined node, positioning an abnormal node which is short-circuited with the current to-be-tested node, and completing the test on each node which is not subjected to the test.

The utility model discloses a radio frequency line loss calibration system which comprises a comprehensive tester, a calibration clamp, a broadband matrix radio frequency switch and an upper computer, the calibration clamp is provided with a plurality of test cavities, and the test cavities comprise at least one of a short circuit test cavity and an open circuit test cavity. The broadband matrix radio frequency switch is provided with a plurality of input ports, a plurality of output ports and a plurality of radio frequency switch paths, the number of the output ports of the broadband matrix radio frequency switch is larger than that of the input ports, and each input port of the broadband matrix radio frequency switch is connected with a corresponding output port of the comprehensive tester. The input end of each radio frequency switch path is connected with the corresponding input port, the output ends of the multiple radio frequency switch paths are connected with multiple output ports of the broadband matrix radio frequency switch, and the output ports of the broadband matrix radio frequency switch are inserted into the multiple test cavities through wires. And the upper computer is respectively connected with the comprehensive tester and the broadband matrix radio frequency switch. The multi-port radio frequency line loss calibration device can meet the multi-port radio frequency line loss calibration requirement.

This utility model discloses a device for open-circuit testing of surge protectors, relating to the field of surge protector testing technology. It includes a base plate with support seats fixedly installed at each of the four corners of its lower surface, and a control device fixedly installed at one end of its upper surface. This utility model, through the setting of a limiting mechanism, can improve testing stability and reduce human error. Standardized clamping force is achieved through the combination of mechanical compression and elastic clamping. Combined with an L-shaped clamping plate to limit the horizontal displacement and vertical sway of the surge protector, it avoids product displacement caused by uneven force in traditional manual fixing, ensuring stable conduction of the test circuit and accurate results. Furthermore, the limiting mechanism simplifies the operation process and improves testing efficiency. No additional manual clamping steps are required; the operator can trigger clamping by pushing the sliding seat, and the clamping plate can be reset by pushing it back after testing. This significantly shortens the preparation and waiting time for testing a single device, adapting to the needs of large-scale continuous testing.

1. The name of the design product: open circuit test table. 2. The use of the design product: for detecting open circuit and open state of circuit or device in the field of electronics and electrical. 3. The design points of the design product: in shape. 4. The picture or photo that best shows the design points: perspective view.

The invention relates to the technical field of equipment testing, and particularly discloses a channel open-circuit testing circuit, system and method. The channel open circuit test circuit comprises an MOS driving module, an open circuit detection module and a fault diagnosis module. The MOS driving module comprises a plurality of output ports and feedback ports, wherein the number of the feedback ports is smaller than that of output channels. The MOS driving module and a corresponding external load form an output channel through each output port, the output end of the open circuit detection module is connected with the output channel, and each feedback port of the MOS driving module is connected with the fault diagnosis module; the open circuit detection module generates an open circuit detection signal and transmits the open circuit detection signal to the MOS driving module through a to-be-detected output channel; the MOS driving module generates a diagnosis feedback signal according to the open circuit detection signal and transmits the diagnosis feedback signal to the fault diagnosis module through a corresponding feedback port; the fault diagnosis module judges whether the output channel to be detected is in an open circuit state according to the level state of the diagnosis feedback signal, and independent detection of the output channel is achieved.

A configurable resistor can be provided to allow multiple tests of a through-silicon via (TSV) testing for respective connection issues to be performed. The tests can include an open test, which checks for discontinuities or breaks (open defects) in the electrical path of the TSV; a VDDQ short test, which identifies short circuits between the TSV and the VDDQ power rails; and a VSS short test, which identifies short circuits between the TSV and the VSS ground rails.

The invention relates to an FFC cable time domain reflection impedance de-embedding measurement method and device, equipment and a medium. The method comprises the steps of obtaining a reflection voltage signal of a target cable in a tail end open circuit state, and obtaining a full-path time domain reflection waveform sequence according to the reflection voltage signal; determining a total reflection feature point based on tail end waveform data of the full-path time domain reflection waveform sequence, taking the total reflection feature point as a signal segment starting point, generating an extension signal segment converged to preset matching impedance, and splicing the extension signal segment with the full-path time domain reflection waveform sequence to obtain an extension reflection waveform sequence; according to the method, the problems of divergence and unstable physical contact of a traditional de-embedding algorithm under an open circuit test can be solved by constructing a virtual matching signal segment and segmented variable bandwidth filtering; the invention relates to high-precision measurement of characteristic impedance of an FFC cable without physical load termination.