BIST-based open-circuit test method for TSVs in 3D SRAM

Abstract

The invention discloses a BIST-based open-circuit test method for TSVs in a 3D SRAM. The method comprises the steps that March elements of all TSV open-circuit faults are determined, test vectors containing the March elements corresponding to all the TSV open-circuit faults are generated; traversal read-write operation is conducted on all storage units of the 3D SRAM based on the test vectors through a BIST circuit; in the execution process of the March element corresponding to a certain TSV open-circuit fault, if the read result of a certain test address X is different from expected test data in the March element, it is judged that the TSV connected with the test address X has a fault, the TSV is marked with an error, and the type of the fault corresponding to the March element executed currently and the address of the fault of the TSV are recorded; after traversal read-write operation on all the storage units is completed, all TSV fault information is output. By means of the method, the purpose of detecting the TSV open-circuit faults can be achieved without using a special TSV test circuit and increasing extra area expenses; the method has the advantages that the complexity of circuit design is low, and test efficiency is high.

Description

technical field [0001] The invention relates to the field of IC testing, in particular to a BIST-based TSV open circuit testing method in 3DSRAM. Background technique [0002] 3DSRAM based on 3D-IC technology is more conducive to high-performance design than graphic design. It has always been a key research and development project of microprocessor manufacturers led by Intel and IBM, many famous universities, scientific research institutions and research centers at home and abroad. [0003] For ultra-large-capacity memory, a large number of through-silicon vias (Through Silicon Via, TSV for short) will be used in the circuit, and its density will reach tens of thousands per square millimeter. The data shows that 1Gb 3DSRAM has about 1.5 million TSVs. Since the manufacturing process of TSVs is not yet mature, TSVs are prone to open circuit failures. Related studies have shown that a scale of 10 4 The probability of TSV failure in a TSV chip is 63.214%, which seriously affec...

AI Technical Summary

Problems solved by technology

[0009] To sum up, the existing 3DSRAM self-test method can not detect the failure of the memory bank and the failure of the interconnection medium TSV at the same time. If it is necessary to detect the failure of the TSV at the same time, it is necessary to add a special test circuit for TSV, which undoubtedly increases additional Area overhead while increasing circuit design complexity

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