Network-on-Chip Architecture Based on Butterfly Network Coding and Its Shortest Path Acquisition Method

Abstract

The invention relates to the technical field of intra-chip communication, in particular to an on-chip network architecture based on butterfly network coding and a method for obtaining the shortest path. Each node of the network architecture is distributed in a honeycomb shape, and each honeycomb is an equilateral triangle formed by connecting lines of three adjacent nodes. The Z-X-Y shortest path routing based on the butterfly network coding based on-chip network architecture and the cellular topology can find the shortest routing path under the condition of avoiding deadlock; compared with the traditional topology, such as mesh topology, the cellular topology in the architecture provided by the present invention has natural shortcuts, which can shorten the number of hops of key links; at the same time, the architecture provided by the present invention will use butterfly network coding, which can greatly eliminate network hot spots and solve network congestion Problem: The cellular architecture provided by the present invention transmits data packets by wireless, transmits control signals by wire, and separates data from control signals, so that high-speed and high-efficiency data transmission can be accomplished.

Description

technical field [0001] The invention relates to the technical field of intra-chip communication, in particular to an on-chip network architecture based on butterfly network coding and a shortest path acquisition method thereof. Background technique [0002] The key to the development of on-chip multi-core processors (CMP) is the communication architecture scheme between multiple cores. Under the traditional bus structure, on-chip communication technology has encountered a development bottleneck, and even if the characteristics of the transmission line are continuously improved, it is difficult to meet the inter-core communication requirements. In recent years, in order to improve the performance of on-chip communication, the scheme of replacing traditional bus technology with network-on-chip (NoC) has been proposed. Although the scalability of the traditional on-chip network interconnection structure based on metal dielectrics meets the requirements, it cannot meet the need...

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Problems solved by technology

Although the scalability of the traditional on-chip network interconnection structure based on metal dielectrics meets the requirements, it cannot meet the needs of future on-chip communication in terms of power consumption and interconnection speed; in order to solve the bottleneck problem of metal transmission lines, the wireless on-chip The characteristics of high transmission rate and low power consumption have gradually begun to be studied. ChengLi et al. proposed a photon-on-chip network architecture using nanophotonic communication--LumiNOC; M.-C.F.Chang et al. proposed using guided wave transmission for on-chip Network communication scheme; S.Watanabe et al. proposed UWB (UltraWideband) for on-chip communication scheme; the proposed wireless on-chip network Small-Word (Small-Word) architecture uses wireless transmission to create shortcuts to reduce key path delays , but as the size of the internal subnet increases, it will still lead to the emergence of high-latency paths

Moreover, if the inner network is too large, the problems of high delay and transmission rate reduction caused by wired transmission in the subnet are still difficult to solve

At the same time, the long distance of the wireless transmission interface and the inconsistency of the transmission distance of the wireless interface will lead to design difficulties

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