38 results about "Network on chip architecture" patented technology

There are provided a method of creating an optimized core-tile-switch mapping architecture in an on-chip bus and a computer-readable recording medium for recording the method. The core-tile-switch mapping architecture creating method includes: creating a core communication graph representing the connection relationship between arbitrary cores; creating a Network-on-chip (NOC) architecture including a plurality of switches, a plurality of tiles, and a plurality of links interconnecting the plurality of switches; and mapping the cores to the tiles using a predetermined optimized mapping method to thereby create the optimized core-tile-switch mapping architecture. The optimized mapping method includes first, second, and third calculating steps. According to the optimized core-tile-switch mapping architecture creating method and the computer-readable recording medium for recording the method, since the hop distance between cores is minimized, it is possible to minimize energy consumption and communication delay time in an on-chip bus. Furthermore, the optimized mapping architecture presents a standard for comparing the optimization of other mapping architectures.

A method of interconnecting blocks of heterogeneous dimensions using a NoC interconnect with sparse mesh topology includes determining a size of a mesh reference grid based on dimensions of the chip, dimensions of the blocks of heterogeneous dimensions, relative placement of the blocks and a number of host ports required for each of the blocks of heterogeneous dimensions, overlaying the blocks of heterogeneous dimensions on the mesh reference grid based on based on a guidance floor plan for placement of the blocks of heterogeneous dimensions, removing ones of a plurality of nodes and corresponding ones of links to the ones of the plurality of nodes which are blocked by the overlaid blocks of heterogeneous dimensions, based on porosity information of the blocks of heterogeneous dimensions, and mapping inter-block communication of the network-on-chip architecture over remaining ones of the nodes and corresponding remaining ones of the links.

The invention provides a three-dimensional network on chip (NoC) structuring method by using a horizontal-plane network structure and a flexible imaginary-plane network structure, wherein, the horizontal-plane network of which the network topology adopts a De Bruijn picture is a plane extending along the X direction and the Y direction; while the imaginary-plane network is a curved surface extending along the three directions of X, Y and Z, the network can be formed by connecting certain nodes of each layer of the horizontal-plane network according to the requirement for solving certain problems such as reducing the wiring complexity or improving the fault-tolerant character, namely, the nodes are not necessarily in a vertical plane. The invention also provides two kinds of imaginary-plane structuring methods comprising a De Bruijn picture structure and a double-ring structure. The first method fully utilizing that the De Bruijn picture allows shorter routing algorithm reduces average hop times in the data transmission, provides a small network delay and has a better fault-tolerant character; the second method improves the transmission efficiency by using the characteristics of low wiring complexity of a ring structure and high data transmission speed and by combining the horizontal-plane network utilizing the advantage of small network diameter of the De Bruijn picture.

Embodiments disclosed herein generally relate to the use of Network-on-Chip architecture for solid state memory structures, both volatile and non-volatile, which provide for the access of memory storage blocks via a router. As such, data may be sent to and/or from the memory storage blocks as data packets on the chip. The Network-on-Chip architecture may further be utilized to interconnect unlimited numbers of memory cell matrices, spread on a die, thus allowing for reduced latencies among matrices, selective power control, unlimited memory density growth without major latency penalties, and reduced parasitic capacitance and resistance. Other benefits may include improved signal integrity, larger die areas available to implement memory arrays, and higher frequency of operation.

Systems and methods for performing multi-message transaction based performance simulations of SoC IP cores within a Network on Chip (NoC) interconnect architecture by accurately imitating full SoC behavior are described. The example implementations involve simulations to evaluate and detect NoC behavior based on execution of multiple transactions at different rates/times/intervals, wherein each transaction can contain one or more messages, with each message being associated with a source agent and a destination agent. Each message can also be associated with multiple parameters such as rate, size, value, latency, among other like parameters that can be configured to indicate the execution of the transaction by a simulator to simulate a real-time scenario for generating performance reports for the NoC interconnect.

A method for dynamical adjusting channel direction and Network-on-Chip architecture thereof are provided. The Network-on-Chip architecture of dynamical adjusting channel direction comprises a first channel, a first router and a second router. The first channel has a first transmission direction. The first router generates and outputs a first output request when receiving a first data. The second router is coupled to the first router through the first channel. The second router receives the first data through the first channel when receiving the first output request.

The invention relates to a wavelength-allocation-based three-dimensional optical on-chip network router communication system and method. The communication system employs a photoelectric mixing type 3D mesh network topological structure and a novel seven-port clog-free optical router capable of realizing multi-wavelength communication; and when the system is applied to a three-dimensional optical on-chip network, no wavelength conversion is needed. Because of utilization of the optical router, the consumed number of optical devices like micro ring resonators and waveguides and the like is reduced. Besides, according to the communication method, when a node of each layer sends out an optical signal, the employed wavelengths are identical; and optical signals with all wavelengths can be received at all layers, so that problems of severe network congestion, low link utilization rate, and limited expansibility due to utilization of single wavelength communication by the existing optical on-chip network architecture can be solved. Therefore, with the system and method, the network congestion probability can be reduced; the communication delay can be reduced; and the throughput capacity and network saturation point can be improved.

The invention discloses a multi-cluster network-on-chip architecture based on a statistic time division multiplexing technology. In the architecture, a bus structure based on the statistic time division multiplexing technology is adopted in clusters; master equipment, slave equipment, a bus component and a statistic time division multiplexing control unit are arranged on a bus; the statistic timedivision multiplexing control unit is connected with the master equipment, the slave equipment and the bus component, wherein the slave equipment comprises a memory and a network interface with a waiting mechanism; the bus component comprises an arbitrator, a decoder and a multipath selector; the statistic time division multiplexing control unit unifiedly controls the master equipment and the slave equipment on the bus to realize the statistic time division multiplexing mechanism; and the network interface with the waiting mechanism receives a data transmission request initiated by the masterequipment on the bus and triggers the transmission under the condition of satisfying the triggering conditions. The multi-cluster network-on-chip architecture disclosed by the invention can effectively reduce the network load and the communication relay and further improves the whole performance of a network-on-chip system, thereby having favorable application value and wide application prospect.

The invention discloses a method for optimizing the on-chip network structure by adding a bypass in a processor. In the invention, the bypass is added in the processor and the auxiliary module is added to support the lower delayed on-chip network structure. In the invention, the processor can be used for not only transmitting the treated result, but also transmitting the intermediate result temporarily stored in the treatment process, for the other node processor, the more data can be obtained, the treating function of the network on the whole chip can be extended. For the thread with the higher data dependence, a large number of data treatment and transmission can be performed between the threads, the execution efficiency is higher. The invention can improve the processor to better support the on-chip network structure and performing the on-chip network advantages.

The invention discloses a CDMA (code division multiple access) on-chip network architecture based on a standard orthonormal basis and a realization method of the CDMA on-chip network architecture. The CDMA on-chip network architecture and the method mainly solve the problem that in the prior art, the on-chip network architecture cannot reduce the resource waste or reduce the power consumption while ensuring the transmission quality and the transmission efficiency. The CDMA on-chip network architecture based on the standard orthonormal basis comprises a network transmitting module, an arbitration module and more than two processing units, wherein the network transmitting module and the arbitration module are integrated, and the processing units are connected with the network transmitting module and the arbitration module respectively through network nodes. Through the scheme, the CDMA on-chip network architecture and the method have the advantages that the goals that the transmission quality and the transmission efficiency are high, in addition, the resource waste and the power consumption are low are reached, and high practical value and popularization value are realized.

The invention provides a convolutional neural network acceleration processing system and method based on an FPGA, and a terminal. The problems that in the prior art, the inherent computing characteristics of a convolutional neural network are mismatched with a network-on-chip architecture, the hardware acceleration efficiency is low, the parallelism difference of a network layer in different dimensions is large, and the memory access characteristics of different network layers are different are solved. The acceleration efficiency, the data throughput rate and the calculation energy efficiencyof the convolutional neural network on the FPGA are improved through an assembly line architecture, a customized multistage memory access strategy and convolutional parallel optimization.

The invention provides a fault-based three-dimensional optical on-chip network architecture, a communication method and an optical router, which solve the technical problems of serious blockage in vertical direction, uneven TSV distribution, and big insert loss of a high order optical router in the prior art. The network architecture has seven layers totally, wherein the top layer is an optical network layer and integrated with NXN novel nine-port optical routers; the bottom layer is a pure electric layer and integrated with NXN five-port electric routers; every layer of the middle five layers is integrated with NXNX4 IP cores; the uppermost layer in the middle layers is a reference, and another four layers are staggered along four diagonal line directions respectively to form a fault mechanism; the optical router provides a high-order optical interconnection of the middle layers; the IP internuclear communication includes a node internal part, internal node of layer and interlayer communication; the communication between the inner part of the node and the inside of the layer is carried out through a middle layer optical network; the interlayer communication is realized through a top layer optical network or a bottom layer electric router. The invention solves the problem of serious blockage of vertical direction in a traditional 3D optical on-chip network; the communication between processor cores is high-efficient.

The invention relates to the technical field of on-chip communication, in particular to a network-on-chip architecture based on butterfly network coding and a shortest path acquiring method of the network-on-chip architecture. The nodes of the network-on-chip architecture are distributed in a honeycomb manner, and each honeycomb is an equilateral triangle formed by the connecting lines of three adjacent nodes. The network-on-chip architecture has the advantages that the network-on-chip architecture based on butterfly network coding and Z-X-Y shortest-path routing matched with honeycomb topology can avoid deadlock and find out the shortest routing path; compared with traditional topological structures such as mesh topology, the honeycomb topology of the network-on-chip architecture has natural shortcuts and can reduce key link hop count; meanwhile, the network-on-chip architecture uses the butterfly network coding, can greatly eliminate network hot spots and can solve the problem of network congestion; the honeycomb network-on-chip architecture transmits data packets in a wireless manner and transmits control signals in a wired manner, data and the control signals are separated, and high-speed and efficient data transmission can be completed.

The invention proposes a multi-cast broadcast communication perception optical on-chip network architecture and a communication method, and is used for solving technical problems in the prior art thatan optical on-chip network architecture is higher in power consumption and is poorer in extendibility and the technical problems that a communication method is bigger in time delay and power consumption. In the optical on-chip network architecture, a processor module is divided into clusters which are arranged in an array, and each cluster comprises an array which is formed by 2*4 processor modules. Each processor module is coupled to one first active micro-ring resonator through a coupling port. The clusters in the array are connected through a snake-shaped optical waveguide structure, and are in unit extension. Meanwhile, the coupling distance distribution between the first active micro-ring resonator and the optical waveguide is set by a power separation system. In the communication method, a global control unit performs the processing of the communication request of the processor modules, and transmits the obtained control information to a multi-wavelength laser light source to perform the network communication configuration with the first active micro-ring resonator.

A system and method embodying some aspects for communicating between nodes in a network-on-chip are provided. The system comprises a microprocessing chip and a plurality of connection paths. The microprocessing chip comprises sixteen processing nodes disposed on the chip. The plurality of connection paths are configured such that each is at most three hops away front any other node. Each node also has connection paths to at most three other nodes.