11 results about "Network on chip architecture" patented technology

The invention discloses a network architecture based on multi-core transmission, and relates to the field of integrated circuits. The network-on-chip module comprises at least one node ring consisting of M pipeline cascade routing nodes; adjacent routing nodes in adjacent node rings are cascaded according to a longitudinal depth pipeline to form a node matrix; n sending buffers and N receiving buffers are respectively arranged on the node ring on the outermost layer of the node matrix, and each sending buffer and each receiving buffer are respectively connected with the corresponding IP core through directly connected routing nodes; a routing algorithm based on a node matrix is built in the network configuration unit, a target IP core is determined according to data sent into the sending buffer by source IP core data, a node matrix is controlled to plan and generate a data transmission path, and data transmission is executed. The data buffer is added in the network-on-chip architecture, so that the data transmission path is shortened, the feedback is more timely, and the network bandwidth is larger; a routing node adds a data replication realization function to realize multicast and broadcast modes; and the interface complexity of the whole node matrix is reduced.

The invention relates to a network-on-chip architecture (100) characterized by: a plurality of replicable partitions (200), each partition (200) comprising one or more routers (10) suitable for communication, a register, and a pre-built communication link established in a base direction or other direction, and one or more configuration bus nodes (20) arranged in each partition (200) connected to the register (40); a system integrator connecting the system operator (60) to one of the configuration bus nodes (20); wherein the system operator (60) initializes a path map between the configuration bus nodes (20) to form a secondary configuration network, and accesses the registers (40) in each partition to program the registers (40) with routing data. A method of processing data on a network-on-chip architecture (100) is also disclosed herein.

This invention discloses a method for optimizing the topology of a 3D on-chip network (SoC) for high-speed data acquisition systems. Addressing the problem that general-purpose 3D SoC architectures are difficult to adapt to the communication characteristics of high-speed data acquisition systems, leading to high transmission latency and redundant link resources, this method models the network topology adjustment process as a Markov decision process and employs deep reinforcement learning to achieve adaptive optimization of the topology. The method uses a general-purpose 3D SoC as the initial architecture, constructing a state representation that includes node connection features, average network latency, longest path latency, and link area; defining a pruning and regrowth action space; designing a reward function that integrates changes in average latency, longest path latency, and link area; and using a deep Q-learning network with a multilayer perceptron structure for policy training. To improve learning efficiency, an action candidate set is constructed and combined with a two-layer greedy policy to achieve fast and effective search. Through iterative learning and topology updates, a 3D SoC topology that better suits the communication load of high-speed data acquisition systems can be obtained, reducing average transmission latency and link area overhead while ensuring connectivity.

The invention discloses a data transmission method, system and device and a computer readable storage medium, relates to the technical field of network-on-chip, and is applied to a routing node of the network-on-chip to determine a source node for transmitting target data and a destination node for receiving the target data. Determining a node routing direction according to the position relationship between the source node and the destination node; according to the position relation between the routing node and the destination node, screening a next node according to the node routing direction; transmitting target data to the next node through a conventional channel of the routing node in response to the fact that the coordinate of the next node and the coordinate of the routing node have the same value; and in response to the fact that the coordinate of the next node and the coordinate of the routing node do not have the same value, transmitting the target data to the next node through the virtual channel of the routing node. On the premise of not changing a network-on-chip architecture system, transmission congestion is reduced by modifying a routing algorithm on a software level, and the data transmission efficiency of the network-on-chip is improved.

The present invention relates to a network-on-chip architecture (100), characterized by: a plurality of stampable partition (200), each partition including one or more router (10) adapted for communication, registers and pre-built communication links established in cardinal directions or other directions, and one or more configuration bus node (20) deposited in each partition (200) connecting to the registers (40); a system integrator connecting a system operator (60) to one of the configuration bus node (20); wherein the system operator (60) initializes a path mapping between the configuration bus node (20) forming a secondary configuration network and access the registers (40) in each partition to program the registers (40) with routing data A method of processing data at the network-on-chip architecture (100) is also disclosed herein.

One technical solution of the present invention is to provide a layout method for a scalable multi-die network-on-chip (NOC) FPGA architecture. Another technical solution of the present invention is to provide an application of the aforementioned layout method for a scalable multi-die NOC FPGA architecture. The present invention discloses a scalable multi-die NOC-based FPGA architecture and a corresponding hierarchical recursive layout algorithm designed to directly map register transfer-level dataflow designs generated by existing high-level synthesis onto the proposed interconnect architecture. The disclosed method can unlock the potential of hierarchical topologies and more effectively utilize dedicated interconnect resources, such as cross-die wire meshes, NOCs, and high-speed transceivers.

The disclosure provides a kind of many-core cache consistency system, method, electronic equipment, storage medium and product, system is based on network-on-chip architecture, by introducing multiple nodes, corresponding router and the distributed directory deployed in router.Each node contains one or more processor cores and distributed last level cache, memory address is divided into multiple address blocks and is associated with distributed last level cache by dynamic address mapping rule. Distributed directory is used to record the state of cache line with distributed last level cache one by one, and the router is responsible for receiving and responding to requests from local or remote nodes, querying the distributed directory and updating the cache line state, which realizes efficient management of cache consistency.The technical scheme belongs to the field of communication technology, effectively solves the problem of high load and communication delay of master node in traditional cache consistency protocol, and improves the data consistency and access efficiency in multi-processor system and large-scale parallel computing environment.

The present application discloses a network architecture based on multi-core transmission, which relates to the field of integrated circuits. The on-chip network module includes at least one node ring composed of M pipeline cascade routing nodes; adjacent routing nodes in adjacent node rings are pipelined in a vertical depth cascade to form a node matrix; N sending buffers and receiving buffers are respectively provided on the outermost node ring of the node matrix, and each sending buffer and receiving buffer is connected to the corresponding IP core through a directly connected routing node; the network configuration unit has a built-in routing algorithm based on the node matrix, which determines the target IP core according to the data sent to the sending buffer by the source IP core data, controls the node matrix to plan and generate the data transmission path and execute the data transmission. The addition of data buffers in the on-chip network architecture shortens the data transmission path, makes feedback more timely, and increases the network bandwidth; the routing node adds data replication to realize the multicast and broadcast modes; the overall node matrix reduces the interface complexity.

Embodiments herein describe using a virtual destination to route packets through a NoC (105). In one embodiment, instead of decoding an address as a target destination ID for the NoC (105), an ingress logic block (115) assigns the same virtual destination ID to packets for multiple different targets. For example, the targets may be located in the same segment or location of the NoC (105). Thus, the ingress logic block (115) does not have to store an entry for each target in a lookup table, but it may have a single entry for the virtual destination ID. The virtual destination ID is then used to route the packets for the targets to a decoder switch (140) in the NoC (105). The decoder switch (140) may then select an appropriate target destination ID using the address in the packet, which is different from the destination ID.

The invention provides a priori knowledge-based heterogeneous in-memory computing network-on-chip architecture optimization method, which comprises the following steps of: constructing a joint simulation platform of a heterogeneous in-memory computing network-on-chip, and performing computing and communication delay joint pipeline simulation on the heterogeneous in-memory computing network-on-chip by adopting the joint simulation platform; a three-stage search strategy based on priori knowledge is adopted, search is conducted in a heterogeneous architecture space of the computing network-on-chip in the heterogeneous memory, a preset lookup table and a preset simulated annealing algorithm are adopted to optimize the search process, and target architecture configuration of the computing network-on-chip in the heterogeneous memory is determined; and according to the target architecture configuration of the heterogeneous in-memory computing network-on-chip, optimizing the core layout of the heterogeneous in-memory computing network-on-chip by adopting a force-oriented algorithm, and determining the architecture of the optimized heterogeneous in-memory computing network-on-chip. According to the method, the search efficiency of computing hardware configuration of the network-on-chip architecture in the heterogeneous memory and the optimization degree of computing delay time, power consumption and area are effectively improved.

Embodiments herein describe using virtual destinations to route packets through a NoC (105). In one embodiment, instead of decoding an address into a target destination ID of the NoC (105), an ingress logic block (115) assigns packets for multiple different targets the same virtual destination ID. For example, these targets may be in the same segment or location of the NoC (105). Thus, instead of the ingress logic block (115) having to store entries in a lookup-table for each target, it can have a single entry for the virtual destination ID. The packets for the targets are then routed using the virtual destination ID to a decoder switch (140) in the NoC (105). This decoder switch (140) can then use the address in the packet (which is different than the destination ID) to select the appropriate target destination ID.