6 results about "Network on chip architecture" patented technology

The invention relates to a network-on-chip architecture (100) characterized by: a plurality of replicable partitions (200), each partition (200) comprising one or more routers (10) suitable for communication, a register, and a pre-built communication link established in a base direction or other direction, and one or more configuration bus nodes (20) arranged in each partition (200) connected to the register (40); a system integrator connecting the system operator (60) to one of the configuration bus nodes (20); wherein the system operator (60) initializes a path map between the configuration bus nodes (20) to form a secondary configuration network, and accesses the registers (40) in each partition to program the registers (40) with routing data. A method of processing data on a network-on-chip architecture (100) is also disclosed herein.

This invention discloses a method for optimizing the topology of a 3D on-chip network (SoC) for high-speed data acquisition systems. Addressing the problem that general-purpose 3D SoC architectures are difficult to adapt to the communication characteristics of high-speed data acquisition systems, leading to high transmission latency and redundant link resources, this method models the network topology adjustment process as a Markov decision process and employs deep reinforcement learning to achieve adaptive optimization of the topology. The method uses a general-purpose 3D SoC as the initial architecture, constructing a state representation that includes node connection features, average network latency, longest path latency, and link area; defining a pruning and regrowth action space; designing a reward function that integrates changes in average latency, longest path latency, and link area; and using a deep Q-learning network with a multilayer perceptron structure for policy training. To improve learning efficiency, an action candidate set is constructed and combined with a two-layer greedy policy to achieve fast and effective search. Through iterative learning and topology updates, a 3D SoC topology that better suits the communication load of high-speed data acquisition systems can be obtained, reducing average transmission latency and link area overhead while ensuring connectivity.

The invention discloses a data transmission method, system and device and a computer readable storage medium, relates to the technical field of network-on-chip, and is applied to a routing node of the network-on-chip to determine a source node for transmitting target data and a destination node for receiving the target data. Determining a node routing direction according to the position relationship between the source node and the destination node; according to the position relation between the routing node and the destination node, screening a next node according to the node routing direction; transmitting target data to the next node through a conventional channel of the routing node in response to the fact that the coordinate of the next node and the coordinate of the routing node have the same value; and in response to the fact that the coordinate of the next node and the coordinate of the routing node do not have the same value, transmitting the target data to the next node through the virtual channel of the routing node. On the premise of not changing a network-on-chip architecture system, transmission congestion is reduced by modifying a routing algorithm on a software level, and the data transmission efficiency of the network-on-chip is improved.

The present invention relates to a network-on-chip architecture (100), characterized by: a plurality of stampable partition (200), each partition including one or more router (10) adapted for communication, registers and pre-built communication links established in cardinal directions or other directions, and one or more configuration bus node (20) deposited in each partition (200) connecting to the registers (40); a system integrator connecting a system operator (60) to one of the configuration bus node (20); wherein the system operator (60) initializes a path mapping between the configuration bus node (20) forming a secondary configuration network and access the registers (40) in each partition to program the registers (40) with routing data A method of processing data at the network-on-chip architecture (100) is also disclosed herein.

Embodiments herein describe using a virtual destination to route packets through a NoC (105). In one embodiment, instead of decoding an address as a target destination ID for the NoC (105), an ingress logic block (115) assigns the same virtual destination ID to packets for multiple different targets. For example, the targets may be located in the same segment or location of the NoC (105). Thus, the ingress logic block (115) does not have to store an entry for each target in a lookup table, but it may have a single entry for the virtual destination ID. The virtual destination ID is then used to route the packets for the targets to a decoder switch (140) in the NoC (105). The decoder switch (140) may then select an appropriate target destination ID using the address in the packet, which is different from the destination ID.

Embodiments herein describe using virtual destinations to route packets through a NoC (105). In one embodiment, instead of decoding an address into a target destination ID of the NoC (105), an ingress logic block (115) assigns packets for multiple different targets the same virtual destination ID. For example, these targets may be in the same segment or location of the NoC (105). Thus, instead of the ingress logic block (115) having to store entries in a lookup-table for each target, it can have a single entry for the virtual destination ID. The packets for the targets are then routed using the virtual destination ID to a decoder switch (140) in the NoC (105). This decoder switch (140) can then use the address in the packet (which is different than the destination ID) to select the appropriate target destination ID.