38 results about "Network on chip architecture" patented technology

A method of interconnecting blocks of heterogeneous dimensions using a NoC interconnect with sparse mesh topology includes determining a size of a mesh reference grid based on dimensions of the chip, dimensions of the blocks of heterogeneous dimensions, relative placement of the blocks and a number of host ports required for each of the blocks of heterogeneous dimensions, overlaying the blocks of heterogeneous dimensions on the mesh reference grid based on based on a guidance floor plan for placement of the blocks of heterogeneous dimensions, removing ones of a plurality of nodes and corresponding ones of links to the ones of the plurality of nodes which are blocked by the overlaid blocks of heterogeneous dimensions, based on porosity information of the blocks of heterogeneous dimensions, and mapping inter-block communication of the network-on-chip architecture over remaining ones of the nodes and corresponding remaining ones of the links.

Systems and methods for performing multi-message transaction based performance simulations of SoC IP cores within a Network on Chip (NoC) interconnect architecture by accurately imitating full SoC behavior are described. The example implementations involve simulations to evaluate and detect NoC behavior based on execution of multiple transactions at different rates / times / intervals, wherein each transaction can contain one or more messages, with each message being associated with a source agent and a destination agent. Each message can also be associated with multiple parameters such as rate, size, value, latency, among other like parameters that can be configured to indicate the execution of the transaction by a simulator to simulate a real-time scenario for generating performance reports for the NoC interconnect.

A system and method embodying some aspects for communicating between nodes in a network-on-chip are provided. The system comprises a microprocessing chip and a plurality of connection paths. The microprocessing chip comprises sixteen processing nodes disposed on the chip. The plurality of connection paths are configured such that each is at most three hops away from any other node. Each node also has connection paths to at most three other nodes.

The invention provides a processing circuit and a neural network operating method thereof. The processing circuit comprises a plurality of processing elements, a plurality of accessory memories, a system memory and a configuration module, wherein the processing elements are used for performing operation processing; each accessory memory is corresponding to one processing element and is coupled with the other two accessory memories; the system memory is coupled with all the accessory memories and is accessible to the processing elements; the configuration module is coupled with the processing elements and the corresponding accessory memories and the system memory to form a network-on-chip architecture; and the configuration module is capable of statically configuring the operations of the processing elements and the data transmission in the network-on-chip architecture according to neural network operations. Therefore, the neural network operations can be optimized and high operation efficiency is provided.

Embodiments disclosed herein generally relate to the use of Network-on-Chip architecture for solid state memory structures, both volatile and non-volatile, which provide for the access of memory storage blocks via a router. As such, data may be sent to and / or from the memory storage blocks as data packets on the chip. The Network-on-Chip architecture may further be utilized to interconnect unlimited numbers of memory cell matrices, spread on a die, thus allowing for reduced latencies among matrices, selective power control, unlimited memory density growth without major latency penalties, and reduced parasitic capacitance and resistance. Other benefits may include improved signal integrity, larger die areas available to implement memory arrays, and higher frequency of operation.

The invention relates to a wavelength-allocation-based three-dimensional optical on-chip network router communication system and method. The communication system employs a photoelectric mixing type 3D mesh network topological structure and a novel seven-port clog-free optical router capable of realizing multi-wavelength communication; and when the system is applied to a three-dimensional optical on-chip network, no wavelength conversion is needed. Because of utilization of the optical router, the consumed number of optical devices like micro ring resonators and waveguides and the like is reduced. Besides, according to the communication method, when a node of each layer sends out an optical signal, the employed wavelengths are identical; and optical signals with all wavelengths can be received at all layers, so that problems of severe network congestion, low link utilization rate, and limited expansibility due to utilization of single wavelength communication by the existing optical on-chip network architecture can be solved. Therefore, with the system and method, the network congestion probability can be reduced; the communication delay can be reduced; and the throughput capacity and network saturation point can be improved.

The invention provides a topological structure based on a staggered three-dimensional light network-on-chip and a wavelength distribution method, and aims to solve the technical problems of serious blockage in the network and high loss in the prior art. The topological structure comprises two layers of 2D-Mesh light networks-on-chip and an interlaminar router; the light networks-on-chip comprise NxN routers connected through optical waveguides; each router is connected with an IP core; the two layers of light networks-on-chip are staggered from each other along the corresponding diagonals, and optical waveguides are added into the light networks-on-chip corresponding to gaps in four single-layer parts on the staggering edges along the optical waveguide directions in the light networks-on-chip; and the interlaminar router is arranged at a position perpendicular to the space where the optical waveguides of the different layer are positioned. The wavelength distribution method of the topological structure comprises the following steps: firstly establishing a three-dimensional coordinate system, and selecting wavelength values; secondly, distributing the wavelength values to all nodes; and finally, configuring a working offset state and temperature of an exchange microring resonator or an interlaminar microring coupler according to the wavelength values distributed to all the nodes.