Multi-cluster network-on-chip architecture based on statistic time division multiplexing technology

Abstract

The invention discloses a multi-cluster network-on-chip architecture based on a statistic time division multiplexing technology. In the architecture, a bus structure based on the statistic time division multiplexing technology is adopted in clusters; master equipment, slave equipment, a bus component and a statistic time division multiplexing control unit are arranged on a bus; the statistic timedivision multiplexing control unit is connected with the master equipment, the slave equipment and the bus component, wherein the slave equipment comprises a memory and a network interface with a waiting mechanism; the bus component comprises an arbitrator, a decoder and a multipath selector; the statistic time division multiplexing control unit unifiedly controls the master equipment and the slave equipment on the bus to realize the statistic time division multiplexing mechanism; and the network interface with the waiting mechanism receives a data transmission request initiated by the masterequipment on the bus and triggers the transmission under the condition of satisfying the triggering conditions. The multi-cluster network-on-chip architecture disclosed by the invention can effectively reduce the network load and the communication relay and further improves the whole performance of a network-on-chip system, thereby having favorable application value and wide application prospect.

Description

technical field [0001] The present invention relates to a multi-cluster on-chip network architecture, specifically a statistical time division multiplexing (Statistical Time Division Multiplex, STDM) technology that can effectively reduce network load, reduce communication delay, and improve overall system performance. Multi-Cluster Network on chip (MCNoC) architecture. Background technique [0002] With the continuous development of semiconductor process technology, the number of transistors that can be integrated on a single chip is increasing. Although it is still barely feasible to continue to improve system performance by improving the process, the commercial cost of this approach has even been reduced. Beyond its commercial benefits, the industry began to seek new ways to try to improve system performance. In this case, the concept of a single-chip multi-core processor (Multi-Processor System on Chip, MPSoC) was proposed and received widespread attention. In MPSoC, a...

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