A Cache-Coherent Behavior-Based On-Chip Network Traffic Synthesis Method

Abstract

The invention discloses an on-chip network traffic composition method based on cache consistency behavior. The steps are to abstract the CPU, cache, and directory into a node model; through the whole system simulation, count the sending and receiving of routing node data packets generated by the cache consistency constraints in the network-on-chip architecture; extract and reflect the time distribution characteristics and spatial distribution characteristics of application traffic The eigenvectors of ; based on the eigenvectors, the on-chip network traffic is synthesized using a Markov modulation model. The present invention can quickly provide accurate on-chip network traffic, save the time for the whole system to simulate and collect traffic, and accelerate the exploration process of on-chip network architecture. The network traffic synthesized by this method is consistent with the real network traffic in terms of time distribution and space distribution characteristics, which is enough to assist the design of the network-on-chip architecture.

Description

technical field [0001] The invention belongs to on-chip network traffic synthesis technology, and in particular relates to an on-chip network traffic synthesis method based on cache consistency behavior. Background technique [0002] System On Chip (SoC) has been widely used due to its advantages of high integration, small size and low power consumption. With the rapid progress of semiconductor process technology and the continuous development of architecture, the design technology of single-core processors can no longer meet the design requirements in terms of performance and cost. The development of multi-core processor technology is an inevitable trend, but the current bus model limits In order to improve the performance of inter-core communication, the research of network-on-chip architecture is put on the agenda. [0003] The research on the network on a chip in academia and industry is mainly to improve the performance of the network on a chip. Network performance ev...

AI Technical Summary

Problems solved by technology

The traffic synthesis form of these traffic models is simple and flexible when used, but they are only formed by very simple function fitting, and the accuracy is very low, so they are not suitable for evaluating the performance of future on-chip networks and exploring the network architecture.

Using the traffic generated based on the whole system simulation directly as the input of network-on-chip architecture exploration research, although the accuracy is high, the traffic acquisition complexity is high and the flexibility is poor, resulting in an increase in the time-consuming architecture evaluation

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