Cache consistency behavior-based on chip network traffic synthesis method

Abstract

The invention discloses a cache consistency behavior-based on chip network traffic synthesis method, comprising the steps: abstracting a CPU, a cache, and a directory into a node model; through system-wide simulation, performing statistics on the transmitting and receiving of data packets of routing nodes generated by the cache consistency constraint in an on chip network architecture; extractingeigenvectors embodying the time distribution characteristics and spatial distribution characteristics of the application traffic; and based on the eigenvectors, synthesizing on chip network traffic byusing a Markov modulation model. The method can quickly provide accurate on chip network traffic, reduce time for system-wide simulation traffic collection, and accelerate the exploration process ofan on chip network architecture. The network traffic synthesized by the method is consistent with the real network traffic in terms of time distribution characteristics and spatial distribution characteristics, and is sufficient to assist in the design of the on chip network architecture.

Description

technical field [0001] The invention belongs to on-chip network traffic synthesis technology, and in particular relates to an on-chip network traffic synthesis method based on cache consistency behavior. Background technique [0002] System On Chip (SoC) has been widely used due to its advantages of high integration, small size and low power consumption. With the rapid progress of semiconductor process technology and the continuous development of architecture, the design technology of single-core processors can no longer meet the design requirements in terms of performance and cost. The development of multi-core processor technology is an inevitable trend, but the current bus model limits In order to improve the inter-core communication performance, the research of network-on-chip architecture is put on the agenda. [0003] The research on the network on a chip in academia and industry is mainly to improve the performance of the network on a chip. Network performance evalu...

AI Technical Summary

Problems solved by technology

The traffic synthesis form of these traffic models is simple and flexible when used, but they are only formed by very simple function fitting, and the accuracy is very low, so they are not suitable for evaluating the performance of future on-chip networks and exploring the network architecture.

Using the traffic generated based on the whole system simulation directly as the input of network-on-chip architecture exploration research, although the accuracy is high, the traffic acquisition complexity is high and the flexibility is poor, resulting in an increase in the time-consuming architecture evaluation

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