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CDMA (code division multiple access) on-chip network architecture based on standard orthonormal basis and realization method of CDMA on-chip network architecture

A network-on-chip, implementation method technology, applied in instruments, electrical digital data processing, computers, etc., to ensure correct reception, ingenious methods, and cost-effective effects

Inactive Publication Date: 2013-11-13
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Application Information

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Problems solved by technology

[0006] The purpose of the present invention is to provide a CDMA network-on-chip architecture based on orthonormal bases and its implementation method, which mainly solves the problem that the existing network-on-chip architecture in the prior art cannot reduce waste of resources and reduce waste of resources while ensuring transmission quality and transmission efficiency. The problem of power consumption

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  • CDMA (code division multiple access) on-chip network architecture based on standard orthonormal basis and realization method of CDMA on-chip network architecture
  • CDMA (code division multiple access) on-chip network architecture based on standard orthonormal basis and realization method of CDMA on-chip network architecture
  • CDMA (code division multiple access) on-chip network architecture based on standard orthonormal basis and realization method of CDMA on-chip network architecture

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Embodiment

[0039] In order to solve the problems of low code word utilization and waste of resources in the traditional Walsh code encoding method, such as Figure 1~4 As shown, the present invention designs a CDMA network-on-chip architecture based on the standard orthogonal basis, which effectively increases the adaptability and flexibility in practical applications by using the standard orthogonal basis encoding method, and can save chip area and power consumption, which is beneficial to realize the cost control of the code division multiplexing network on chip.

[0040] Such as figure 1 , figure 2 As shown, the present invention includes a plurality of processing units, a network node interface arranged on the processing unit, a data buffer module bidirectionally connected to the network node interface, a data transceiving module bidirectionally connected to the data buffer module, a bidirectionally connected data transceiving module, An integrated network forwarding module and ar...

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Abstract

The invention discloses a CDMA (code division multiple access) on-chip network architecture based on a standard orthonormal basis and a realization method of the CDMA on-chip network architecture. The CDMA on-chip network architecture and the method mainly solve the problem that in the prior art, the on-chip network architecture cannot reduce the resource waste or reduce the power consumption while ensuring the transmission quality and the transmission efficiency. The CDMA on-chip network architecture based on the standard orthonormal basis comprises a network transmitting module, an arbitration module and more than two processing units, wherein the network transmitting module and the arbitration module are integrated, and the processing units are connected with the network transmitting module and the arbitration module respectively through network nodes. Through the scheme, the CDMA on-chip network architecture and the method have the advantages that the goals that the transmission quality and the transmission efficiency are high, in addition, the resource waste and the power consumption are low are reached, and high practical value and popularization value are realized.

Description

technical field [0001] The invention relates to a CDMA on-chip network architecture based on orthonormal basis and its realization method. Background technique [0002] As the number of processors integrated on a single chip increases, multiprocessor systems have increasingly used Network-on-Chip (NoC) architectures to solve the problems of large inter-processor communication and high communication delay. [0003] The existing network-on-chip architecture mainly includes the traditional network-on-chip architecture based on the cache method. This network-on-chip architecture can solve the problem of data communication between nodes and can improve a certain data transmission delay, but it is not suitable for the connection between two nodes. However, the stability of the data transmission delay cannot be guaranteed, that is, the transmission delay between nodes is a variable and is affected by the network congestion situation. Therefore, the buffer-based network-on-chip is ...

Claims

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Application Information

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IPC IPC(8): G06F15/173
Inventor 钟阳王坚陈北辰李玉柏李桓
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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