26 results about "System-level simulation" patented technology

The invention discloses a digital pre-distortion algorithm verification method and device suitable for a large-scale antenna array, and the method comprises the steps: constructing a single-channel radio frequency link, and obtaining the input data and output data of a power amplifier; taking input data and output data of the power amplifier as a training set, and training by using a target digital pre-distortion algorithm to obtain a pre-distorter model and a pre-distorter model correlation coefficient; modeling input data and output data of a power amplifier into a high-precision mathematical model through a neural network method, loading the high-precision mathematical model into a radio frequency channel of the large-scale phased array system-level simulation model, and adding actual damage into the large-scale phased array system-level simulation model; deploying a predistorter model in a radio frequency channel of the large-scale phased array system-level simulation model, and evaluating the final performance of a target digital predistortion algorithm from multiple dimensions; modeling and digital pre-distortion training are carried out based on hardware actual measurement data, the research and development cost is reduced, and algorithm optimization and system design are guided.

The invention discloses a coaxial electric drive axle gear microscopic modification analysis method based on MASTA and Abaqus, and belongs to the technical field of electric vehicle transmission. The method comprises the following steps: firstly, building an electric drive axle transmission model in the MASTA; secondly, creating power substructure models of key components such as a differential case, a bull gear spoke and an axle housing in Abaqus, and importing the power substructure models into MASTA to construct a high-precision flexible system model; then, a gear finite element model is generated in the MASTA, and a condensation stiffness matrix of the gear finite element model is calculated; thirdly, calculating initial gear dislocation quantity under different working conditions by utilizing advanced loading tooth surface analysis; and finally, performing targeted tooth direction and tooth shape microcosmic modification on the gear according to the dislocation quantity, and verifying whether the transmission error and the tooth surface pressure of the gear meet the design standard or not. Through deep fusion of MASTA and Abaqus, balance of precision and efficiency in system-level simulation is realized, a scientific basis is provided for gear modification, and NVH performance and reliability of the electric drive axle are remarkably improved.

The invention discloses a graph processor modeling and analyzing method and device, and belongs to the field of computer system structure aided design. The method comprises the following steps: establishing a unified calculation model decoupled from a storage architecture model; full-link micro-architecture behavior data is obtained through FPGA actual measurement, and a bandwidth constraint model is constructed to determine the optimal parallelism degree of a calculation unit; carrying out closed-loop calibration on bus delay and internal logic parameters of the simulation model by utilizing measured data; and on the calibrated reference model, keeping the optimal parallelism unchanged, and carrying out space evaluation and performance quantitative analysis on various storage architecture schemes. The device comprises an upper computer, an FPGA hardware platform and a communication interface assembly, wherein system-level simulation software and hardware control software are integrated on the upper computer. According to the method, by constructing a software and hardware closed-loop cooperation mechanism, the problems that the degree of parallelism is difficult to reasonably determine and the simulation precision of pure software is insufficient are solved, and high-precision and high-efficiency evaluation of the calculation subsystem and the storage subsystem of the graph processor is realized.

The application discloses a chip model simulation calibration method and device and a storage medium, relates to the chip architecture simulation field, and comprises the following steps: determining the simulation deviation of a specified function dimension according to system-level simulation results and operator-level simulation results for each target computation graph node; screening a target function dimension from the specified function dimension according to the simulation deviation, and acquiring a parameter set associated with the target function dimension in the target computation graph node; and performing hierarchical inverse labeling on the parameter set according to the simulation deviation of the target function dimension. The system-level simulation results are used to intelligently filter the operator-level simulation space, blind traversal of low-value invalid configurations is avoided, an error decomposition mechanism is introduced, estimated errors are attributed according to dimensions such as computation, memory access, communication and power consumption, directional inverse labeling instead of traditional global parameter fitting is realized, hierarchical inverse labeling strategies are used, parameter interference between different operator families is reduced, the model can adapt to various complex scenes, and parameter oscillation is avoided.

The present application relates to a kind of rule-based aerospace equipment system level simulation guiding and adjusting intervention system and method, the system includes: scenario loading subsystem, for the structured data in external scenario file is parsed, form the initialization data required for guiding and adjusting rule editing and situation display;Guiding and adjusting rule editing subsystem, for the definition, generation and sending of the rule of guiding and adjusting intervention;Situation display subsystem, for the detailed parameter display of guiding and adjusting result in guiding and adjusting intervention process Visual display;Rule guiding and adjusting model, for the condition satisfaction of simulation scene according to conditional logic monitoring, and according to the condition satisfaction Guiding and adjusting instruction set is sent.The present application solves the problem that traditional guiding and adjusting is easy to appear missed judgment, delay, timeliness is not strong, complex rule support is not strong, realizes the full process automation, can guarantee the adaptability of system simulation complex guiding and adjusting rule, can also guarantee the accuracy and real-time performance of guiding and adjusting intervention process execution.

The invention discloses an air handling system of an air conditioning unit and a control method of the air handling system, and belongs to the technical field of air conditioning systems, and the system constructs an intelligent agent with sensing, predicting, decision-making and optimizing capabilities by fusing a physical entity, edge control and a cloud platform. The core of the method is that the AI technology is utilized to predict building load and personnel change, system-level simulation optimization is performed through digital twinning, air supply parameters and fresh air volume are dynamically set, and a variable air volume control mode is adaptively switched. According to the method, the hysteresis of traditional feedback control is overcome, conversion from passive response to active intervention is achieved, the energy efficiency, comfort and adaptability of the system are remarkably improved, and the method is suitable for modern intelligent buildings with high-standard requirements for indoor environment quality and energy consumption.

The invention provides a multi-board circuit simulation method and system, computer equipment and a storage medium. The method comprises the following steps: acquiring device pin information and network topology information of each circuit board in a multi-board circuit; marking each device pin on each circuit board as a starting point or an ending point of a cross-board signal; constructing a connector model, wherein the connector model comprises a 0-ohm resistance model and an S parameter model; establishing a cross-board pin mapping relation that the device pins on each circuit board are mapped to the device pins on other circuit boards through the connector model; and selecting a 0-ohm resistance model and / or an S parameter model based on the type of the cross-board signal, and performing multi-board circuit system-level simulation in combination with the cross-board pin mapping relationship. According to the scheme, pin and connector modeling can be accurately carried out in multi-board circuit simulation, the parasitic effect and real topological information are guaranteed, the characteristics of insertion loss, reflection, mode conversion and the like under high-speed signals can be accurately reflected, and simulation of a multi-board circuit is more accurate.

The application discloses a method, an electronic device and a storage medium for accelerating system-level simulation verification, comprising: establishing a register model in a simulation verification environment, the register model comprising a built-in read function for accessing a target register through a backdoor path; after use case chaining is completed, reading an initial value of the target register through the backdoor path of the register model and storing; in the use case execution process, reading a current value of the target register through the backdoor path of the register model in real time, and comparing with a predefined condition to verify the simulation state; at the end of the simulation, reading a final value of the target register through the backdoor path of the register model again; comparing the initial value with the final value, and triggering an error report if they are inconsistent.

An implementation of a method for generating a product system model may include receiving a selection of a product type from a user using a first interface (120), selecting a product SPICE model associated with the product type from a database of product SPICE models, and receiving a selection of process conditions from the user using a second interface (130). The method may include receiving one or more system characteristics and one or more operational characteristics from the user using a third interface (134), receiving one or more circuit characteristics from the user using a fourth interface (140), generating SPICE model output using the product SPICE model using a SPICE model simulation module (110), and formatting the SPICE model output into a product system model file using a formatting module (112).

The invention relates to the technical field of integrated circuit design, in particular to an integrated verification system and method based on multi-protocol bridging. By configuring the control and bridging conversion module, an instruction of the first communication interface is dynamically converted into a bottom layer target protocol time sequence, so that a uniform register access entry is constructed. The design effectively avoids the redundant work of writing a drive code for each peripheral protocol in the traditional verification. Meanwhile, in a system-level simulation stage, the mechanism enables a high-level test sequence and a bottom-layer physical protocol to be thoroughly decoupled, so that the time overhead caused by frequent development and mounting of different interfaces is reduced, and the cross-level reuse rate and the overall simulation efficiency of a verification environment are improved. After the built-in self-test engine is introduced, the system can automatically generate continuous target access addresses and expected test data internally through hardware logic according to a preset instruction. Automatic internal excitation generation can improve the automation level and the screening efficiency in the chip mass production test stage.

The application discloses a kind of based on SiP chip's transient radiation effect circuit level fault simulation system and method, including clock signal generation module, fault injection module, ADC simulation module, voltage comparator simulation module, FPGA simulation module, DAC simulation module and level driver simulation module;Clock signal generation module is connected with ADC simulation module, DAC simulation module and FPGA simulation module, and the output end of ADC simulation module and voltage comparator simulation module is connected with the input end of FPGA simulation module, and the input end of DAC simulation module and level driver simulation module is connected with the output end of FPGA simulation module;Each simulation module includes IBIS model and SPICE circuit level model / Verilog behavior level model;The present application establishes the SiP system level simulation model including each chip simulation module and signal transmission module in SiP interior.Given simulation model input signal and transient radiation excitation, the output signal of entire SiP system level simulation model can be obtained.

This invention discloses a protection and control method and system for energy storage converter testing under extreme environments. The method includes calibrating the parameters of a multiphysics reduced-order simulation model based on measured performance data to obtain a calibrated multiphysics reduced-order simulation model; embedding a device-level performance degradation proxy model into the calibrated multiphysics reduced-order simulation model to obtain a system-level simulation model; inputting environmental parameter samples into the system-level simulation model for simulation, obtaining risk assessment results based on the performance simulation result set, and selecting at least one high-risk environmental parameter combination; obtaining corresponding physical test cases, driving test equipment to perform physical extreme environment tests on the energy storage converter, comparing the measured results with the prediction results obtained by the system-level simulation model based on the corresponding high-risk environmental parameter combination simulation, and optimizing the parameters of the multiphysics reduced-order simulation model and the device-level performance degradation proxy model to ensure the reliability of the energy storage converter operating under extreme environments.

This invention discloses a simulation evaluation method and apparatus for chip models, comprising: generating feasible deployment strategies for the computational graph of an AI model through an AI system-level simulation platform, and sending the operator feature information of each candidate deployment strategy extracted from the candidate deployment strategy set to a cloud base; determining the target deployment strategy requiring accurate simulation based on the user's simulation requirements through the cloud base, and sending the operator-level simulation task to the SOC operator-level simulation platform; the SOC operator-level simulation platform feeding back the obtained accurate simulation results to the cloud base, and the cloud base performing accuracy back-annotation on the target deployment strategy based on the accurate simulation results. By introducing a cloud base and cloud-based elastic computing resources, standardized access and end-to-end data connectivity of heterogeneous simulation platforms are achieved. This solution not only improves the efficiency of operator-level simulation from single-machine serial to large-scale parallel in the cloud, but also significantly improves the accuracy of overall network performance prediction through a dynamic back-annotation mechanism.

This invention discloses a digital twin experimental system and testing method for dynamic target firing using high-repetition-rate lasers. The system includes a high-fidelity multiphysics model cluster, a virtual diagnostic module, a data-driven interface, a simulation engine and scheduler, and a visualization and analysis platform. The model cluster includes a target flight dynamics model, a beam transmission and control model, and a beam-target interaction physical model. The data-driven interface supports bidirectional data interaction between the digital twin system and the physical target firing system. The virtual diagnostic module outputs simulation data comparable to that of the physical system. This invention possesses system-level simulation capabilities that integrate the entire chain of "target injection – trajectory measurement – ​​beam control – interaction – physical results," and can be used for virtual testing of control strategies, performance prediction of novel target components, system fault prediction and health management, significantly reducing experimental costs and risks, and accelerating research and development iterations.

This invention discloses a simulation calibration method, apparatus, and storage medium for chip models, relating to the field of chip architecture simulation. The method includes: determining the simulation deviation of a specified functional dimension for each target computation graph node based on system-level and operator-level simulation results; filtering target functional dimensions from the specified functional dimensions based on the simulation deviation, and obtaining the parameter set associated with the target functional dimension in the target computation graph node; and performing hierarchical back-annotation on the parameter set based on the simulation deviation of the target functional dimension. The system-level simulation results are used to intelligently filter the operator-level simulation space, avoiding blind traversal of low-value, ineffective configurations. By introducing an error decomposition mechanism, the estimation error is attributed according to dimensions such as computation, memory access, communication, and power consumption, achieving targeted back-annotation instead of traditional global parameter fitting. The hierarchical back-annotation strategy reduces parameter interference between different operator families, enabling the model to adapt to various complex scenarios and avoiding parameter oscillations.

The invention provides a dynamic full-link simulation method and system for space gravitational wave detection spacecraft formation. A multi-physical field model, a full-link noise model and drag-free control are fused to carry out system-level simulation. The method comprises the steps that firstly, multi-physics field models such as a temperature field, a magnetic field and a self-gravitational field are established, optical measurement noise and residual acceleration noise models are combined and input to a spacecraft formation orbit dynamics and drag-free control system, then the drag-free control model feeds satellite state information after control back to the multi-physics field models, system-level closed-loop simulation is carried out, and the system-level closed-loop simulation is carried out. State changes of the spacecraft are dynamically analyzed, scientific measurement data are output to evaluate the sensitivity of the spacecraft formation space gravitational wave detection system, a multi-physical field noise transmission rule among an instrument, the spacecraft and the environment is disclosed, and space gravitational wave detection spacecraft formation dynamic full-link simulation is achieved.

The application provides a multi-board circuit simulation method and system, computer equipment and a storage medium. The method comprises the following steps: obtaining device pin information and network topology information of each circuit board in a multi-board circuit; marking each device pin on each circuit board as a starting point or an ending point of a cross-board signal; constructing a connector model, wherein the connector model comprises a 0-ohm resistance model and an S parameter model; establishing a cross-board pin mapping relationship of the device pins on each circuit board to the device pins on other circuit boards through the connector model; selecting the 0-ohm resistance model and / or the S parameter model based on the type of the cross-board signal, and performing multi-board circuit system-level simulation in combination with the cross-board pin mapping relationship. The scheme can accurately perform pin and connector modeling in multi-board circuit simulation, ensure parasitic effects and real topology information, and accurately reflect the insertion loss, reflection and mode conversion characteristics under high-speed signals, so that the simulation of the multi-board circuit is more accurate.

Multiple Access Point Coordination (MAPC) is directed to enhance WiFi performance by enabling a set of Access Points (APs) to coordinate with each other through advanced coordinating schemes to reduce inter-AP contention and congestion. A process framework is described which facilitates coordination across multiple-APs using Coordinated Spatial Reuse (C-SR), that reciprocally adjust their scheduling strategy, power control and link adaptation to meet specific Quality of Service (QoS) requirements. A two-layer Multi-Armed Bandit (MAB) approach is described, which also preserves fair use of resources across all nodes. The validity of this approach is confirmed by system level simulations, which validate the improved efficiency in terms of sum-throughput, as well as enhanced fairness.

This invention provides a harmonic assessment method and system for the MMC flexible DC transmission system of a semi-direct drive offshore wind turbine. This method constructs an assessment system covering all electrical nodes along the entire path, a wide frequency range, and multi-dimensional indicators, specifically addressing the harmonic and ultra-high-order harmonic characteristics of this system. Through a complete process of full-element data collection and parameter calibration, precise equipment modeling and system-level simulation, fine extraction and analysis of wide-band harmonics, evaluation of multi-dimensional superposition results, and precise source tracing and optimization of suppression measures for excessive harmonics, it achieves comprehensive and accurate assessment and targeted management of system harmonics and ultra-high-order harmonics, solving the problems of incomplete assessment, low accuracy, and weak targeting in existing technologies.

The invention discloses a system-level simulation method for an L-band switch filter module, and belongs to the technical field of radio frequency device simulation, and the method comprises the steps: importing a module 2D layout into 3D electromagnetic simulation software, and building a module 3D model; single-channel cutting is conducted on the module 3D model in a plane cutting mode, and a target single channel is reserved; s parameter simulation is carried out according to the single channel, and insertion loss, an input reflection coefficient and an output reflection coefficient of the single channel are extracted; building a TDR simulation circuit in the ADS, and positioning an impedance discontinuous point; and building a joint simulation circuit in the ADS, and carrying out S parameter joint simulation and verification. According to the invention, electromagnetic-circuit collaborative analysis is realized, reliable support is provided for module structure optimization and ringing suppression, and the technical problems of low simulation efficiency, inaccurate impedance discontinuous point positioning and large simulation and actual measurement deviation in existing L-band switch filter module simulation are solved.

This invention provides a continuous beam scanning method for liquid crystal phased arrays based on non-return-to-zero switching, belonging to the field of phased array antenna technology. The method involves obtaining the correspondence between the driving voltage and the steady-state liquid crystal molecule orientation angle, the driving voltage and the steady-state effective dielectric constant, and a microstrip transmission line model, thus establishing the relationship between the driving voltage and the phase difference. Based on the target beam pointing angle and the phased array antenna parameters, the target phase compensation value is obtained. Based on the correspondence between the driving voltage and the phase difference and the target phase compensation value, array-level dynamic simulation is performed to obtain a fixed driving voltage and a dynamic response curve. Based on the dynamic response curve and the fixed driving voltage, the driving voltage is adjusted using a unidirectional progressive control strategy, and under the constraint that no phase loopback occurs in any radiating element, continuous beam scanning results are obtained. This invention solves the bottleneck problems of rapid continuous scanning and system-level simulation optimization in liquid crystal phased arrays.

The invention discloses an ultra-low delay emission calibration method realized based on an FPGA, which belongs to the technical field of wireless communication, and comprises the following steps: establishing a mathematical algorithm model comprising emission calibration measurement, calculation and compensation based on array antenna parameters and radio frequency link indexes; fPGA logic design is completed based on a mathematical algorithm model, an emission calibration measurement module, a calculation module and a compensation module are realized, and verification is carried out through module-level simulation and system-level simulation; carrying out integration, layout and wiring on the simulated FPGA logic, generating a configuration file, and downloading the configuration file to an FPGA chip; a hardware test platform is established, the FPGA is connected with the hardware test platform, a test instrument is used for operation according to the emission calibration test process, and emission calibration amplitude phase consistency index verification work is completed. Depending on the strong parallel processing capability of the FPGA chip and the high-speed clock, the delay caused by processing is greatly reduced, and meanwhile, the transmission paths are greatly reduced, so that the real-time performance and the stability of calibration are improved.

The invention discloses a simulation method and system of an aircraft fault prediction and health management (PHM) architecture. The method comprises the following steps: dividing an aircraft system into a data acquisition layer, a signal processing layer, a state monitoring layer, a health assessment layer, a prediction layer and a decision support layer according to a PHM system architecture; a simulation model of each layer is constructed in sequence, and sensor data acquisition and noise addition, data noise reduction and conversion, abnormal state judgment based on threshold detection, health assessment and fault probability calculation based on Bayesian reasoning, residual service life prediction based on a degradation trend and maintenance decision generation based on comprehensive cost optimization are simulated respectively. The invention provides a hierarchical and standardized system-level simulation solution, which can perform dynamic and executable verification and optimization on the overall architecture design, each layer of algorithm logic and interaction performance of the PHM system before physical prototype manufacturing, and effectively solves the problems of disjunction of design and verification, tight model coupling and poor reusability in the prior art. And the development cost and risk are obviously reduced.

The invention discloses a distributed coupling simulation system, method, device and equipment for a heavy-load train. The system comprises a distributed simulation management module and a plurality of train simulation modules, the plurality of train simulation modules comprise an electric traction transmission module, an air braking module, a longitudinal dynamics module, a business description module, a driving simulation module and a three-dimensional dynamics module; and the distributed simulation management module is used for performing joint management on the plurality of train simulation modules so as to establish system-level simulation. By adopting the system, the running state of the heavy-load train can be comprehensively monitored and evaluated, so that the running safety and the transportation efficiency of the heavy-load train can be improved.

Multiple Access Point Coordination (MAPC) is directed to enhance WiFi performance by enabling a set of Access Points (APs) to coordinate with each other through advanced coordinating schemes to reduce inter-AP contention and congestion. A process framework is described which facilitates coordination across multiple-APs using Coordinated Spatial Reuse (C-SR), that reciprocally adjust their scheduling strategy, power control and link adaptation to meet specific Quality of Service (QoS) requirements. A two-layer Multi-Armed Bandit (MAB) approach is described, which also preserves fair use of resources across all nodes. The validity of this approach is confirmed by system level simulations, which validate the improved efficiency in terms of sum-throughput, as well as enhanced fairness.

The invention discloses a lumped model-based rapid modeling method for a quantum well semiconductor optical amplifier. The method comprises the following steps of: S1, extracting parameter data; s2, constructing a lumped model; s3, performing numerical simulation calculation; s4, extracting design parameters; and S5, system-level simulation optimization is carried out. Compared with an existing space-time two-dimensional device model, the lumped model-based rapid modeling method for the quantum well semiconductor optical amplifier has the advantages that original two-dimensional space-time solution is simplified into one-dimensional time solution by integrating a space propagation equation and combining reasonable approximation, so that the calculation efficiency is improved in an order of magnitude manner, and the modeling precision is improved. The time domain simulation speed of the quantum well semiconductor optical amplifier can be obviously improved, and the calculation time consumption of device and system joint debugging in the parameter extraction and optimization design process is effectively shortened.