Convolutional neural network acceleration processing system and method based on FPGA, and terminal

Abstract

The invention provides a convolutional neural network acceleration processing system and method based on an FPGA, and a terminal. The problems that in the prior art, the inherent computing characteristics of a convolutional neural network are mismatched with a network-on-chip architecture, the hardware acceleration efficiency is low, the parallelism difference of a network layer in different dimensions is large, and the memory access characteristics of different network layers are different are solved. The acceleration efficiency, the data throughput rate and the calculation energy efficiencyof the convolutional neural network on the FPGA are improved through an assembly line architecture, a customized multistage memory access strategy and convolutional parallel optimization.

Description

technical field [0001] The present application relates to the technical field of artificial intelligence, in particular to an FPGA-based convolutional neural network accelerated processing system, method and terminal. Background technique [0002] In recent years, with the continuous development of artificial intelligence technology and the explosive growth of data volume, deep learning technology represented by convolutional neural network (CNN) has been widely used in human-like visual analysis (target detection, classification, tracking), etc. Brain cognitive tasks, and achieved remarkable results. Due to the increasing complexity of application scenarios, the structure of network models is becoming more and more complex and the depth is also increasing, which brings very serious challenges to the real-time processing of general computing platforms. [0003] Due to the demanding performance and energy efficiency requirements of embedded platforms, the deployment of convo...

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Problems solved by technology

[0006] In view of the shortcomings of the prior art described above, the purpose of this application is to provide an FPGA-based convolutional neural network acceleration processing system, method, and terminal to solve the inherent computing characteristics and deployment of convolutional neural networks in the prior art. In the case of on-chip network architecture mismatch, there is still a lot of room for improvement in hardware acceleration efficiency, and there are problems such as large differences in the degree of parallelism in different dimensions of the network layer, and different memory access characteristics of different network layers.

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