Intensive operation-oriented hierarchical heterogeneous multi-core on-chip network architecture

Abstract

The invention discloses an intensive operation-oriented hierarchical heterogeneous multi-core on-chip network architecture. The top layer of the architecture is integrated with multiple operation clusters, a transposition cluster, a communication interface and a global sharing storage unit by use of a two-dimensional grid on-chip network; a bus architecture is adopted in the operation clusters and the transposition cluster on the bottom layer; the internal bus of each operation cluster is integrated with various operation units and direct memory access, a network interface and an in-cluster sharing storage unit; and the internal bus of the transposition cluster is integrated with a processor core, direct memory access, a network interface and an in-cluster sharing storage unit. The architecture disclosed by the invention can support multiple groups of global sharing storage units which are independent from each other; each global sharing storage unit can be integrated to the on-chip network through multiple network interfaces; the in-cluster sharing storage units are distributed in the operation clusters and the transposition cluster; and the sharing storage units in the operation clusters are divided into multiple groups independent from each other. According to the invention, the communication performance, data processing capability and access bandwidth of the system can be effectively improved through the hierarchical multi-level architecture and multi-channel access.

Description

technical field [0001] The present invention relates to a hierarchical heterogeneous multi-core network on chip (Network on chip, NoC) architecture and its hierarchical storage scheme for intensive computing. Heterogeneous multi-core system architecture and hierarchical storage solution with high capacity and memory access bandwidth. Background technique [0002] With the rapid development of semiconductor process technology, the integration level of single chip is getting higher and higher, and multi-core has become the hot spot of recent chip industry research and the main development direction in the future. According to different on-chip interconnection methods, the multi-core architecture can be divided into bus-based interconnection and network-based interconnection. The former is an extension of the existing bus architecture, which integrates multiple processor cores through technologies such as multi-bus and hierarchical bus; while the latter is a brand-new concept ...

AI Technical Summary

Problems solved by technology

Based on the above analysis, it can be seen that the existing network-on-chip architecture cannot well meet the needs of practical applications.

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