A
system and method for accurately measuring a pulse run length in a
high frequency (HF)
data signal while utilizing a low analog-to-
digital conversion (ADC) sampling rate. Four bits are added to the most significant end of an oscillator's accumulator register so that the oscillator generates a sawtooth
clock waveform
ranging in phase from zero (0) to 32pi radians. An interpolator detects a first zero-crossing transition of the HF
data signal at the
leading edge of the pulse run length, and a
phase detector measures a first phase increment at that time. The MSBs of the accumulator register is then initialized to place the measured first phase increment in a range between zero (0) and 2pi radians. The accumulator register then accumulates phase increments until the interpolator detects a second zero-crossing transition of the HF
data signal at the
trailing edge of the pulse run length, and the
phase detector measures a second phase increment when the second zero-crossing transition is detected. An accumulated
phase difference is calculated by subtracting the initialized first phase increment from the measured second phase increment. The pulse run length is then obtained by dividing the accumulated
phase difference by 2pi.