11 results about "Cryptographic accelerator" patented technology

A cryptographic accelerator utilizes a combination of parallel and pipelined butterfly operator circuit to perform number theoretic transform (NTT) or inverse NTT (INTT.) The accelerator includes a first set of pipelined pairs of parallel butterfly operator circuits configured to operate on pairs of polynomial coefficients to provide output coefficients. A first buffer is coupled to store the output coefficients. A second set of pipelined pairs of parallel butterfly operator circuits are configured to operation on pairs of coefficients obtained from the first buffer to provide coefficients of the polynomial in a number theoretic transform (NTT) domain or out of the NTT domain.

A circuit arrangement includes a plurality of cryptographic accelerators. Each cryptographic accelerator is configured to perform cryptographic operations according to a respective cryptographic protocol. A first memory is coupled to the cryptographic accelerators. A first processor is configured to specify, in response to requests to perform the cryptographic operations, parameters to the cryptographic accelerators according to the requests. The first processor is configured to identify, in the first memory, keys that are associated with the cryptographic accelerators, and signal the cryptographic accelerators to commence performing the cryptographic operations according to the parameters and using the associated keys.

The invention discloses a security verification encryption accelerator, an application method, equipment, a medium and a product, and relates to the technical field of accelerators, and the security verification encryption accelerator comprises a verification module which is used for verifying whether an address interval corresponding to a to-be-verified code is complete based on a preset address verification interval and a preset address verification value under the condition that the to-be-verified code is received; and the security key management module is used for processing the encryption and decryption request corresponding to the to-be-verified code under the condition that the address interval corresponding to the to-be-verified code is complete. The technical problem of poor safety of the accelerator is solved.

This utility model discloses a dual-backup high-voltage power supply security upgrade system based on dynamic key RC4 encryption, relating to the field of automotive high-voltage power supply management technology. It includes a main control chip, a memory connected to the main control chip, an encryption accelerator, and a secure communication interface. The memory contains a key generation module and a dual-storage partition module. The key generation module contains a dynamic key RC4 encryption module and is connected to the encryption accelerator. The dual-storage partition module includes a main storage area and a backup storage area, with a remapping module between the main and backup storage areas. This utility model effectively avoids system paralysis caused by upgrade interruptions by setting the main partition of the dual-storage partition module to run the current firmware and the backup area to store the firmware to be upgraded, thus improving the reliability of the system upgrade. Furthermore, by setting the key generation module to generate dynamic keys for the upgraded system, it effectively increases the difficulty of cracking and improves the security of the system upgrade.

Examples described herein provide a computer-implemented method that includes performing, using a cryptographic accelerator, a cryptographic operation asynchronously relative to a core pipeline. The method further includes computing a chaining value for the cryptographic operation. The method further includes, responsive to an occurrence of an error, recovering from the error using the chaining value.

The invention relates to a device, in particular an automation device, having a flexible communication structure for real-time network applications with high data security, and to a method for configuring the device. In order to support all market-related communication protocols used in automation engineering, the device (AG) has a communication processor (KP) having: at least one freely programmable communication controller (KC), at least one freely programmable data controller (DC) and at least one interactive dual-port RAM memory (DPM), wherein the communication processor (KP) cooperates with a higher-level control system via the host interface (HS), whereby the higher-level control system is exchangeable,-at least one flexible communication fabric integrated in the communication controller (KC), by means of a processor core (gMAC: RPU, TPU; gPEC), at least one flexible data processing structure integrated in the data controller (DC) and having a cryptographic accelerator (KB), and an exchangeable physical interface (PYS) arranged in the device (AG) and connected via a signal line to a communication controller (KC) arranged in the communication processor (KP) for transmitting the identification code (ID), the control data (ST), the reception data (ED) and the transmission data (SD), therefore, processing, filtering and distribution of the data streams within the transmission rate range of 10 Mbps to 1 Gbps are realized. 2.2 The invention is applicable to the field of equipment with a flexible communication structure, in particular to automation equipment.

The application discloses a reconfigurable cryptographic accelerator based on a modulo-30 two-dimensional sieve table and an FPGA implementation method thereof, and belongs to the technical field of FPGA hardware acceleration and cryptographic chips. The application constructs an 8-column and multi-row two-dimensional sieve table structure by using a modulo-30 reduction residue system, and compresses a candidate prime number space by 73.3%; a modulo-30 address generation unit is adopted to generate a storage address by using a 3-bit state machine and a row counter, only shift and addition operations are needed, and division and modulus are completely replaced; a matrix deletion operation unit is used to realize parallel screening of multiple processing units, and address iteration and bit operation are used to complete composite marking; a reconfigurable multi-mode application module is used to dynamically distribute prime number streams to different functional modules such as prime number direct output, random number generation, key derivation, hash calculation and the like, and supports runtime mode switching. The application realizes high-speed, low-resource and deterministic prime number generation and multi-mode cryptographic acceleration on an FPGA, and can be applied to cryptographic chips, blockchain nodes, post-quantum cryptographic systems and secure terminal devices.

The disclosed embodiments relate to a cryptographic accelerator circuit comprising: a first affine transformation circuit to generate a first data block from an input data block; an SM4 S-box circuit configured to perform a first byte S-box operation according to an SM4 cipher and using an SM4 S-box table, the SM4 S-box operation being applied to the first transformed data block to obtain a substitution data block; and a second affine transformation circuit to generate a second data block from the substitution data block, wherein the first affine transformation circuit and the second affine transformation circuit are configured to perform a multiplication of the substitution data block with a respective matrix and an addition of a respective translation vector, and wherein the first affine transformation circuit and the second affine transformation circuit are configured such that the second transformed data block is equal to an input data block processed by a second S-box operation using an S-box table according to another symmetric cipher.

Digital hardware architecture containing elements for the protection of confidentiality, authenticity and integrity against quantum attacks, for which the invention includes: (CPU) (101); hardware based on a Chain of Trust (CoT) comprising: a hardware RoT (110), and a reconfigurable section for hosting post-quantum cryptographic accelerators (103) related to PQ (post-quantum) security; a non-volatile memory (NVM) (104); on-chip SRAM (126) and Flash (127) memories; and peripherals (120, 121,122,123,124,125), wherein the hardware RoT (110) comprises the following modules: a Hash-Based Signature (HBS) block (111); a control unit (112) for managing the RoT functions; and an immutable storage (113), which stores the information required for integrity verification purposes. The hardware RoT starts two processes: secure boot and secure reconfiguration, and in addition neither the CPU (101) nor other architecture blocks interfere with the internal operations of the hardware RoT.

Examples described herein provide a computer-implemented method that includes performing, using a cryptographic accelerator, a cryptographic operation asynchronously relative to a core pipeline. The method further includes computing a chaining value for the cryptographic operation. The method further includes, responsive to an occurrence of an error, recovering from the error using the chaining value.

A circuit arrangement includes a plurality of cryptographic accelerators. Each cryptographic accelerator is configured to perform cryptographic operations according to a respective cryptographic protocol. A first memory is coupled to the cryptographic accelerators. A first processor is configured to specify, in response to requests to perform the cryptographic operations, parameters to the cryptographic accelerators according to the requests. The first processor is configured to identify, in the first memory, keys that are associated with the cryptographic accelerators, and signal the cryptographic accelerators to commence performing the cryptographic operations according to the parameters and using the associated keys.