9 results about "Ip processing" patented technology

The invention discloses a malicious IP processing method and device, electronic equipment and a storage medium. The method comprises the steps of performing preprocessing according to acquired source data; performing machine learning feature extraction according to the preprocessed source data to obtain a first feature set, and inputting the first feature set into a machine learning model to obtain a first malicious IP set; performing deep learning feature extraction according to the preprocessed source data to obtain a second feature set, and inputting the second feature set into a deep learning model to obtain a second malicious IP set; determining an attack graph according to the source data, and performing attack evaluation according to the attack graph to obtain an evaluation result; a forbidding strategy is determined according to the evaluation and the malicious IP, the malicious IP is forbidden according to the forbidding strategy, and the malicious IP comprises a first malicious IP set and a second malicious IP set. The malicious IP can be identified through a machine learning model and a deep learning model. On the basis of accurately identifying the malicious IP, the malicious IP is automatically forbidden.

Apparatuses for partially offloading processing from a user equipment (UE) to a cellular Radio Access Network (RAN) node are disclosed. An apparatus for a UE includes at least one processor configured to perform Transmission Control Protocol and Internet Protocol (TCP / IP) processing and offload only a portion of the TCP / IP processing to a cellular RAN node while maintaining TCP protocols running end-to-end between the UE and a remote host.

Techniques for host devices to offload iSCSI and NVMe / TCP data plane processing for data plane traffic to a NIC, and for the NIC to perform the data plane traffic processing in hardware. Traditionally, network protocol stacks have been implemented within the kernel of an operating system of a computing device. In light of this, iSCSI and NVMe / TCP user space applications running on host devices interact with a kernel of an operating system using system calls in order to send network traffic. However, the system calls, TCP / IP processing, and data copying required when communicating via the kernel increases CPU utilization as well as I / O latency. Techniques described herein include configuring the host device to enable kernel bypass for data path traffic for iSCSI and NVMe / TCP user space applications, and a NIC may include hardware configured to perform the iSCSI and NVMe / TCP processing for iSCSI and NVMe / TCP connections.

Techniques for host devices to offload iSCSI and NVMe / TCP data plane processing for data plane traffic to a NIC, and for the NIC to perform the data plane traffic processing in hardware. Traditionally, network protocol stacks have been implemented within the kernel of an operating system of a computing device. In light of this, iSCSI and NVMe / TCP user space applications running on host devices interact with a kernel of an operating system using system calls in order to send network traffic. However, the system calls, TCP / IP processing, and data copying required when communicating via the kernel increases CPU utilization as well as I / O latency. Techniques described herein include configuring the host device to enable kernel bypass for data path traffic for iSCSI and NVMe / TCP user space applications, and a NIC may include hardware configured to perform the iSCSI and NVMe / TCP processing for iSCSI and NVMe / TCP connections.

The embodiment of the invention discloses a protocol stack applied to a 5G gateway and the 5G gateway, relates to the technical field of communication, and can meet the function requirement of simultaneously supporting the 5G gateway and local area network end equipment to surf the Internet. In the protocol stack, a transport layer protocol processing module is connected with a gateway application interface and a socket interface through an internally arranged transport layer interface, and a network layer processing module is connected with the transport layer protocol processing module through an internally arranged IP: port pool interface and an IP processing interface; wherein the gateway application interface is used for serving an auditing / forwarding application of the 5G gateway; the socket interface is used for serving a client application of the 5G gateway; the network layer processing module is used for processing the traffic from the transmission layer protocol processing module and the Ethernet network card driver and the 5G module driver of the 5G gateway; and the IP: port pool interface is used for uniformly managing IP: port resources so as to be used by a 5G gateway and related local area network end equipment.

The present disclosure relates to an apparatus for partial offloading of protocol processing. An apparatus for partially offloading processing from a user equipment (UE) to a cellular radio access network (RAN) node is disclosed. An apparatus for a UE includes at least one processor configured to perform transmission control protocol and internet protocol (TCP / IP) processing and to offload only a portion of the TCP / IP processing to a cellular RAN node while maintaining the TCP protocol running end-to-end between the UE and a remote host.

Apparatuses for partially offloading processing from a user equipment (UE) to a cellular Radio Access Network (RAN) node are disclosed. An apparatus for a UE includes at least one processor configured to perform Transmission Control Protocol and Internet Protocol (TCP / IP) processing and offload only a portion of the TCP / IP processing to a cellular RAN node while maintaining TCP protocols running end-to-end between the UE and a remote host.

The invention discloses a storage logic optimization method for a storage-intensive chip, which is applied to the field of digital back-end design of an integrated circuit, and aims to solve the problems of too many SRAMs (Static Random Access Memory), unreasonable SRAM distribution and relatively strong relevance in the traditional design. The problems of difficulty in time sequence convergence, shortage of winding resources, low design efficiency, more iteration times and the like caused by physical separation between the SRAM and a standard unit are solved; the method comprises the following steps: firstly, carrying out SRAM merging analysis based on time sequence and area constraint, and analyzing the feasibility of merging a plurality of small-capacity SRAMs into a large-capacity SRAM according to the time sequence margin; then, executing the combination of the SRAMs, and generating a combined SRAM macro cell; then, a storage logic group IP is constructed, the merged SRAM macro cell and a part of the IP having a strong logic connection relationship with the merged SRAM macro cell are processed, fine routing and time sequence optimization are carried out in the IP, and module-level time sequence sign-off is realized; and finally, outputting the storage logic group IP as a hardcore module, and integrating the storage logic group IP into a top-layer chip design.

The invention relates to a fast address readout circuit and a readout method, comprising a plurality of groups of channels, each group of channels having the same circuit connection structure; each group of channels is integrated with a control latch and a pull-up and pull-down unit, wherein the pull-up and pull-down units are configured in different ways, and a channel hit signal of each group of channels is transmitted to a lower-level encoding circuit as a chip select signal of the group after operation, and the lower-level encoding circuit transmits the chip select signal step by step in the same way; each group of channels is provided with a three-state buffer as a control switch, and by integrating a control latch and a pull-up and pull-down unit in the channel to directly read the value, the address transmission delay is significantly reduced, the address readout speed is accelerated, and the readout circuit is integrated inside the channel and processed as a standard module or IP, which is conducive to module circuit multiplexing and easy to expand a chip array; the pull-up and pull-down units are provided in the channel to quickly read out the low-order address, and the high-order address is obtained by combining a hierarchical address encoding scheme, thereby ensuring the power consumption requirement.