3 results about "Ip processing" patented technology

Techniques for host devices to offload iSCSI and NVMe / TCP data plane processing for data plane traffic to a NIC, and for the NIC to perform the data plane traffic processing in hardware. Traditionally, network protocol stacks have been implemented within the kernel of an operating system of a computing device. In light of this, iSCSI and NVMe / TCP user space applications running on host devices interact with a kernel of an operating system using system calls in order to send network traffic. However, the system calls, TCP / IP processing, and data copying required when communicating via the kernel increases CPU utilization as well as I / O latency. Techniques described herein include configuring the host device to enable kernel bypass for data path traffic for iSCSI and NVMe / TCP user space applications, and a NIC may include hardware configured to perform the iSCSI and NVMe / TCP processing for iSCSI and NVMe / TCP connections.

The present disclosure relates to an apparatus for partial offloading of protocol processing. An apparatus for partially offloading processing from a user equipment (UE) to a cellular radio access network (RAN) node is disclosed. An apparatus for a UE includes at least one processor configured to perform transmission control protocol and internet protocol (TCP / IP) processing and to offload only a portion of the TCP / IP processing to a cellular RAN node while maintaining the TCP protocol running end-to-end between the UE and a remote host.

The invention discloses a storage logic optimization method for a storage-intensive chip, which is applied to the field of digital back-end design of an integrated circuit, and aims to solve the problems of too many SRAMs (Static Random Access Memory), unreasonable SRAM distribution and relatively strong relevance in the traditional design. The problems of difficulty in time sequence convergence, shortage of winding resources, low design efficiency, more iteration times and the like caused by physical separation between the SRAM and a standard unit are solved; the method comprises the following steps: firstly, carrying out SRAM merging analysis based on time sequence and area constraint, and analyzing the feasibility of merging a plurality of small-capacity SRAMs into a large-capacity SRAM according to the time sequence margin; then, executing the combination of the SRAMs, and generating a combined SRAM macro cell; then, a storage logic group IP is constructed, the merged SRAM macro cell and a part of the IP having a strong logic connection relationship with the merged SRAM macro cell are processed, fine routing and time sequence optimization are carried out in the IP, and module-level time sequence sign-off is realized; and finally, outputting the storage logic group IP as a hardcore module, and integrating the storage logic group IP into a top-layer chip design.