Shared cache system applied to real-time network terminal chip

Abstract

The invention discloses a shared cache system applied to a real-time network terminal chip. The shared cache system comprises queue management, enqueue scheduling control, dequeue scheduling control, write bus control, read bus control, a data cache, a register module, an RXFIFO module and a TXFIFO module. According to the cache allocation strategy, the variable-length data is stored by using the fixed-length unit. The user can customize and configure the private space, the residual space is the shared space, and the storage utilization rate is high. The shared cache is mainly used for storing data packets sent by an external application layer through a host interface. And storing the received data packet, extracting frame information according to a network flow protocol, and directly discarding frames which do not meet the protocol. The shared cache is provided with a dynamic cache structure, the state of each queue can be updated in real time, frame loss is prevented, and the data stream processing capacity is improved. And meanwhile, complex hybrid scheduling of a real-time network is met. The whole shared cache is subjected to anti-radiation reinforcement, the scene requirement of space navigation application is met, and high reliability is achieved.

Description

Technical Field

[0001] The invention relates to a shared cache system applied to a real-time network terminal chip, belonging to the technical field of chips. Background Art

[0002] With the rapid development of communication technology, the application of real-time Ethernet technology has become more mature, and the research on shared cache has also come in succession. However, there are still some problems with the existing shared cache research. For example, the static cache structure is not flexible, the FIFO queue head buffer occupies more on-chip cache space, and has low storage utilization and weak reliability. Therefore, designing a shared cache with a dynamic cache structure, high storage utilization and high reliability has become a new trend. Summary of the invention

[0003] In order to solve the above problems, the present invention provides a shared cache system applied to a real-time network terminal chip, which is used to realize shared cache of data and meet the complex hybrid scheduling and high reliability of the real-time network.

[0004] In order to achieve the above object, the present invention provides the following technical solutions:

[0005] A shared cache system applied to a real-time network terminal chip, comprising: a queue management module, an entry scheduling control module, an exit scheduling control module, a write bus control module, a read bus control module, a shared cache, a register module, an RX_FIFO and a TX_FIFO;

[0006] The queue management module is used to implement the allocation and release of shared cache;

[0007] The queue scheduling control module is used to control the logical and physical queueing of data frames to achieve coordinated operation of each module; the data frame information sent by the upper level module is sent to the queue scheduling control module through RX_FIFO;

[0008] The dequeue scheduling control module reads and parses the data frame information that needs to be dequeued in TX_FIFO, and controls the logical dequeue and physical dequeue of the data frame;

[0009] The write bus control module moves the queued data frame from the upper level module to the shared cache according to the queued scheduling instruction provided by the queued scheduling control module;

[0010] The read bus control moves the dequeued data frame from the shared cache to the designated next-level module according to the dequeued scheduling instruction provided by the dequeued scheduling control module;

[0011] The register module implements the status register and cache configuration table of the shared cache, which can be accessed by both the embedded processor and the host, and has address mapping on the embedded processor AHB bus and the host AHB bus.

[0012] Furthermore, the shared cache is used to store data frames sent from the external application layer through the host interface. After the data frames are added with a UDP header, an IP header, and a MAC header to form a complete MAC frame, they are stored in the shared cache according to the VL_ID.

[0013] Furthermore, the shared cache is managed as one cache unit of 64 bytes, which is recorded as one buffer. The shared cache has a total of 2048 cache units, and the shared cache supports 256 virtual queues.

[0014] Furthermore, the shared cache workflow is:

[0015] RX_FIFO receives the data frame information sent by the superior, and then enters the queue scheduling control module to perform corresponding analysis on the data frame information;

[0016] The queue scheduling control module determines whether the data frame can be queued according to the frame information and the capacity information of the cache space at this time; if it can be queued, the queue management module is informed of the frame information and the cache address assigned to the data frame by the queue management module is received; when the queue scheduling module receives the cache address, the data frame is moved from the upper-level module to the corresponding position of the shared cache through the write bus control module;

[0017] The dequeue scheduling control module reads the data frame information that needs to be dequeued in the TX_FIFO module, informs the queue management module of the frame information, and receives the cache address in the shared cache allocated by the queue management module for the data frame; the cache address and data frame information are passed to the read bus control module, and the read bus control module moves the data frame from the shared cache to the next level module through the bus.

[0018] Furthermore, the register module stores the buffer configuration table information of each data frame sending port; the buffer configuration table information includes: MAX_BUFF_NUM and MIN_BUFF_NUM, which respectively represent the maximum and minimum number of buffer blocks occupied by this port.

[0019] Further, the queue management module includes: a RAM initialization module, an enqueue controller, a dequeue controller, a BD_RAM, a BD_RAM ​​multiplexer, a queue information RAM, a queue information RAM multiplexer and an idle buffer management module;

[0020] RAM initialization module: responsible for power-on initialization of BD_RAM ​​and queue information RAM;

[0021] Enqueue controller: responsible for the overall scheduling of enqueue frame buffer allocation and logical enqueue and communication with the interface scheduling module;

[0022] Dequeue controller: responsible for the overall scheduling of dequeue frame buffer query and logical dequeue and communication with the interface scheduling module;

[0023] BD_RAM: BD_RAM ​​stores the descriptor of each buffer;

[0024] BD_RAM ​​multiplexer: responsible for coordinating the reading and writing of BD_RAM ​​during enqueue and dequeue operations;

[0025] Queue Information RAM: The queue information RAM stores the information of each virtual output queue;

[0026] Queue information RAM multiplexer: responsible for coordinating the reading and writing of queue information RAM during enqueue and dequeue operations;

[0027] Idle Buffer Management Module: responsible for modifying the head and tail addresses of the idle Buffer queue, and recording the usage and occupied quantity of the idle Buffer.

[0028] Furthermore, the queue management module's queue entry workflow is specifically as follows:

[0029] (1) When the enqueue controller receives the frame enqueue request and frame information from the enqueue scheduling control module, the BD_RAM ​​multiplexer stores the frame information in the BD_RAM ​​and starts working;

[0030] (2) The queue controller queries the corresponding virtual output queue information, and the queue information RAM multiplexer stores the head address and tail address of the queue to the queue information RAM;

[0031] (3) The queue controller calculates the number of buffers required for the queued frame;

[0032] (4) The queue controller takes out the first free buffer according to the free buffer queue head pointer of the free buffer management module; submits the buffer address to the queue scheduling control module, modifies the descriptor of the first free buffer, and records the next hop address of the buffer;

[0033] (5) If the queued frame still needs a cache address, take the Buffer block corresponding to the next node address of the Buffer recorded in step (4) and repeat step (4);

[0034] (6) When the number of cache fragments allocated by the enqueue controller meets the number of enqueued frames, the next node address of the buffer block at the end of the original queue is modified to point to the first buffer block of the new enqueued frame; at the same time, the head pointer of the free buffer queue is modified to remove the allocated buffer blocks;

[0035] (7) The enqueue controller modifies the contents of the corresponding queue information RAM, including the tail pointer and the new queue length.

[0036] Furthermore, the dequeueing workflow of the queue management module is specifically as follows:

[0037] (1) When the dequeue controller receives the frame dequeue request and frame information sent by the dequeue scheduling control module, it stores the frame information and starts working;

[0038] (2) The dequeue controller extracts the queue information of the corresponding queue from the queue information RAM, including the queue head pointer, the head frame length, the number of queue buffers, and the queue tail pointer, and stores this information for subsequent work;

[0039] (3) The dequeue controller determines whether the queue is empty. If it is empty, the dequeue fails and the read failure signal will be pulled high; if it is not empty, it goes to step (4);

[0040] (4) The dequeue controller calculates the number of buffers shared by the head frame of the queue based on the head frame length of the queue;

[0041] (5) According to the dequeuing process with the minimum storage limit, the idle buffer management module calculates the change in the size of the shared area after the frame is dequeued;

[0042] (6) The dequeue controller cyclically outputs the fragment cache address of the frame. The cache address output operation varies according to the fragment location. The new queue head pointer register will store the next node address corresponding to the dequeue fragment.

[0043] (7) The dequeue controller updates the queue information RAM and reads the first buffer descriptor of the queue in BD_RAM ​​with the new queue head pointer as the address. The frame length recorded in the first buffer descriptor is used as the head frame length of the new queue, and the number of buffer descriptors in the queue is the number of original buffer descriptors minus the number of output buffer descriptors. The dequeue operation will not change the queue tail pointer. At this point, the dequeue operation ends, and the data frame is logically dequeued by changing the queue head pointer. The released idle buffer will be recycled by the idle buffer descriptor module after the bus is moved.

[0044] The beneficial effects of the present invention compared with the prior art are:

[0045] 1. The present invention solves the problem of poor flexibility of static cache structure in current research. The present invention adopts a flexible dynamic cache structure, which can effectively save storage and has high storage utilization rate;

[0046] 2. The shared cache of the present invention can update the status of each queue in real time, prevent frame loss, and improve the data flow processing capability;

[0047] 3. The shared cache of the present invention meets the requirements of complex hybrid scheduling of real-time networks;

[0048] 4. The present invention meets the scenario requirements of aerospace applications by performing radiation-resistant reinforcement on the entire shared cache, has high reliability, and has a wide range of application scenarios;

[0049] 5. The present invention has good versatility and can be extended to the application of shared cache in similar fields. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 The overall block diagram of a shared cache system applied to a real-time network terminal chip of the present invention;

[0051] Figure 2 It is an overall block diagram of the queue management module in the present invention;

[0052] Figure 3 It is the simulation result of the embodiment of the present invention. DETAILED DESCRIPTION

[0053] Hereinafter, embodiments of the present invention are more fully described with reference to the accompanying drawings. Embodiments of the present invention are shown in the accompanying drawings, however, embodiments of the present invention can be implemented in many different forms and should not be interpreted as being limited to the embodiments listed here. On the contrary, the following exemplary embodiments can make this disclosure thorough and fully convey the scope of the present invention to those skilled in the art, and detailed descriptions of known functions and structures will be omitted to avoid blurring the main issues of the embodiments.

[0054] The technical solution of the present invention is further described below with reference to the accompanying drawings and through specific implementation methods.

[0055] 1. The shared cache of the present invention has a flexible dynamic cache structure, supports out-of-order scheduling of frames, can update the status of each queue in real time, prevents frame loss, and improves the ability of data flow processing.

[0056] 2. In order to improve storage utilization, the present invention has made the following designs:

[0057] (1) The present invention simplifies the data information transmitted by the receiving FIFO queue head and the sending FIFO queue head, reduces the FIFO size, and improves storage utilization.

[0058] (2) The data cache of the present invention stores the accelerated data frames into queues. The data cache has a total of 256 queues with a capacity of 128KB. Each port corresponds to a queue, and the capacity of each queue is configured by two parameters in the configuration table: MIN_BUFF_NUM and MAX_BUFF_NUM. MAX_BUFF_NUM is configured as the maximum, and MIN_BUFF_NUM is set to the minimum space (private space) as required. This table is configured by comprehensively considering the flow rate of each port, frame length and other information, effectively saving resources, avoiding waste of storage space, and improving storage utilization.

[0059] 3. Furthermore, in order to prevent RAM resources from being affected by SEU and improve the reliability of the system. All RAMs in the present invention are subjected to error detection and correction (EDAC), and a one-check-two error correction coding method is adopted. The specific coding scheme is Hamming code, and (N, M)-bit Hamming code is used on the data bus of N-bit RAM. A RAM with a bit width of N and a RAM with a bit width of M are completely equivalent in logical function. When a flip error occurs, the error correction code can effectively detect and correct these errors. This method can detect two errors and correct one error.

[0060] Figure 1 The overall block diagram of a shared cache system applied to a real-time network terminal chip of the present invention comprises: a queue management module, an entry scheduling control module, an exit scheduling control module, a write bus control module, a read bus control module, a shared cache, a register module, an RX_FIFO and a TX_FIFO;

[0061] The queue management module is used to implement the allocation and release of shared cache;

[0062] The queue scheduling control module is used to control the logical and physical queueing of data frames to achieve coordinated operation of each module; the data frame information sent by the upper level module is sent to the queue scheduling control module through RX_FIFO;

[0063] The dequeue scheduling control module reads and parses the data frame information that needs to be dequeued in TX_FIFO, and controls the logical dequeue and physical dequeue of the data frame;

[0064] The write bus control module moves the queued data frame from the upper level module to the shared cache according to the queued scheduling instruction provided by the queued scheduling control module;

[0065] The read bus control moves the dequeued data frame from the shared cache to the designated next-level module according to the dequeued scheduling instruction provided by the dequeued scheduling control module;

[0066] The register module implements the status register and cache configuration table of the shared cache, which can be accessed by both the embedded processor and the host, and has address mapping on the embedded processor AHB bus and the host AHB bus.

[0067] refer to Figure 1 The shared cache is used to store data frames sent by the external application layer through the host interface. After the data frame is formed into a complete MAC frame by adding a UDP header, an IP header, and a MAC header, it is stored in the shared cache according to the VL_ID.

[0068] The shared cache is managed as a 64-byte cache unit, called a buffer. This shared cache is designed as 128KB, with a total of 2048 cache units, and the shared cache supports 256 virtual queues.

[0069] The shared cache workflow is:

[0070] RX_FIFO receives the data frame information sent by the superior, and then enters the queue scheduling control module to perform corresponding analysis on the data frame information; the queue scheduling control module determines whether the data frame can be queued according to the frame information and the capacity information of the cache space at this time; if it can be queued, the frame information is notified to the queue management module, and the cache address assigned to the data frame by the queue management module is received; when the queue scheduling module receives the cache address, the data frame is moved from the upper-level module to the corresponding position of the shared cache through the write bus control module; the dequeue scheduling control module reads the data frame information that needs to be dequeued in the TX_FIFO module, notifies the queue management module of the frame information, and receives the cache address in the shared cache assigned to the data frame by the queue management module; the cache address and data frame information are passed to the read bus control module, and the read bus control module moves the data frame from the shared cache to the next-level module through the bus.

[0071] The register module stores the buffer configuration table information of each data frame sending port; the buffer configuration table information includes: MAX_BUFF_NUM and MIN_BUFF_NUM, which respectively represent the maximum and minimum buffer block numbers occupied by this port.

[0072] The present invention performs EDAC processing on all internal storage RAMs, meets SEU requirements, and improves system reliability.

[0073] Figure 2 The overall block diagram of the queue management module in the present invention. The queue management module includes: a RAM initialization module, an enqueue controller, a dequeue controller, a BD_RAM, a BD_RAM ​​multiplexer, a queue information RAM, a queue information RAM multiplexer and an idle buffer management module;

[0074] RAM initialization module: responsible for power-on initialization of BD_RAM ​​and queue information RAM;

[0075] Enqueue controller: responsible for the overall scheduling of enqueue frame buffer allocation and logical enqueue and communication with the interface scheduling module;

[0076] Dequeue controller: responsible for the overall scheduling of dequeue frame buffer query and logical dequeue and communication with the interface scheduling module;

[0077] BD_RAM: BD_RAM ​​stores the descriptor of each buffer;

[0078] BD_RAM ​​multiplexer: responsible for coordinating the reading and writing of BD_RAM ​​during enqueue and dequeue operations;

[0079] Queue Information RAM: The queue information RAM stores the information of each virtual output queue;

[0080] Queue information RAM multiplexer: responsible for coordinating the reading and writing of queue information RAM during enqueue and dequeue operations;

[0081] Idle Buffer Management Module: responsible for modifying the head and tail addresses of the idle Buffer queue, and recording the usage and occupied quantity of the idle Buffer.

[0082] refer to Figure 2 The queue management module implements the allocation and release of shared cache and controls the logical enqueue and dequeue of data frames. The workflow of the queue management module is as follows:

[0083] 1. Team entry workflow:

[0084] (1) When the enqueue controller receives the frame enqueue request and frame information from the enqueue scheduling control module, the BD_RAM ​​multiplexer stores the frame information in the BD_RAM ​​and starts working;

[0085] (2) The queue controller queries the corresponding virtual output queue information, and the queue information RAM multiplexer stores the head address and tail address of the queue to the queue information RAM;

[0086] (3) The queue controller calculates the number of buffers required for the queued frame;

[0087] (4) The queue controller takes out the first free buffer according to the free buffer queue head pointer of the free buffer management module; submits the buffer address to the queue scheduling control module, modifies the descriptor of the first free buffer, and records the next hop address of the buffer;

[0088] (5) If the queued frame still needs a cache address, take the Buffer block corresponding to the next node address of the Buffer recorded in step (4) and repeat step (4);

[0089] (6) When the number of cache fragments allocated by the enqueue controller meets the number of enqueued frames, the next node address of the buffer block at the end of the original queue is modified to point to the first buffer block of the new enqueued frame; at the same time, the head pointer of the free buffer queue is modified to remove the allocated buffer blocks;

[0090] (7) The enqueue controller modifies the contents of the corresponding queue information RAM, including the tail pointer and the new queue length.

[0091] 2. Departure workflow:

[0092] (1) When the dequeue controller receives the frame dequeue request and frame information sent by the dequeue scheduling control module, it stores the frame information and starts working;

[0093] (2) The dequeue controller extracts the queue information of the corresponding queue from the queue information RAM, including the queue head pointer, the head frame length, the number of queue buffers, and the queue tail pointer, and stores this information for subsequent work;

[0094] (3) The dequeue controller determines whether the queue is empty. If it is empty, the dequeue fails and the read failure signal will be pulled high; if it is not empty, it goes to step (4);

[0095] (4) The dequeue controller calculates the number of buffers shared by the head frame of the queue based on the head frame length of the queue;

[0096] (5) According to the dequeuing process with the minimum storage limit, the idle buffer management module calculates the change in the size of the shared area after the frame is dequeued;

[0097] (6) The dequeue controller cyclically outputs the fragment cache address of the frame. The cache address output operation varies according to the fragment location. The new queue head pointer register will store the next node address corresponding to the dequeue fragment.

[0098] (7) The dequeue controller updates the queue information RAM and reads the first buffer descriptor of the queue in BD_RAM ​​with the new queue head pointer as the address. The frame length recorded in the first buffer descriptor is used as the head frame length of the new queue, and the number of buffer descriptors in the queue is the number of original buffer descriptors minus the number of output buffer descriptors. The dequeue operation will not change the queue tail pointer. At this point, the dequeue operation ends, and the data frame is logically dequeued by changing the queue head pointer. The released idle buffer will be recycled by the idle buffer descriptor module after the bus is moved.

[0099] 3. Queue status indication function

[0100] A queue status indication function is specially added in queue management. The queue status indication module is a status bit table, and each output queue corresponds to one bit in it. "1" indicates that there are frames to be output in the queue, and "0" indicates that there are no frames to be output in the queue. When the number of queues after the queues scheduled by the output scheduling module are 0, the queue status indication will be set to 0. When the number of queues in the queue update module changes from 0 to 1, the queue status indication will be set to 1. The status of each queue is updated in real time, and it can be observed in real time whether each queue is idle.

[0101] Figure 3 It is a simulation result diagram of an embodiment of the present invention.

[0102] refer to Figure 3 , verifying the core function of the shared cache algorithm, and realizing the allocation and release of the shared cache through a highly reliable cache strategy. According to the simulation waveform, it can be seen that the present invention successfully moves the queued data frames from the UDPIP acceleration framing module to the shared cache, and at the same time moves the dequeued frames from the shared cache to the designated next-level module. Finally, the present invention completes a high-reliability real-time network terminal shared cache system with high storage utilization and dynamic cache structure.

[0103] Parts of the present invention that are not described in detail belong to common knowledge among those skilled in the art.

Claims

1. A shared cache system for a real-time network terminal chip, characterized in that include: Queue management module, queue scheduling control module, queue dispatching control module, write bus control module, read bus control module, shared cache, register module, RX_FIFO and TX_FIFO; The queue management module is used to implement the allocation and release of shared cache; The queue scheduling control module is used to control the logical and physical queueing of data frames to achieve coordinated operation of each module; the data frame information sent by the upper level module is sent to the queue scheduling control module through RX_FIFO; The dequeue scheduling control module reads and parses the data frame information that needs to be dequeued in TX_FIFO, and controls the logical dequeue and physical dequeue of the data frame; The write bus control module moves the queued data frame from the upper level module to the shared cache according to the queued scheduling instruction provided by the queued scheduling control module; The read bus control moves the dequeued data frame from the shared cache to the designated next-level module according to the dequeued scheduling instruction provided by the dequeued scheduling control module; The register module implements the status register and cache configuration table of the shared cache, which can be accessed by both the embedded processor and the host, and has address mapping on the embedded processor AHB bus and the host AHB bus.

2. The shared cache system for a real-time network terminal chip according to claim 1, characterized in that: The shared cache is used to store data frames sent from the external application layer through the host interface. After the data frame is formed into a complete MAC frame by adding a UDP header, an IP header, and a MAC header, it is stored in the shared cache according to the VL_ID.

3. The shared cache system for a real-time network terminal chip according to claim 1, characterized in that: The shared cache is managed as one cache unit of 64 bytes, recorded as one buffer. The shared cache has a total of 2048 cache units, and the shared cache supports 256 virtual queues.

4. The shared cache system for a real-time network terminal chip according to claim 1, characterized in that: The shared cache workflow is: RX_FIFO receives the data frame information sent by the superior, and then enters the queue scheduling control module to perform corresponding analysis on the data frame information; The queue scheduling control module determines whether the data frame can be queued according to the frame information and the capacity information of the cache space at this time; If it can be queued, the frame information is notified to the queue management module, and the cache address assigned by the queue management module to the data frame is received; When the queue scheduling module receives the cache address, it moves the data frame from the upper-level module to the corresponding position of the shared cache through the write bus control module; The dequeue scheduling control module reads the data frame information that needs to be dequeued in the TX_FIFO module, informs the queue management module of the frame information, and receives the cache address in the shared cache allocated by the queue management module for the data frame; the cache address and data frame information are passed to the read bus control module, and the read bus control module moves the data frame from the shared cache to the next level module through the bus.

5. The shared cache system for a real-time network terminal chip according to claim 1, characterized in that: The register module stores the buffer configuration table information of each data frame sending port; the buffer configuration table information includes: MAX_BUFF_NUM and MIN_BUFF_NUM, which respectively represent the maximum and minimum number of buffer blocks occupied by this port.

6. A shared cache system for a real-time network terminal chip according to claim 4, characterized in that: The queue management module includes: a RAM initialization module, an entry controller, a dequeue controller, a BD_RAM, a BD_RAM ​​multiplexer, a queue information RAM, a queue information RAM multiplexer and an idle buffer management module; RAM initialization module: responsible for power-on initialization of BD_RAM ​​and queue information RAM; Enqueue controller: responsible for the overall scheduling of enqueue frame buffer allocation and logical enqueue and communication with the interface scheduling module; Dequeue controller: responsible for the overall scheduling of dequeue frame buffer query and logical dequeue and communication with the interface scheduling module; BD_RAM: BD_RAM ​​stores the descriptor of each buffer; BD_RAM ​​multiplexer: responsible for coordinating the reading and writing of BD_RAM ​​during enqueue and dequeue operations; Queue Information RAM: The queue information RAM stores the information of each virtual output queue; Queue information RAM multiplexer: responsible for coordinating the reading and writing of queue information RAM during enqueue and dequeue operations; Idle Buffer Management Module: responsible for modifying the head and tail addresses of the idle Buffer queue, and recording the usage and occupied quantity of the idle Buffer.

7. A shared cache system for a real-time network terminal chip according to claim 6, characterized in that: The queue management module's queue entry workflow is specifically as follows: (1) When the enqueue controller receives the frame enqueue request and frame information from the enqueue scheduling control module, the BD_RAM ​​multiplexer stores the frame information in the BD_RAM ​​and starts working; (2) The queue controller queries the corresponding virtual output queue information, and the queue information RAM multiplexer stores the head address and tail address of the queue to the queue information RAM; (3) The queue controller calculates the number of buffers required for the queued frame; (4) The queue controller takes out the first free buffer according to the free buffer queue head pointer of the free buffer management module; Submit the cache address to the queue scheduling control module, modify the descriptor of the first free buffer, and record the next hop address of the buffer; (5) If the queued frame still needs a cache address, take the Buffer block corresponding to the next node address of the Buffer recorded in step (4) and repeat step (4); (6) When the number of cache fragments allocated by the enqueue controller meets the number of enqueued frames, the next node address of the buffer block at the end of the original queue is modified to point to the first buffer block of the new enqueued frame; at the same time, the head pointer of the free buffer queue is modified to remove the allocated buffer blocks; (7) The enqueue controller modifies the contents of the corresponding queue information RAM, including the tail pointer and the new queue length.

8. The shared cache system for a real-time network terminal chip according to claim 6, characterized in that: The dequeueing workflow of the queue management module is specifically as follows: (1) When the dequeue controller receives the frame dequeue request and frame information sent by the dequeue scheduling control module, it stores the frame information and starts working; (2) The dequeue controller extracts the queue information of the corresponding queue from the queue information RAM, including the queue head pointer, the head frame length, the number of queue buffers, and the queue tail pointer, and stores this information for subsequent work; (3) The dequeue controller determines whether the queue is empty. If it is empty, the dequeue fails and the read failure signal will be pulled high; if it is not empty, it goes to step (4); (4) The dequeue controller calculates the number of buffers shared by the head frame of the queue based on the head frame length of the queue; (5) According to the dequeuing process with the minimum storage limit, the idle buffer management module calculates the change in the size of the shared area after the frame is dequeued; (6) The dequeue controller cyclically outputs the fragment cache address of the frame. The cache address output operation varies according to the fragment location. The new queue head pointer register will store the next node address corresponding to the dequeue fragment. (7) The dequeue controller updates the queue information RAM and reads the first buffer descriptor of the queue in BD_RAM ​​with the new queue head pointer as the address. The frame length recorded in the first buffer descriptor is used as the head frame length of the new queue, and the number of buffer descriptors in the queue is the number of original buffer descriptors minus the number of output buffer descriptors. The dequeue operation will not change the queue tail pointer. At this point, the dequeue operation ends, and the data frame is logically dequeued by changing the queue head pointer. The released idle buffer will be recycled by the idle buffer descriptor module after the bus is moved.

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