Method and apparatus for refresh management of memory modules

Abstract

One embodiment sets forth an interface circuit configured to manage refresh command sequences that includes a system interface adapted to receive a refresh command from a memory controller, dock frequency detection circuitry configured to determine the timing for issuing staggered refresh commands to two or more memory devices coupled to the interface circuit based on the refresh command received from the memory controller. and at least two refresh command sequence outputs configured to generate the staggered refresh commands for the two or more memory devices

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is a continuation of the U.S. patent application having Ser. No. 11 / 828,181, filed on Jul. 25, 2007, which is a continuation-in-part of the U.S. patent application having Ser. No. 11 / 584,179, filed on Oct. 20, 2006, which is a continuation of the U.S. patent application having Ser. No. 11 / 524,811, filed on Sep. 20, 2006, which is a continuation-in-part of the United States patent application having Ser. No. 11 / 461,439, filed on Jul. 31, 2006. application Ser. No. 11 / 828,181 also claims the priority benefit of U.S. Provisional Patent Application No. 60 / 823,229, filed on Aug. 22, 2006. The subject matter the above related applications is hereby incorporated herein by reference. However, insofar as any definitions, information used for claim interpretation, etc. from the above parent application conflict with that set forth herein, such definitions, information, etc. in the present application should apply.BACKGROUND OF TH...

AI Technical Summary

Problems solved by technology

However, one issue associated with the action of refreshing more DRAM devices for each refresh operation in the higher capacity DRAM devices is that larger electrical currents may be drawn by the higher capacity DRAM devices for each refresh operation.

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