Prefetch mechanism for use in a system including a host connected to a plurality of memory modules via a serial memory interconnect

Abstract

A system includes a host coupled to a serially connected chain of memory modules. In one embodiment, the host includes a memory controller that may be configured to issue a memory read request for data stored within the memory modules. The memory controller may further request that data be prefetched from the memory modules by encoding prefetch information within the memory read request. The memory controller may also be configured to issue a memory write request to write data to the memory modules and to selectively request that one or more pages of memory within a given one of the memory modules remain open by encoding the prefetch information within the memory write request.

Description

[0001] This application claims the benefit of U.S. Provisional Application No. 60 / 470,078 filed May 13, 2003.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] This invention relates to computer system memory and, more particularly, to prefetching data in a serial memory subsystem topology. [0004] 2. Description of the Related Art [0005] Many computer systems employ a main system memory that may be configured dependent upon the needs of an end user. In such systems, a motherboard or system board may include a number of memory expansion sockets. One or more small circuit boards, referred to as memory modules, may be inserted into the sockets as needed to increase the memory capacity of the computer system. Each of the memory modules typically includes multiple memory devices that provide a given amount of memory capacity. The memory devices are usually implemented using some type of dynamic random access memory (DRAM). Some examples of DRAM types include synchronous ...

AI Technical Summary

Benefits of technology

The patent describes a system that includes a host and multiple memory modules connected in a series. The host sends a memory read request to the memory modules, which then preloads data from the modules into the host's memory. The preload information includes a request for data and information about which addresses to preload. The memory modules have a controller that manages access to the memory chips and a DRAM controller that generates memory read cycles. The host can also issue a memory write request with preload information to keep pages of memory open. The technical effect of this system is improved performance and efficiency by optimizing data preload and reducing latency.

Problems solved by technology

Although the operating speed of computer system processors continues to increase, the relative performance of the main system memory has not increased at the same rate.

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