Pixel circuit, driving method thereof, display panel and display device
A pixel circuit and drive control technology, applied in the field of display panels, display devices, and pixel circuits, can solve the problem of inconsistent brightness of the first frame, and achieve the effect of avoiding afterimage phenomenon, consistent brightness, and avoiding differences
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example 1
[0104] by Figure 4 Take the pixel circuit shown as an example, and the corresponding input and output timings are as follows Figure 11a shown. Specifically, choose the Figure 11a The four stages T1, T2, T3 and T4 in the input timing diagram shown.
[0105] In node initialization phase T1, Scan1=0, Scan2=1, Emit1=1, Emit2=0.
[0106] Since Scan1=0, the fifth switching transistor M5 is turned on to provide the signal of the reference signal terminal Vref to the first node N1, and the potential of the first node N1 is Vref. Since Emit2=0, the first switching transistor M1 is turned on to provide the signal of the first voltage terminal PVDD to the second node N2, the potential of the second node N2 is VDD, and the first node N1 and the second node N2 are initially reset. Since Scan2=1, the third switching transistor M3, the fourth switching transistor M4 and the sixth switching transistor M6 are turned off. Since Emit1=1, the second switching transistor M2 is turned off, ...
example 2
[0117] by Figure 5 and Figure 8 Take the pixel circuit shown as an example, and the corresponding input and output timings are as follows Figure 12 shown. Specifically, choose the Figure 12 The four stages T1, T2, T3 and T4 in the input timing diagram shown.
[0118] In node initialization phase T1, Scan1=0, Scan2=1, Emit1=Emit2=1.
[0119]Since Scan1=0, the fifth switch transistor M5 is turned on to provide the signal of the reference signal terminal Vref to the first node N1, and the potential of the first node N1 is Vref; the seventh switch transistor M7 is turned on to supply the signal of the first voltage terminal The signal of PVDD is provided to the second node N2, the potential of the second node N2 is VDD, the first node N1 and the second node N2 are initialized and reset, and the driving transistor M0 is turned on. Since Scan2=1, the third switching transistor M3, the fourth switching transistor M4 and the sixth switching transistor M6 are turned off. Sinc...
example 3
[0128] by Figure 6 , Figure 7 , Figure 9 and Figure 10 Take the pixel circuit shown as an example, and the corresponding input and output timings are as follows Figure 13 shown. Specifically, choose the Figure 13 The three stages T1, T2 and T3 in the input timing diagram are shown.
[0129] In node initialization phase T1, Scan1=0, Scan2=1, Emit1=Emit2=1.
[0130] Since Scan1=0, the fifth switch transistor M5 is turned on to provide the signal of the reference signal terminal Vref to the first node N1, and the potential of the first node N1 is Vref; the seventh switch transistor M7 is turned on to supply the signal of the first voltage terminal The signal of PVDD is provided to the second node N2, the potential of the second node N2 is VDD, the first node N1 and the second node N2 are initialized and reset, the eighth transistor is turned on and the signal of the reference signal terminal Vref is provided to the third node N3, The driving transistor M0 is turned o...
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