8 results about "Grid bias" patented technology

An electrolyteless fuel cell system includes an anode; a cathode; an electrical grid between the anode and cathode; an anode side grid bias electrode; a cathode side grid bias electrode; and an electrical grid power supply, wherein the electrical grid is biased negative with respect to the anode through the anode side grid bias electrode and the electrical grid power supply, or wherein the electrical grid is biased positive with respect to the cathode through the cathode side grid bias electrode and the electrical grid power supply. In electrolyteless electrolyzer mode steam is introduced to the cathode, wherein the electrical grid is biased positive with respect to the cathode through the cathode side grid bias electrode and the electrical grid power supply.

The invention relates to an innovative power amplifier (PA) circuit design aimed at enhancing efficiency and simplifying circuit complexity for modern wireless communication systems. This design employs a hybrid architecture that combines a main amplifier and an auxiliary amplifier, which work together to optimize performance across a broad range of output power levels. A key feature of the design is the use of a single gate bias voltage, applied to both amplifiers, eliminating the need for separate bias supplies and reducing overall circuit complexity. The amplification circuitry includes a main amplifier with a first transistor, an auxiliary amplifier with a second transistor, and a common gate bias supply. The transistors are fabricated either on a single wafer or separate wafers, with tailored threshold voltages to ensure optimal performance and efficient operation.

This invention discloses a method for stabilizing and correcting radio frequency power amplifiers based on modulator parasitic control, belonging to the field of radio frequency technology. The method includes: Step S1: collecting modulator output voltage, power amplifier power supply current, power amplifier power supply voltage, and gate bias voltage; Step S2: calculating parasitic response parameters using a recursive parameter algorithm and recording abnormal oscillation components; Step S3: calculating stability margin values ​​and identifying abnormal oscillation branches; Step S4: calculating the damping coefficient of the abnormal oscillation branches, constructing a digital compensator to perform a cyclic correction process, completing the cyclic correction process when the stability margin value of the abnormal oscillation branch exceeds a preset margin threshold. This invention, by collecting power amplifier power supply voltage and gate bias voltage, uses a recursive parameter algorithm to calculate parasitic response parameters in real time, and actively predicts and corrects parasitic oscillations. It has the advantage of verifying parasitic oscillations in the bias network and helps to quickly locate design defects in the bias network.

A power amplifier including a gate bias circuit that comprises a first power supply interface and a second power supply interface, a drain bias circuit, and a power transistor. A specific voltage difference exists between a first voltage signal received by an input end of the first power supply interface and a second voltage signal received by an input end of the second power supply interface. A gate of the power transistor is configured to receive a radio frequency signal carrying a plurality of signal slice symbols. When a first signal slice symbol carries valid data, the gate is coupled to an output end of the first power supply interface. When the first signal slice symbol carries no valid data or no radio frequency signal is received, the gate is coupled to an output end of the second power supply interface.

The application relates to a wideband high-efficiency rectifier circuit based on a GaN HEMT, which comprises an input matching network, a harmonic suppression network, a direct-current output circuit, a second harmonic suppression network, a current stabilizing circuit, a radio frequency junction gate field effect transistor, a gate matching network and a gate bias circuit; the input matching network is used for direct-current isolation processing of received signals; the harmonic suppression network is used for suppressing second and third harmonics, adjusting fundamental wave impedance and expanding the distribution interval of each harmonic impedance to realize wideband characteristics; the direct-current output circuit is used for converting input alternating-current power into direct-current power for output; the second harmonic suppression network is used for suppressing the second harmonic of the gate of the radio frequency junction gate field effect transistor; the current stabilizing circuit is used for preventing the whole circuit from oscillating; the gate matching network is used for impedance matching between the second harmonic suppression network and the ground end; and the gate bias circuit is used for providing direct-current bias voltage for the gate of the radio frequency junction gate field effect transistor.

The application discloses a dual-frequency power amplifier with band-pass filtering characteristics, wherein the power amplifier comprises an input matching network, a gate bias circuit, a stabilizing circuit, a transistor, a harmonic control network, a drain bias circuit and an output matching network; the input matching network adopts a matching circuit structure with band-stop filtering characteristics, aims to generate transmission zero points with high suppression between passbands, and provides good inter-band suppression; the output matching network adopts a dual-frequency structure with band-pass filtering characteristics, aims to realize matching in target frequency bands, and provides good out-of-band suppression; and good dual-frequency filtering effect is realized through cooperation of the input and the output. The application can realize good dual-frequency filtering effect, realize wider passband bandwidth at two frequencies than traditional design, and realize high-efficiency output in dual-frequency bands.

The application relates to an adjustable adaptive bias circuit for a power amplifier, which comprises a bias voltage generating circuit and a positive feedback voltage dividing circuit; the bias voltage generating circuit generates a bias voltage input to the positive feedback voltage dividing circuit, and the bias voltage input to the positive feedback voltage dividing circuit is adjusted through an adjustable current source in the bias voltage generating circuit; the positive feedback voltage dividing circuit forms a positive feedback mechanism through voltage division on a gate bias voltage Vcs input to the power amplifier, which automatically increases with the increase of input power, so that the power amplifier maintains high transconductance and gain at large power output, thereby inhibiting the gain compression phenomenon and realizing adaptive bias control. The circuit structure is simple, can realize real-time sensing of output power change and adaptive adjustment of the size of the bias voltage, dynamically enhances the bias voltage with the increase of the output power, thereby effectively offsets the gain compression effect, and maintains high and stable gain output in a wide power range.

The embodiment of the application provides a linear adjustable capacitive negative feedback amplification circuit and a bandwidth expansion method, and belongs to the technical field of integrated circuits. The circuit comprises: a differential input pair tube; a capacitive negative feedback network connected between the sources of the differential input pair tube, the network comprising a source MOS tube and a capacitor element working in a linear region, and the linear adjustment of the zero frequency is realized by adjusting the gate bias voltage of the source MOS tube; and a negative capacitance compensation network connected to the drain of the differential input pair tube, used for generating an equivalent negative capacitance to offset the load capacitance of the output node. The application also provides a bandwidth expansion method, which cooperatively improves the bandwidth through the double mechanisms of pole-zero cancellation and negative capacitance load cancellation. The application solves the problems that the bandwidth of an amplification circuit is limited and difficult to linearly adjust under a unipolar transistor process, realizes linear adjustment and multiplication of the bandwidth, and has the advantages of gain-bandwidth decoupling adjustment, strong process adaptability and the like.