160 results about "Grid bias" patented technology

A structure includes a level shifter, first and second variable voltage generators, and a programmable voltage generator. The level shifter includes low and high supply voltage nodes and two parallel branches, including multiple transistors, connected between the nodes. The programmable voltage generator generates and applies a high supply voltage (VH) to the high supply voltage node. VH is programmable to one of multiple possible VH levels. Based on the voltage level of VH, the first variable voltage generator generates and applies a low supply voltage (VL) to the low supply voltage node and the second variable voltage generator generates and applies a gate bias voltage (VGB) to gates of some transistors. By tracking VH and adjusting VL and VGB based on thereon, the voltage level shifter operates within the SOA at high VHs, remains operable at low VHs, and maintains operating speed at mid-level VHs.

The invention discloses a SiC MOSFET maximum surge current test and failure analysis method and device based on three-terminal resistance monitoring. The performance change of the device under the extreme stress is quickly evaluated by applying the stepping surge current and combining the online monitoring of the three-terminal resistor, so that the maximum single surge current bearing capacity and the failure mode of the device are judged. The method comprises the following specific steps: applying proper grid bias voltage to a SiC MOSFET to be tested, and setting parameters of a surge current generating circuit; and after the stepping single surge current is applied, measuring and recording three-terminal static resistance values of the gate-source terminal, the drain-source terminal and the gate-drain terminal. By monitoring the change of the resistance value, the maximum single surge current is determined, the failure mode of the device is judged, and the modes of open circuit, short circuit, electric leakage, burning and the like are determined. The method is easy and convenient to operate and low in cost, and reliability information of the SiC MOSFET can be rapidly provided under the condition that a high-precision instrument is not used.

The invention relates to the technical field of radio frequency integrated circuits, in particular to a harmonic suppression power amplifier combining a matching network and a feed network, which comprises a transistor, an input matching module, an output matching module, a stabilizing module and a bias module, the input matching module comprises a first parallel resonance unit, the first parallel resonance unit is used for second harmonic suppression, the output matching module comprises a series resonance unit and a second parallel resonance unit, the series resonance unit is used for resonating at a second harmonic frequency and performing low-impedance grounding on the second harmonic, and the second parallel resonance unit is used for resonating at a second harmonic frequency and performing low-impedance grounding on the second harmonic. The second parallel resonance unit is used for resonating at a third harmonic frequency and forms a high-impedance open circuit for the third harmonic, the output matching module is coupled to a drain electrode of the transistor, and the bias module comprises a grid bias sub-module and a drain bias sub-module. The grid bias sub-module is coupled to a connection node of the input matching module and the grid of the transistor, the drain bias sub-module is coupled to the output matching module, and the bias voltage of the transistor is jointly determined by the grid bias sub-module and the drain bias sub-module. The power amplifier has the effect of improving the efficiency level of the power amplifier while realizing harmonic suppression optimization.

The invention discloses a gain temperature compensation method and circuit for a Ku-band amplifier, and belongs to the technical field of semiconductor integrated circuits. A Ku wave band power amplifier is formed on the basis of a pHEMT amplification device. A grid temperature compensation bias network is adopted for grid bias of the pHEMT amplifier, and the gain of the amplifier is controlled to fluctuate along with the temperature. According to the fluctuation condition of the gain of the pHEMT amplifier along with the temperature, the resistance value of a temperature compensation resistor in the grid bias network is determined, and the grid bias voltage is divided through the grid temperature compensation resistor. As the resistance value of the thermistor changes along with the temperature, the direct-current voltage output by the grid bias network correspondingly changes along with the temperature, so that the gain is controlled. The problem that the gain of an existing PHEMT technology-based Ku band amplifier changes greatly along with the temperature change is solved, and the situation that the gain of the amplifier is out of tolerance along with the temperature change is avoided. The technical scheme provided by the invention is widely applied to various Ku wave band power amplifiers.

The invention relates to an ultra-wideband high-performance radio frequency power amplifier based on gate source nonlinearity. One end of an SMA input connecting line is connected with a radio frequency signal source; the other end of the SMA input connecting line is connected with the input end of the input matching circuit; the output end of the input matching circuit is connected with the input end of the gate-source nonlinear control circuit; the output end of the gate-source nonlinear control circuit is connected with the gate of the power amplifier tube; the gate bias circuit is connected in parallel between the output end of the input matching circuit and the input end of the gate-source nonlinear control circuit; the drain electrode of the power amplifier tube is connected with the input end of the tuning circuit; the output end of the tuning circuit is connected with the input end of the output fundamental wave and harmonic wave matching circuit; the drain biasing circuit is connected in parallel between the output end of the tuning circuit and the input end of the output fundamental wave and harmonic wave matching circuit; the output end of the output fundamental wave and harmonic wave matching circuit is connected with one end of the SMA output connecting line; and the other end of the SMA output connecting line is a radio frequency signal output end. According to the invention, the ultra-wideband / multi-octave high-performance power amplifier is designed.

The invention belongs to the technical field of integrated circuit design, and particularly relates to a double-gear GaN power tube grid bias control integrated circuit. The integrated circuit comprises a GaN power tube, a positive voltage power supply, a DC-DC negative voltage power supply, a negative voltage linear voltage stabilizing circuit, a 11-bit digital-to-analog converter, a gate driving buffer, a gate voltage operation control module, a gate voltage adjusting circuit, a current detection module, a temperature detection module and a 11-bit analog-to-digital converter. Aiming at the application of the GaN power tube in a radio frequency front-end transmitting channel, the invention provides a bias solution which is highly integrated and low in power consumption and aims at the GaN power tube technology, so that the number of off-chip elements is greatly reduced, and a power amplifier is enabled to work in a required optimal bias state no matter how voltage, temperature and other environmental parameters change.

The invention provides a voltage clamping circuit and a bidirectional level shifter comprising the same, and relates to the field of integrated circuit design. The circuit comprises a first phase inverter, a first transistor and a first diode, the first transistor is an NMOS, the input end of the first phase inverter is connected with an enable end, the power supply end is connected with a first power supply, the output end is connected with the grid electrode and the drain electrode of the first transistor, the source electrode of the first transistor is connected with a second power supply, and the drain electrode is used for outputting low level when the enable end outputs low level. And the anode of the first diode is connected with the substrate of the first transistor, and the cathode of the first diode is connected with a second power supply. By using the circuit of the NMOS transistor and the phase inverter, the stable grid bias voltage can be provided for the NMOS transmission tube, and the bias voltage change caused by power supply fluctuation, temperature change or process deviation can be reduced, so that the stability and the reliability of the circuit are improved; the first diode can avoid current consumption when the enable is turned off.

Apparatuses, systems, and methods are disclosed for chemically differentiated sensor arrays and methods of manufacturing and using the same. In one or more examples. An integrated circuit chip includes a chemically differentiated array of graphene field effect transistors with one or more wells configured to receive a volume of biological sample liquid comprising a plurality of different types of biological substances to be distinguished using electrical measurements of output signals of the graphene field effect transistors. At least one electrode is configured to apply a changing gate bias voltage (VGs) that increases and decreases within a predetermined range to the sample liquid and at least one electrode is configured to monitor measurement vectors including slopes of drain current measurements relative to the voltage measurements and differences in slope of the measurement vectors distinguish different biological substances in the sample liquid. Systems and methods utilize the integrated circuit chip.

Embodiments of the present disclosure include adaptive bias control of cascode drivers in envelope tracking power amplifier devices, systems, and methods. In some aspects, a wireless communication device is disclosed that includes a power amplifier. The power amplifier may include a driver stage configured to receive a variable voltage supply signal, and a power amplifier stage following the driver stage. In some embodiments, the driver stage includes a cascode gate bias circuit configured to receive a first signal that is based on the variable voltage supply signal; and a cascode amplifier stage comprising a first field effect transistor (FET) and a second FET in a stacked configuration. The cascode gate bias circuit may be further configured to adaptively convert the first signal into a bias signal for a gate of the first FET. The power amplifier stage may be configured to generate an amplified signal based on the intermediate output.

The invention discloses a single-power-supply ultra-wideband temperature compensation low-noise amplifier circuit, and belongs to the technical field of radio frequency microwaves. The circuit is mainly composed of a pre-stage low-noise amplifier module, an inter-stage temperature compensation equalization module and a post-stage driving amplifier module. The temperature compensation equalizer module generates differential voltage related to temperature through a three-stage gallium arsenide diode temperature sensing unit, outputs a control signal through an enhanced FET differential amplification circuit, drives a voltage-controlled attenuation equalizer to dynamically adjust the attenuation amount of a radio frequency signal, and achieves gain stability in a frequency band. Through the collaborative design of a blocking capacitor and a divider resistor, the grid bias of an FET switch is strictly limited in a transconductance linear adjustment interval, and the interval covers 80% of the effective range of the threshold voltage of a gallium arsenide FET tube. The circuit is powered by a single power supply + 5V, stable work of each module is ensured through active bias and a power supply filter network, and the circuit is suitable for extreme temperature environments such as high-frequency communication and radar.

The invention relates to a Doherty power amplifier with a reconfigurable mode, which belongs to the technical field of microwave circuits and comprises a power divider, a carrier power amplifier module, a peak power amplifier module and a combining impedance. According to the Doherty power amplifier, under the condition that a matching circuit is not changed, by exchanging the grid bias of the two transistors, the Doherty power amplifier achieves the function that the working frequency band is reconfigurable, and therefore the amplifier can work at multiple frequency bands. In addition, an output matching circuit of the amplifier is changed by utilizing a PIN switch SMP1345-079, so that the working frequency band bandwidth of the amplifier is increased. The power amplifier disclosed by the invention works in two modes, the working frequency bands of the first mode are 2.5-2.9 GHz and 3.3-3.7 GHz, and the working frequency band of the second mode is 2.8-3.4 GHz. According to the Doherty power amplifier, the reciprocal gate is adopted to be biased between two modes of different frequency bands to be switched, the proposed Doherty power amplifier can cover various frequency bands of 5G of operators, and therefore a promising solution is provided for 5G in broadband services.

The invention provides a millimeter wave radio frequency power amplifier and a millimeter wave radio frequency transceiver, in the amplifier, an input differential signal is connected to grid electrodes of an amplification tube pair transistor and an auxiliary tube pair transistor through an auxiliary tube pair transistor blocking capacitor and an amplification tube pair transistor blocking capacitor; source electrodes of the auxiliary tube pair tube and the amplifier tube pair tube are grounded. The first amplifier tube is connected with the drain electrode of the first common-gate tube and the source electrode of the first auxiliary tube; the second amplifier tube is connected with the drain electrode of the second common-gate tube and the source electrode of the second auxiliary tube; grid electrodes of the common-gate pair transistors are connected; common-gate tube grid bias voltage is connected to grids of the common-gate tube geminate transistors through the bias resistor, and the other end of the grounding capacitor is connected to the grids of the common-gate tube geminate transistors; the drain electrode of the common-gate pair transistor is connected to the shunt capacitor and the main coil inductor of the output balun, and the secondary coil inductor of the output balun is connected with a single-ended output signal. According to the radio frequency power amplifier, OP1dB of the radio frequency power amplifier can be improved under the condition that the working voltage of the power amplifier is not increased.

The invention provides a maladjustment self-calibration method. The maladjustment self-calibration method comprises the following steps: 1) short-circuiting input signal ends VINP and VINN of an amplifying circuit to a common-mode voltage VCOM; 2) detecting an output signal difference value of the signal output ends VOUTP and VOUTN of the amplification circuit through a comparator, wherein the difference value is an offset error and generates high and low level signals; 3) accumulating the high and low level signals in a preset period through a counter to obtain an error value, converting the error value into a digital control signal through a register, and returning the digital control signal to the amplification circuit; and 4) the amplification circuit adjusts the input end to compensate the grid bias voltage of the CMOS circuit according to the digital control signal, and adjusts the offset error value to the reduction direction. The invention further provides a high-speed amplification circuit which uses the offset calibration method.

A radio frequency power amplifier includes a power amplification transistor and a gate bias circuit. The gate bias circuit includes a VHb terminal connected to a high voltage power supply for bias, a VLb terminal connected to a low voltage power supply for bias, an enable terminal that receives an enable signal, an enable transistor and a voltage dividing resistor that are connected in series and connected between the VHb terminal and the VLb terminal, a driver that outputs a voltage to a control terminal of the enable transistor, and a gate bias output terminal that outputs, as a gate bias voltage, a divided voltage generated by the voltage dividing resistor. When an OFF signal is received as the enable signal, the driver causes the enable transistor to operate in a first operating area that is not a cutoff region.

Bias circuits for CMOS power amplifiers are provided. The bias circuit includes a feedback module, a first bias module, and a second bias module. The feedback module has a first input connected to a output common mode voltage, a second input connected to a reference voltage, and an output connected to gates of main amplification transistors in a first differential amplification module; based on a difference between the output common mode voltage and the reference voltage, the feedback module adjusts gate voltages of main amplification transistors until the output common mode voltage is equal to the reference voltage; the first bias module provides bias voltages for the first differential amplification module; the second bias module provides bias voltages for a second differential amplification module. The present disclosure adopts direct negative feedback and cascoded current mirrors, which realize accurate DC gate bias and accurate control of the output common mode voltage.

The invention relates to the technical field of integrated circuit design, and particularly discloses a class-AB output stage biasing circuit and method changing along with load current, the circuit comprises an IBOOSTP sink current source, the two ends of the IBOOSTP sink current source are connected in parallel with the source drain electrode of a PMOS tube connected with a power supply in a grid biasing circuit for determining the static current of an output NMOS tube of class-AB, and the IBOOSTP sink current source is connected with the grid biasing circuit. The magnitude of the current is in proportion to the current flowing through the output PMOS tube of the class-AB; two ends of the IBOOSTN pull current source are connected in parallel with a source and a drain of an NMOS (N-channel metal oxide semiconductor) tube connected to the ground in the grid bias circuit for determining the static current of the output PMOS tube of the class-AB, and the size of the IBOOSTN pull current source is proportional to the current flowing through the output NMOS tube of the class-AB. According to the invention, the size of the IBOOSTP sink current source and the size of the IBOOSTN pull current source are respectively proportional to the current flowing through the output PMOS tube and the output NMOS tube of the class-AB, so that the overall gain of the class-AB is increased under the large load current, and the output error is reduced.

The present invention provides a broadband class F power amplifier based on an ultra-compact output network and a design method, including an input matching circuit, a gate bias circuit, a transistor, a drain bias circuit, and an output matching circuit. The input end of the input matching network is connected to the power input end, the output end is connected to the gate of the transistor, the gate bias circuit is connected in parallel with the gate, the drain of the transistor is connected to the output matching circuit, the drain bias circuit is connected in parallel with the drain, and the output end of the output matching circuit is used as the power output. Compared with the prior art, the ultra-compact broadband class F power amplifier implemented by the present invention using a single-section microstrip line achieves the same broadband and high efficiency, and realizes a compact output network. The circuit structure is simple, easy to implement, reduces costs, and has good application prospects.

An RF circuit is disclosed that may include a driver stage. The driver stage may include a gate bias circuit configured to receive a variable voltage supply signal; and an amplifier stage comprising a FET, wherein the gate bias circuit is configured to adaptively convert the variable voltage supply signal into a bias signal. The RF circuit may further include a circuit component configured to combine the bias signal and a radio frequency input signal to generate a combined signal, and wherein the amplifier stage is configured to receive the combined signal at a gate of the FET and to produce an intermediate output, and wherein the gate bias circuit is configured to generate the bias signal such that the bias signal increases as the variable voltage supply signal decreases to compensate for a tendency of a current through the FET to decrease as the variable voltage supply signal decreases.

The application discloses a Doherty power amplifier integrated circuit and a preparation method and device thereof, and relates to the technical field of communication.The Doherty power amplifier integrated circuit comprises a power divider, a main power amplifier, a peak power amplifier, a gate bias voltage regulator and a combiner; a first signal output end of the power divider is connected with a signal input end of the main power amplifier, and a signal output end of the main power amplifier is connected with a first signal input end of the combiner; a second signal output end of the power divider is connected with a signal input end of the peak power amplifier, and a signal output end of the peak power amplifier is connected with a second signal input end of the combiner; pinch-off voltage of the peak power amplifier is different from that of the main power amplifier, and an output end of the gate bias voltage regulator is connected with a gate of the main power amplifier and a gate of the peak power amplifier respectively.The Doherty power amplifier integrated circuit can simplify a power supply system.

The invention discloses a ka wave band high-efficiency power amplifier based on a GaAs technology. A circuit comprises an input stage tube core, a driving stage tube core, an output stage tube core, an output stage second harmonic suppression network, an inter-stage matching network, an output matching network, a grid electrode biasing circuit, a drain electrode biasing circuit and a stabilizing resistor. The input matching network adopts a T-shaped matching network structure, and the inter-stage matching circuit adopts a matching network combining an LC series structure and a T-shaped structure, so that the working bandwidth of the circuit is further improved, and the area of the power amplifier is reduced; the output efficiency of the whole power amplifier is improved by introducing a second harmonic suppression network at the output end by adopting a second harmonic suppression technology. According to the invention, based on the 0.15 [mu] m GaAs pHEMT technology, a three-stage cascade amplification and power distribution synthesis structure is adopted to realize that the output saturation power is greater than or equal to 29.5 dBm and the power additional efficiency is greater than or equal to 34% in the working frequency band of 34-38GHz, and the power amplifier has the advantages of high stability, high power additional efficiency, high saturation output power, wide working frequency band and the like.

A voltage gate driver for a semiconductor-based transistor, the voltage gate driver comprising: a voltage generator circuit arranged to receive a drive voltage, the voltage generator circuit including a capacitor connected in series with a Zener diode, wherein a cathode of the Zener diode is arranged to be connected to a gate of the semiconductor-based transistor; a bias current circuit connected in parallel across the capacitor, wherein the bias current circuit includes a switch and is arranged to provide a bias current to the cathode of the Zener diode based on a state of the switch, wherein the bias current circuit is arranged to provide the bias current to the cathode of the Zener diode when the switch is in a closed state and is arranged to prevent the provision of the bias current to the cathode of the Zener diode when the switch is in an open state.

The invention belongs to the field of integrated circuits, and relates to a distributed amplifier, in particular to a distributed amplifier based on a GaN process, which comprises N stages of traveling wave tube networks and a grid power supply bias network, the N stages of traveling wave tube networks comprise cascaded N traveling wave tube networks, and the Nth stage of traveling wave tube network outputs radio frequency signals; and the grid power supply bias network is used for providing bias voltage for the N-stage traveling wave tube network and is connected with the Nth-stage traveling wave tube network. Compared with a traditional distributed amplifier, according to the grid power supply bias network, a traditional grid absorption resistor is not connected with grid bias power supply voltage, the grid absorption resistor is divided into two resistors, and a filter capacitor is connected to the ground at an intermediate node of the two resistors; the tail end of the resistor is connected with grid bias power supply voltage, so that the bandwidth is expanded, and the stability of the circuit is improved; in addition, an input matching network is added to the input end of the amplifier, and input standing waves are optimized.

The application discloses an amplifier, a radio frequency chip and an electronic device. The amplifier comprises a field effect tube, a drain matching circuit, a gate matching circuit, a gate bias circuit and a source matching circuit. The field effect tube comprises a drain, a gate and a source, and is used for signal amplification. The first end of the drain matching circuit is connected with the drain of the field effect tube, and the second end of the drain matching circuit is connected with a radio frequency signal output end. The first end of the gate matching circuit is connected with the gate of the field effect tube, and the second end of the gate matching circuit is connected with a radio frequency signal input end. The gate bias circuit is connected with the third end of the gate matching circuit. The source matching circuit is connected with the source of the field effect tube. The gate matching circuit comprises a low coupling inductance pair, and the coupling inductance pair is an inductance pair with opposite induced magnetic field directions. The application has small power consumption, small size, low cost and low noise.

This invention discloses an ultrawide, high-efficiency inverse Class-F power amplifier based on an elliptic low-pass filter matching network. The gate DC bias network provides the gate bias voltage required for the power amplifier transistor to operate; the drain DC bias network provides the drain bias voltage required for the power amplifier transistor to operate; the input impedance matching network includes a microstrip line, a DC blocking capacitor, and an RC parallel circuit; the output impedance matching network includes a harmonic control network and an elliptic low-pass filter matching network. The harmonic control network selects two frequency points outside the passband for second harmonic control; the elliptic low-pass filter matching network is based on an improved sixth-order Chebyshev low-pass filter, generating two transmission zeros outside the operating frequency band to achieve the conversion from fundamental impedance to second harmonic impedance. This invention enables the power amplifier to achieve high efficiency and high gain within a bandwidth exceeding five harmonics.

The invention discloses an amplifier MMIC with a grid temperature compensation bias network and a design method, and belongs to the technical field of microwave integrated circuits. The circuit comprises a grid bias module and an amplifier module. Wherein the grid bias module changes the magnitude of voltage output to the amplifier module through temperature characteristics of a resistor and a field effect transistor, the amplifier module compensates and realizes the change of quiescent current along with temperature through the temperature compensation characteristic of a main amplifier FET along with the voltage, and the function that the quiescent current of the amplifier is greatly reduced along with temperature fluctuation is realized. The grid temperature compensation biasing circuit suitable for the E technology can compensate the phenomenon that quiescent current fluctuation of an amplifier is too large along with temperature.

The invention discloses a chip aging test system and method, and the method comprises the steps: constructing a main buried layer and a reference buried layer in a silicon substrate in a chip manufacturing stage, enabling a sensing structure and a transistor to share a substrate and the same technology, and eliminating the parasitic effect introduced by a probe from a physical level; zero offset voltage and a temperature drift compensation value are obtained through initial offset calibration, and sensing signals are continuously corrected in the aging process; extracting the source electrode-substrate junction leakage current of the spatially coupled target transistor through differential processing, completing multi-dimensional normalization according to the cavity temperature and the grid bias voltage, and finally generating a normalized leakage current sequence capable of directly representing the intrinsic degradation trend of the device; the sequence supports continuous central difference operation, so that the inflection point moment of the leakage current is accurately identified, the residual service life is predicted according to the inflection point moment, and a degradation fingerprint spectrum is generated; therefore, the method realizes undisturbed, synchronous, in-situ and quantitative sensing of the leakage current of the key node under the real aging stress.

A radio-frequency power source, includes: an amp unit including a gate terminal, a drain terminal, and a source terminal; an output terminal; an input power unit electrically connected to the gate terminal, configured to supply an input power to the amp unit, and configured to change frequencies in a frequency band in which the input power is can be supplied; a first setting unit, and configured to set a gate bias voltage of the amp unit; a second setting unit electrically connected to the drain terminal, and configured to set a drain bias voltage of the amp unit; and an instruction unit configured to output instruction values with which a radio-frequency power output from the output terminal is set for maximum efficiency to the input power unit, the first setting unit, and the second setting unit with respect to each of the frequencies in the frequency band.

Power amplifier circuitry is disclosed having an inverse Class-D amplifier functioning as a power amplifier and self-biasing circuitry generating gate bias voltages for switching type power transistors within the power amplifier. The self-biasing circuitry includes a low-dropout regulator that generates and applies a gate bias voltage in response to a feedback current scaled according to the power amplifier's operating current. A current-based digital-to-analog converter is configured to generate the reference current based on a received digital value. Additionally, a digital processor is configured to generate the digital value in response to the gate bias voltage. The power amplifier circuitry enhances performance and efficiency while ensuring precise control over power transistors'operation, offering advantages for various applications requiring radio frequency signal amplification.

An apparatus includes a transistor (204) configured to receive an electrical current generated by an input source and an integration capacitor configured (208) to receive the electrical current through the transistor and store an electrical charge. The apparatus also includes an amplifier (206) configured to be coupled to the input source and to generate a control signal for a gate of the transistor. The apparatus further includes a comparator (214) configured to compare the stored electrical charge on the integration capacitor to a reference voltage (VREF). In addition, the apparatus includes one or more switches (210, 212) configured to adjust an operating mode of the apparatus. In a DI mode, the one or more switches are configured to couple a fixed gate bias voltage (VDI) to the gate of the transistor. In a BDI mode, the one or more switches are configured to couple the control signal from the amplifier to the gate of the transistor.

According to one aspect, there is provided a swing-enhanced differential oscillator (500) and a method for trimming an oscillator. The oscillator comprises: a switch (110 ') for alternately connecting a set of capacitors (C1, C2) to a power supply and ground (102', 112 ') based on a switching control (116A', 116B '); two comparators (502, 504) configured to be coupled to each other by coupling capacitors (C1, C2) at inputs (VC1, VC2) of the comparators (502, 504) to the capacitors (C1, C2); an output signal (ck) of the oscillator and a switching control (116A ', 116B') are generated via a multiplexer (508) by comparing a voltage of the oscillator (C1, C2) with a threshold voltage (VBB), where the comparator includes a back gate bias input (Figure 5: 804, Figure 8: Vbb, 804) for controlling the threshold voltage of the comparator that trims the frequency of the output signal of the oscillator.