97 results about "Grid bias" patented technology

The invention relates to the technical field of radio frequency integrated circuits, in particular to a harmonic suppression power amplifier combining a matching network and a feed network, which comprises a transistor, an input matching module, an output matching module, a stabilizing module and a bias module, the input matching module comprises a first parallel resonance unit, the first parallel resonance unit is used for second harmonic suppression, the output matching module comprises a series resonance unit and a second parallel resonance unit, the series resonance unit is used for resonating at a second harmonic frequency and performing low-impedance grounding on the second harmonic, and the second parallel resonance unit is used for resonating at a second harmonic frequency and performing low-impedance grounding on the second harmonic. The second parallel resonance unit is used for resonating at a third harmonic frequency and forms a high-impedance open circuit for the third harmonic, the output matching module is coupled to a drain electrode of the transistor, and the bias module comprises a grid bias sub-module and a drain bias sub-module. The grid bias sub-module is coupled to a connection node of the input matching module and the grid of the transistor, the drain bias sub-module is coupled to the output matching module, and the bias voltage of the transistor is jointly determined by the grid bias sub-module and the drain bias sub-module. The power amplifier has the effect of improving the efficiency level of the power amplifier while realizing harmonic suppression optimization.

Embodiments of the present disclosure include adaptive bias control of cascode drivers in envelope tracking power amplifier devices, systems, and methods. In some aspects, a wireless communication device is disclosed that includes a power amplifier. The power amplifier may include a driver stage configured to receive a variable voltage supply signal, and a power amplifier stage following the driver stage. In some embodiments, the driver stage includes a cascode gate bias circuit configured to receive a first signal that is based on the variable voltage supply signal; and a cascode amplifier stage comprising a first field effect transistor (FET) and a second FET in a stacked configuration. The cascode gate bias circuit may be further configured to adaptively convert the first signal into a bias signal for a gate of the first FET. The power amplifier stage may be configured to generate an amplified signal based on the intermediate output.

The invention discloses a single-power-supply ultra-wideband temperature compensation low-noise amplifier circuit, and belongs to the technical field of radio frequency microwaves. The circuit is mainly composed of a pre-stage low-noise amplifier module, an inter-stage temperature compensation equalization module and a post-stage driving amplifier module. The temperature compensation equalizer module generates differential voltage related to temperature through a three-stage gallium arsenide diode temperature sensing unit, outputs a control signal through an enhanced FET differential amplification circuit, drives a voltage-controlled attenuation equalizer to dynamically adjust the attenuation amount of a radio frequency signal, and achieves gain stability in a frequency band. Through the collaborative design of a blocking capacitor and a divider resistor, the grid bias of an FET switch is strictly limited in a transconductance linear adjustment interval, and the interval covers 80% of the effective range of the threshold voltage of a gallium arsenide FET tube. The circuit is powered by a single power supply + 5V, stable work of each module is ensured through active bias and a power supply filter network, and the circuit is suitable for extreme temperature environments such as high-frequency communication and radar.

The invention provides a maladjustment self-calibration method. The maladjustment self-calibration method comprises the following steps: 1) short-circuiting input signal ends VINP and VINN of an amplifying circuit to a common-mode voltage VCOM; 2) detecting an output signal difference value of the signal output ends VOUTP and VOUTN of the amplification circuit through a comparator, wherein the difference value is an offset error and generates high and low level signals; 3) accumulating the high and low level signals in a preset period through a counter to obtain an error value, converting the error value into a digital control signal through a register, and returning the digital control signal to the amplification circuit; and 4) the amplification circuit adjusts the input end to compensate the grid bias voltage of the CMOS circuit according to the digital control signal, and adjusts the offset error value to the reduction direction. The invention further provides a high-speed amplification circuit which uses the offset calibration method.

A radio frequency power amplifier includes a power amplification transistor and a gate bias circuit. The gate bias circuit includes a VHb terminal connected to a high voltage power supply for bias, a VLb terminal connected to a low voltage power supply for bias, an enable terminal that receives an enable signal, an enable transistor and a voltage dividing resistor that are connected in series and connected between the VHb terminal and the VLb terminal, a driver that outputs a voltage to a control terminal of the enable transistor, and a gate bias output terminal that outputs, as a gate bias voltage, a divided voltage generated by the voltage dividing resistor. When an OFF signal is received as the enable signal, the driver causes the enable transistor to operate in a first operating area that is not a cutoff region.

Bias circuits for CMOS power amplifiers are provided. The bias circuit includes a feedback module, a first bias module, and a second bias module. The feedback module has a first input connected to a output common mode voltage, a second input connected to a reference voltage, and an output connected to gates of main amplification transistors in a first differential amplification module; based on a difference between the output common mode voltage and the reference voltage, the feedback module adjusts gate voltages of main amplification transistors until the output common mode voltage is equal to the reference voltage; the first bias module provides bias voltages for the first differential amplification module; the second bias module provides bias voltages for a second differential amplification module. The present disclosure adopts direct negative feedback and cascoded current mirrors, which realize accurate DC gate bias and accurate control of the output common mode voltage.

An RF circuit is disclosed that may include a driver stage. The driver stage may include a gate bias circuit configured to receive a variable voltage supply signal; and an amplifier stage comprising a FET, wherein the gate bias circuit is configured to adaptively convert the variable voltage supply signal into a bias signal. The RF circuit may further include a circuit component configured to combine the bias signal and a radio frequency input signal to generate a combined signal, and wherein the amplifier stage is configured to receive the combined signal at a gate of the FET and to produce an intermediate output, and wherein the gate bias circuit is configured to generate the bias signal such that the bias signal increases as the variable voltage supply signal decreases to compensate for a tendency of a current through the FET to decrease as the variable voltage supply signal decreases.

The application discloses a Doherty power amplifier integrated circuit and a preparation method and device thereof, and relates to the technical field of communication.The Doherty power amplifier integrated circuit comprises a power divider, a main power amplifier, a peak power amplifier, a gate bias voltage regulator and a combiner; a first signal output end of the power divider is connected with a signal input end of the main power amplifier, and a signal output end of the main power amplifier is connected with a first signal input end of the combiner; a second signal output end of the power divider is connected with a signal input end of the peak power amplifier, and a signal output end of the peak power amplifier is connected with a second signal input end of the combiner; pinch-off voltage of the peak power amplifier is different from that of the main power amplifier, and an output end of the gate bias voltage regulator is connected with a gate of the main power amplifier and a gate of the peak power amplifier respectively.The Doherty power amplifier integrated circuit can simplify a power supply system.

The invention discloses a ka wave band high-efficiency power amplifier based on a GaAs technology. A circuit comprises an input stage tube core, a driving stage tube core, an output stage tube core, an output stage second harmonic suppression network, an inter-stage matching network, an output matching network, a grid electrode biasing circuit, a drain electrode biasing circuit and a stabilizing resistor. The input matching network adopts a T-shaped matching network structure, and the inter-stage matching circuit adopts a matching network combining an LC series structure and a T-shaped structure, so that the working bandwidth of the circuit is further improved, and the area of the power amplifier is reduced; the output efficiency of the whole power amplifier is improved by introducing a second harmonic suppression network at the output end by adopting a second harmonic suppression technology. According to the invention, based on the 0.15 [mu] m GaAs pHEMT technology, a three-stage cascade amplification and power distribution synthesis structure is adopted to realize that the output saturation power is greater than or equal to 29.5 dBm and the power additional efficiency is greater than or equal to 34% in the working frequency band of 34-38GHz, and the power amplifier has the advantages of high stability, high power additional efficiency, high saturation output power, wide working frequency band and the like.

The invention belongs to the field of integrated circuits, and relates to a distributed amplifier, in particular to a distributed amplifier based on a GaN process, which comprises N stages of traveling wave tube networks and a grid power supply bias network, the N stages of traveling wave tube networks comprise cascaded N traveling wave tube networks, and the Nth stage of traveling wave tube network outputs radio frequency signals; and the grid power supply bias network is used for providing bias voltage for the N-stage traveling wave tube network and is connected with the Nth-stage traveling wave tube network. Compared with a traditional distributed amplifier, according to the grid power supply bias network, a traditional grid absorption resistor is not connected with grid bias power supply voltage, the grid absorption resistor is divided into two resistors, and a filter capacitor is connected to the ground at an intermediate node of the two resistors; the tail end of the resistor is connected with grid bias power supply voltage, so that the bandwidth is expanded, and the stability of the circuit is improved; in addition, an input matching network is added to the input end of the amplifier, and input standing waves are optimized.

The application discloses an amplifier, a radio frequency chip and an electronic device. The amplifier comprises a field effect tube, a drain matching circuit, a gate matching circuit, a gate bias circuit and a source matching circuit. The field effect tube comprises a drain, a gate and a source, and is used for signal amplification. The first end of the drain matching circuit is connected with the drain of the field effect tube, and the second end of the drain matching circuit is connected with a radio frequency signal output end. The first end of the gate matching circuit is connected with the gate of the field effect tube, and the second end of the gate matching circuit is connected with a radio frequency signal input end. The gate bias circuit is connected with the third end of the gate matching circuit. The source matching circuit is connected with the source of the field effect tube. The gate matching circuit comprises a low coupling inductance pair, and the coupling inductance pair is an inductance pair with opposite induced magnetic field directions. The application has small power consumption, small size, low cost and low noise.

This invention discloses an ultrawide, high-efficiency inverse Class-F power amplifier based on an elliptic low-pass filter matching network. The gate DC bias network provides the gate bias voltage required for the power amplifier transistor to operate; the drain DC bias network provides the drain bias voltage required for the power amplifier transistor to operate; the input impedance matching network includes a microstrip line, a DC blocking capacitor, and an RC parallel circuit; the output impedance matching network includes a harmonic control network and an elliptic low-pass filter matching network. The harmonic control network selects two frequency points outside the passband for second harmonic control; the elliptic low-pass filter matching network is based on an improved sixth-order Chebyshev low-pass filter, generating two transmission zeros outside the operating frequency band to achieve the conversion from fundamental impedance to second harmonic impedance. This invention enables the power amplifier to achieve high efficiency and high gain within a bandwidth exceeding five harmonics.

The invention discloses an amplifier MMIC with a grid temperature compensation bias network and a design method, and belongs to the technical field of microwave integrated circuits. The circuit comprises a grid bias module and an amplifier module. Wherein the grid bias module changes the magnitude of voltage output to the amplifier module through temperature characteristics of a resistor and a field effect transistor, the amplifier module compensates and realizes the change of quiescent current along with temperature through the temperature compensation characteristic of a main amplifier FET along with the voltage, and the function that the quiescent current of the amplifier is greatly reduced along with temperature fluctuation is realized. The grid temperature compensation biasing circuit suitable for the E technology can compensate the phenomenon that quiescent current fluctuation of an amplifier is too large along with temperature.

The invention discloses a chip aging test system and method, and the method comprises the steps: constructing a main buried layer and a reference buried layer in a silicon substrate in a chip manufacturing stage, enabling a sensing structure and a transistor to share a substrate and the same technology, and eliminating the parasitic effect introduced by a probe from a physical level; zero offset voltage and a temperature drift compensation value are obtained through initial offset calibration, and sensing signals are continuously corrected in the aging process; extracting the source electrode-substrate junction leakage current of the spatially coupled target transistor through differential processing, completing multi-dimensional normalization according to the cavity temperature and the grid bias voltage, and finally generating a normalized leakage current sequence capable of directly representing the intrinsic degradation trend of the device; the sequence supports continuous central difference operation, so that the inflection point moment of the leakage current is accurately identified, the residual service life is predicted according to the inflection point moment, and a degradation fingerprint spectrum is generated; therefore, the method realizes undisturbed, synchronous, in-situ and quantitative sensing of the leakage current of the key node under the real aging stress.

A radio-frequency power source, includes: an amp unit including a gate terminal, a drain terminal, and a source terminal; an output terminal; an input power unit electrically connected to the gate terminal, configured to supply an input power to the amp unit, and configured to change frequencies in a frequency band in which the input power is can be supplied; a first setting unit, and configured to set a gate bias voltage of the amp unit; a second setting unit electrically connected to the drain terminal, and configured to set a drain bias voltage of the amp unit; and an instruction unit configured to output instruction values with which a radio-frequency power output from the output terminal is set for maximum efficiency to the input power unit, the first setting unit, and the second setting unit with respect to each of the frequencies in the frequency band.

Power amplifier circuitry is disclosed having an inverse Class-D amplifier functioning as a power amplifier and self-biasing circuitry generating gate bias voltages for switching type power transistors within the power amplifier. The self-biasing circuitry includes a low-dropout regulator that generates and applies a gate bias voltage in response to a feedback current scaled according to the power amplifier's operating current. A current-based digital-to-analog converter is configured to generate the reference current based on a received digital value. Additionally, a digital processor is configured to generate the digital value in response to the gate bias voltage. The power amplifier circuitry enhances performance and efficiency while ensuring precise control over power transistors'operation, offering advantages for various applications requiring radio frequency signal amplification.

An apparatus includes a transistor (204) configured to receive an electrical current generated by an input source and an integration capacitor configured (208) to receive the electrical current through the transistor and store an electrical charge. The apparatus also includes an amplifier (206) configured to be coupled to the input source and to generate a control signal for a gate of the transistor. The apparatus further includes a comparator (214) configured to compare the stored electrical charge on the integration capacitor to a reference voltage (VREF). In addition, the apparatus includes one or more switches (210, 212) configured to adjust an operating mode of the apparatus. In a DI mode, the one or more switches are configured to couple a fixed gate bias voltage (VDI) to the gate of the transistor. In a BDI mode, the one or more switches are configured to couple the control signal from the amplifier to the gate of the transistor.

The invention discloses a four-dimensional antenna array system based on a grid time modulation active radio frequency module, and belongs to the technical field of wireless communication and radio frequency. According to the system, the grid bias control of the radio frequency power amplifier is combined with the time modulation time sequence of the four-dimensional antenna array, so that the same power amplifier has signal amplification and high-speed on-off functions. In the working process of the four-dimensional antenna array, the grid bias voltage is periodically switched, so that efficient time modulation of the radiation unit is realized, a signal is amplified during the turn-on period, and zero static power consumption is realized during the turn-off period. According to the four-dimensional antenna array, the problems of insertion loss and static power consumption in the turn-off period of a traditional radio frequency switch and power amplifier framework in the four-dimensional antenna array are effectively solved, the system efficiency is remarkably improved, the four-dimensional antenna array is particularly suitable for being applied to the four-dimensional antenna array with low duty ratio, multiple beams and rapid beam scanning, and the four-dimensional antenna array has the advantages of being simple in structure, low in cost, high in modulation speed and the like.

This invention discloses a wide input range pre-regulated power supply circuit, belonging to the field of integrated circuits, including NMOS transistors MN1 to MN3, diodes D1 to D2, resistors R1 to R6, capacitors C1 to C2, and Zener transistors ZN1 to ZN6. The circuit's pre-regulated voltage is achieved through a Zener reference source, and its voltage is approximately equal to the breakdown voltage of Zener diode ZN6. NMOS transistors MN1 to MN3 are connected in series to increase the circuit's maximum input voltage. Diodes D1 and D2 are connected in series with Zener diode ZN1 to generate the gate bias voltage of NMOS transistor MN3. Resistor R1 puts Zener diode ZN1 into a breakdown state, and capacitor C1 provides filtering for the gate voltage of NMOS transistor MN3. Resistors R2, R3, and R4 put Zener diode ZN2 into a breakdown state and generate the gate bias voltages of NMOS transistors MN1 and MN2. Zener diodes ZN3, ZN4, and ZN5 clamp the gate-source voltages of NMOS transistors MN1, MN2, and MN3 to approximately 5V, respectively, to prevent the NMOS devices from failing due to gate-source breakdown. Resistor R5 limits the current in the main pre-regulated voltage path of the Zener diodes. Resistor R6 provides a DC load for the pre-regulated voltage, and capacitor C2 filters the pre-regulated voltage.

The invention relates to a low-noise amplifier device in a liquid nitrogen temperature zone. The amplifier device includes a first stage die cell, a second stage die cell, an inter-stage matching circuit, and an output matching circuit. The first-stage tube core unit comprises an amplifier GaAS pHEMT tube core T1, S parameters of a gold wire L1 and a gold wire L2, an input blocking capacitor C1, a T1 gate bias circuit, a T1 drain bias circuit and an RLC feedback circuit. The second-stage tube core unit comprises a GaAs pHEMT tube core T2, S parameters of a gold wire L3 and a gold wire L4, a T2 gate bias circuit, a T2 drain bias circuit and an RLC feedback circuit. The low-temperature amplifier can work below a liquid nitrogen temperature zone, is low in noise temperature and high in gain flatness in a broadband range, and can be well used as a low-noise amplification circuit.

The present invention realizes an attenuator circuit and an output load circuit capable of suppressing performance degradation and compensating for variations in gain due to temperature characteristics of a power amplifier element. An attenuator circuit (1) is provided with: an input / output circuit (10) provided at the preceding stage of a power amplifier; and a first control circuit (20) that controls the gain of the input / output circuit (10). An input / output circuit (10) is provided with at least: a first resistor (11) electrically connected between an input terminal (ATTin) and an output terminal (ATTout); and a first FET (12) electrically connected between the output terminal (ATTout) and the reference potential point (GND). The first control circuit (20) is provided with at least a second FET (21) having substantially the same on-resistance as the first FET (12) when the same gate bias voltage as the first FET (12) is applied. The gate of the first FET (12) and the gate of the second FET (21) are electrically connected.

A high frequency power amplifier (100) comprises a plurality of unit amplifiers (4) mounted on a semiconductor substrate (1). The plurality of unit amplifiers (4) each have: a high frequency transistor (12) which has a plurality of gate fingers (9), at least one drain finger (8), and a plurality of source fingers (7); a gate bus line (13) which is connected to one end of each of the plurality of gate fingers (9); a drain bus line (14) which is connected to one end of the at least one drain finger (8); a gate bias circuit (20) which is connected to the gate bus line (13); and a bias terminal (21) which supplies a voltage to the gate bias circuit (20). The voltages supplied to the respective bias terminals (21) of the plurality of unit amplifiers (4) are the same or different.

An electrolyteless fuel cell system includes an anode; a cathode; an electrical grid between the anode and cathode; an anode side grid bias electrode; a cathode side grid bias electrode; and an electrical grid power supply, wherein the electrical grid is biased negative with respect to the anode through the anode side grid bias electrode and the electrical grid power supply, or wherein the electrical grid is biased positive with respect to the cathode through the cathode side grid bias electrode and the electrical grid power supply. In electrolyteless electrolyzer mode steam is introduced to the cathode, wherein the electrical grid is biased positive with respect to the cathode through the cathode side grid bias electrode and the electrical grid power supply.

An RF circuit is disclosed that may include a driver stage. The driver stage may include a gate bias circuit configured to receive a variable voltage supply signal; and an amplifier stage comprising a FET, wherein the gate bias circuit is configured to adaptively convert the variable voltage supply signal into a bias signal. The RF circuit may further include a circuit component configured to combine the bias signal and a radio frequency input signal to generate a combined signal, and wherein the amplifier stage is configured to receive the combined signal at a gate of the FET and to produce an intermediate output, and wherein the gate bias circuit is configured to generate the bias signal such that the bias signal increases as the variable voltage supply signal decreases to compensate for a tendency of a current through the FET to decrease as the variable voltage supply signal decreases.

Various methods and circuital arrangements for reducing a turn ON time of a cascode amplifier are presented. According to one aspect, a configurable switching arrangement coupled to a cascode transistor of the amplifier shorts a gate of the cascode transistor to a reference ground during an inactive mode of operation of the amplifier. During an active mode of operation of the amplifier, the configurable switching arrangement couples a gate capacitor to the gate of the cascode transistor that is pre-charged to a voltage that is higher than a gate biasing voltage to the cascode transistor, which ensures that cascode transistor turns ON much quicker than the traditional method of grounding the cap, hence provide a final current flow through the cascode amplifier in a shorter time by not limiting the turn ON time of the input transistor. The gate biasing voltage is coupled to the gate capacitor via a resistor. A relationship between the pre-charged voltage, and minimum saturation voltages and threshold voltages of the transistors of the cascode amplifier is also provided.

The Doherty amplifier comprises: a first filter circuit (6a) that, when an input signal of the first frequency band is input, outputs a first input signal that attenuates the input signal by a first attenuation amount, and when an input signal of the second frequency band different from the first frequency band is input, outputs a second input signal that allows the input signal to pass; and a second filter circuit (6b) that, when an input signal of the first frequency band is input, outputs a third input signal that attenuates the input signal by a second attenuation amount smaller than the first attenuation amount, and when an input signal of the second frequency band is input, outputs a third input signal that attenuates the input signal by an attenuation amount greater than the first attenuation amount. The fourth input signal of attenuation; the first amplifier (8a), whose gate bias voltage is fixed, operates as an auxiliary amplifier when input to the first input signal from the first filter circuit (6a), and operates as a main amplifier when input to the second input signal from the first filter circuit (6a); and the second amplifier (8b), whose gate bias voltage is fixed, operates as a main amplifier when input to the third input signal from the second filter circuit (6b), and operates as an auxiliary amplifier when input to the fourth input signal from the second filter circuit (6b).

The invention relates to a high electron mobility transistor with a superlattice cap layer and a preparation method, and belongs to the field of semiconductor devices, the high electron mobility transistor sequentially comprises a substrate, a GaN buffer layer, a GaN channel layer, an AlN insertion layer and an AlGaN barrier layer from bottom to top, the superlattice cap layer is arranged above the AlGaN barrier layer, and gate metal is arranged above the superlattice cap layer; the superlattice cap layer is composed of p-GaN cap layers and n-GaN cap layers which are alternately arranged, and the p-GaN cap layers and the n-GaN cap layers in the superlattice cap layer form a PN junction structure. According to the invention, the p-GaN cap layers and the n-GaN cap layers are alternately arranged to form the superlattice cap layer, and a plurality of PN junction structures are generated in the cap layer, so that an under-gate channel region can be further depleted, and the threshold voltage is remarkably improved; a plurality of continuous reverse-biased PN junctions can significantly reduce grid electric leakage; meanwhile, the multi-stage PN junctions connected in series can share the grid bias voltage, smooth the peak electric field and enhance the withstand voltage of the device.

The invention provides a leakage region quiescent current reduction circuit and a low dropout linear regulator, belongs to the technical field of integrated circuits, is applied to a target circuit comprising a three-stage amplification unit and an inter-stage impedance matching network connected between a second-stage amplification unit and a third-stage amplification unit, and comprises a current sampling unit, a first-stage impedance matching unit, a second-stage impedance matching unit and a third-stage impedance matching unit, the sampling unit is used for sampling current of the third-stage amplification unit; one end of the resistance voltage division unit is connected with the control end of the second-stage amplification unit, and a voltage division node is connected with the output end of the current sampling unit; the control end of the second-stage amplification unit is further connected with a grid bias current, the grid bias current generates a control signal at the control end of the second-stage amplification unit through the resistance voltage dividing unit, and the second-stage amplification unit forms an access according to the control signal so as to limit the current of a branch where the inter-stage impedance matching network is located. The beneficial effect is that the purpose of reducing the quiescent current of the leakage region is achieved by limiting the current of the branch where the inter-stage impedance matching network is located.

According to the test method for the BTI effect of the MOSFET discrete device, a Keysight B2902 source meter can provide dual-channel power supply voltage and is connected with a grid electrode, a source electrode and a drain electrode of the MOSFET device. A constant grid bias voltage is applied to the grid during BTI effect test under the control of a computer program of the source meter, and the other two electrodes are grounded; when the threshold voltage of the device under different stress time is tested, the source meter in-situ test can also be used, and the situation that the BTI effect is recovered due to the fact that the interval time between the grid bias voltage and the test is long after the grid bias voltage is removed, and the test result is inaccurate is avoided.

Embodiments of the present disclosure include adaptive bias control of cascode drivers in envelope tracking power amplifier devices, systems, and methods. In some aspects, a wireless communication device is disclosed that includes a power amplifier. The power amplifier may include a driver stage configured to receive a variable voltage supply signal, and a power amplifier stage following the driver stage. In some embodiments, the driver stage includes a cascode gate bias circuit (202) configured to receive a first signal that is based on the variable voltage supply signal; and a cascode amplifier stage (204) comprising a first field effect transistor (Mi) and a second field effect transistor (M2) in a stacked configuration. The cascode gate bias circuit (202) may be further configured to adaptively convert the first signal into a bias signal for a gate of the first field effect transistor (Mi).