Terahertz antenna structure based on mixed single-layer and double-layer delay lines and precoding method

Abstract

The invention provides a terahertz antenna structure and precoding method based on a mixed single-layer and double-layer delay line, and the method comprises the steps: firstly, analyzing the relation between the position of an antenna and the delay range of a delay line based on a single-layer delay line structure, and designing a brand new delay line deployment scheme; secondly, designing a mixed single-layer and double-layer delay line structure based on a brand new delay line deployment scheme, namely, adopting a single-layer delay line structure in the middle part of an antenna needing to provide small time delay, and adopting a double-layer delay line structure at two end parts needing to provide large time delay; then calculating the maximum time delay of the mixed single-layer and double-layer delay line structure, and quantifying the hardware complexity of the mixed single-layer and double-layer delay line structure based on the maximum time delay; and finally, designing a hybrid analog digital pre-coding scheme based on the hybrid single-layer and double-layer delay line structure. According to the invention, the hardware complexity and power consumption of the terahertz antenna structure are effectively reduced, and high spectrum efficiency is maintained.

Description

Technical Field

[0001] The present invention relates to the field of terahertz communication technology, and in particular to a terahertz antenna structure and precoding method based on a hybrid single- and double-layer delay line. Background Art

[0002] To overcome the beam splitting effect in terahertz communication, a direct solution is to replace all phase shifters with frequency-dependent delay lines. However, since the hardware complexity of delay lines is higher than that of phase shifters, a large number of delay lines will result in huge hardware complexity and power consumption. Based on this, some studies have proposed inserting a limited number of delay lines between the radio frequency chain and phase shifters, and by jointly controlling the phase shifters and delay lines, generating a beam pointing to the target direction, thereby alleviating the beam splitting phenomenon. In addition, when the maximum time delay of the delay line is limited, the system performance will be significantly degraded. Especially for large antenna arrays, the delay line needs to support a large range of delays. Moreover, most current studies assume that the delay line can provide high-resolution or even infinite-resolution delays, which is not only power-consuming but also often infeasible in practical applications. Therefore, finite-resolution delay lines are considered.

[0003] In the multi-layer delay line scheme, the number of delay lines with a large delay range is significantly reduced, thus effectively reducing the hardware complexity and power consumption of the system. However, as the number of delay line layers increases, the system performance gradually degrades. Summary of the Invention

[0004] Aiming at the deficiencies in the existing background art, the present invention proposes a terahertz antenna structure and precoding method based on a hybrid single- and double-layer delay line, which effectively reduces the hardware complexity and power consumption of the terahertz antenna structure and maintains high spectral efficiency.

[0005] To achieve the above object, the technical solution of the present invention is realized as follows:

[0006] A terahertz antenna structure and precoding method based on a hybrid single- and double-layer delay line, the steps are as follows:

[0007] Step 1: Analyze the relationship between the antenna position and the delay range of the delay line based on the single-layer delay line structure, and design a new delay line deployment scheme;

[0008] Step 2: Design a hybrid single- and double-layer delay line structure based on the new delay line deployment scheme, that is, adopt a single-layer delay line structure in the middle part of the antenna that needs to provide small time delays, and adopt a double-layer delay line structure in the two end parts that need to provide large time delays;

[0009] Step 3: Calculate the maximum time delay of the hybrid single- and double-layer delay line structure, and quantify the hardware complexity of the hybrid single- and double-layer delay line structure based on the maximum time delay;

[0010] Step 4: Design a hybrid analog-digital precoding scheme based on the hybrid single- and double-layer delay line structure, where the analog precoding is jointly determined by phase shifters and delay lines, and the digital precoding is determined using a low-complexity zero-forcing precoding technique.

[0011] Preferably, the single-layer delay line structure is as follows: there is only one radio frequency (RF) chain at the base station, and this RF chain serves a single-antenna user; the uniform linear array at the base station contains N antennas, and the RF chain is connected to U delay lines; a sub-connection structure is adopted, each sub-array contains P = N / U antennas, and the azimuth angle of the single-antenna user is θ0 ∈ [-π / 2, π / 2].

[0012] Preferably, the hybrid single- and double-layer delay line structure is as follows: one RF chain is equipped at the base station to serve a single-antenna user; the number of antennas is N, the number of first-layer delay lines in the double-layer delay line part is H h = 2H, each first-layer delay line unit is connected to L second-layer delay lines, and the number of delay lines in the single-layer delay line part is S h = 2S, where H represents the number of first-layer delay devices at the left end, and S represents the number of single-layer delay devices on the left side of the central axis; a sub-connection structure is adopted, and these delay lines evenly divide the antennas into U h = H h L + S h sub-arrays, each sub-array contains P h = N / U h antennas, and the azimuth angle of the user is θ0 ∈ [-π / 2, π / 2].

[0013] Preferably, the method for determining the delay range of the delay line under the single-layer delay line structure is as follows:

[0014] In the single-layer delay line structure, define the time delay difference between the first delay line and the u-th delay line as τ u , u = 1, 2, …, U, then there is:

[0015] τ u = (u - 1)PT d sinθ0 (1)

[0016] where T d = d / c is the time delay between adjacent two antennas;

[0017] Considering that the time delay τ u should be greater than 0, the time delay of the u-th delay line can be optimized as:

[0018]

[0019] Therefore, in the traditional single-layer delay line structure, the maximum time delay of the delay line is (U - 1)PTd , the delay range is τ u ∈[0, (U - 1)PT d ;

[0020] In the two extreme cases where the user azimuth angle θ0 = -π / 2 and θ0 = π / 2, analyze the maximum time delay that each delay line in the single-layer delay line scheme needs to provide;

[0021] When θ0 = -π / 2, according to formula (2), the time delay that the delay line connecting the u-th subarray needs to provide is τ u =(1 - u)PT d sinθ0; Therefore, the time delay vector that the U delay lines need to provide is:

[0022]

[0023] When θ0 = π / 2, according to formula (2), the time delay that the delay line connecting the u-th subarray needs to provide is τ u =(U - u)PT d sinθ0; Therefore, the time delay vector that the U delay lines need to provide is:

[0024]

[0025] In summary, when the number of delay lines U is even, the maximum time delay vector that the delay lines connecting the U subarrays in the single-layer delay line scheme need to provide is:

[0026]

[0027] Therefore, the delay range of the u-th delay line is [0, τ max (u)];

[0028] From the above formula, the discrete delay set of the u-th delay line in the antenna structure based on the single-layer delay line can be obtained as:

[0029] τ u ∈Γ u ={0, D, 2D,..., τ max (u)D} (6)

[0030] where, D = PT d represents the delay step;

[0031] In the antenna structure based on the single-layer delay line, not all delay lines need to provide the maximum time delay (U - 1)PT d; In fact, the maximum time delay required for the delay line in the middle part of the antenna is relatively small, while the maximum time delay required for the delay lines at both ends is relatively large; Based on this, a new delay line deployment scheme is designed, that is, delay lines with different delay ranges are deployed according to different antenna positions.

[0032] Preferably, the method for determining the delay range of the delay line under the hybrid single - and double - layer delay line structure is as follows:

[0033] For the double - layer delay line part of the hybrid single - and double - layer delay line structure, the transmission delay generated by the first - layer delay line unit is:

[0034] τ h =(h - 1)LP h T d sinθ0 (7)

[0035] Where, for the double - layer delay line at the left end, h = 1,..., H, and for the double - layer delay line at the right end, h = U h / L - H + 1,..., U h / L;

[0036] The transmission delay generated by the second - layer delay line unit is:

[0037] τ l =(l - 1)P h T d sinθ0, l = 1,..., L (8)

[0038] Therefore, the total transmission delay generated by the delay line in the double - layer delay line part is:

[0039] τ h,l =[(h - 1)L+(l - 1)]P h T d sinθ0 (9)

[0040] For the single - layer delay line part of the hybrid single - and double - layer delay line structure, the transmission delay generated by the s - th delay line unit is:

[0041] τ s =(s - 1)P h T d sinθ0 (10)

[0042] Where, s = HL + 1,..., HL + S h ;

[0043] Considering that the time delay is greater than 0, therefore, for the double - layer delay line part, the time delay of the l - th second - layer delay line connected to the h - th first - layer delay line should be modified to:

[0044]

[0045] For the single-layer time delay line part, the time delay of the s-th time delay line should be modified to:

[0046]

[0047] Divide the hybrid single-double layer time delay line structure into three parts: the left-end double layer time delay line, the middle single layer time delay line, and the right-end double layer time delay line. Referring to the analysis process of the single-layer time delay line structure, when θ0 = -π / 2, the time delay vector is:

[0048]

[0049] When θ0 = π / 2, the time delay vector is:

[0050]

[0051] In summary, the maximum time delay vector of the hybrid single-double layer time delay line structure is:

[0052]

[0053] Therefore, the delay range of the time delay line where the u-th sub-array is located is [0, τ hmax (u)];

[0054] From the above formula, for the hybrid single-double layer time delay line structure, when h = 1,..., H, the discrete time delay set of the double layer time delay line part is:

[0055]

[0056] When h = U h / L - H + 1,..., U h / L, the discrete time delay set of the double layer time delay line part is:

[0057]

[0058] The discrete time delay set of the s-th time delay line in the single layer time delay line part is:

[0059] τ s ∈Γ s ={0, D, 2D,..., τ hmax (s)D} (20).

[0060] Preferably, the quantization method for the hardware complexity of the hybrid single-double layer time delay line structure is:

[0061] Taking a radio frequency chain as an example to analyze the hardware complexity of the system, define λ to numerically measure the hardware complexity of the system; for a single-layer delay line structure with the same delay range of the delay line, its hardware complexity is expressed as:

[0062]

[0063] For a single-layer delay line structure with different delay ranges of the delay line, its hardware complexity is expressed as:

[0064]

[0065] Therefore, the reduction degree of the hardware complexity of the single-layer delay line structure with different delay ranges compared to that with the same delay range is expressed as:

[0066]

[0067] For a hybrid single- and double-layer delay line structure with different delay ranges of the delay line, its hardware complexity is expressed as:

[0068]

[0069] Assume that each radio frequency chain of the double-layer delay line scheme is connected to H t first-layer delay lines, and each first-layer delay line unit is connected to L t second-layer delay lines. Then, for a double-layer delay line structure with different delay ranges of the delay line, its hardware complexity is expressed as:

[0070]

[0071] Similarly, when the delay ranges are different, compared with the single-layer delay line structure, the reduction degrees of the hardware complexity of the hybrid single- and double-layer delay line structure and the double-layer delay line scheme are λ h / λ1 and λ2 / λ1, respectively.

[0072] Preferably, the hybrid analog-digital precoding scheme based on the hybrid single- and double-layer delay line structure is:

[0073] According to the array response vector f(f c ,θ c ,θ k ) at the center frequency f n,p , the frequency-independent phase shift ψ

[0074] ψ n,p generated by the phase shifter unit is: c (p - 1)T d sinθ k (26)

[0075] where n = 1, 2,..., NRF For the single-layer delay line structure, p = 1, ..., P, and for the hybrid single-double layer delay line structure, p = 1, ..., P h ;

[0076] For the single-layer delay line structure, the frequency-dependent delay τ generated by the delay line where the u-th subarray is located n,u is:

[0077] τ n,u =(u - 1)PT d sinθ k (27)

[0078] Based on the actual hardware limitations, considering the finite-resolution delay line, the transmission delay τ n,u is discretized to obtain the discretized delay τ′ n,u which is:

[0079]

[0080] Therefore, the phase shift ψ generated by the delay line n,p is:

[0081] ψ n,u =2πf m τ′ n,u (29)

[0082] In the antenna structure based on the single-layer delay line, the phases of the antenna elements are jointly regulated by a phase shifter independent of frequency and a delay line dependent on frequency; thus, when the frequency is f m , the phase ψ of the p-th antenna element in the u-th subarray n,u,p is:

[0083] ψ n,u,p =ψ n,p +ψ n,u (30)

[0084] Then the expression of the analog precoding matrix of the single-layer delay line structure is:

[0085]

[0086] where, is the analog precoding vector of a single RF chain, and the expression is:

[0087]

[0088] For the double-layer delay line part of the hybrid single-double layer delay line structure, the delay τ generated by the first-layer delay line unit n,h is:

[0089] τn,h = (h - 1)LP h T d sinθ k (33)

[0090] The time delay τ generated by the second - layer time - delay line unit connected to the first - layer time - delay line unit n,l is:

[0091] τ n,l = (l - 1)P h T d sinθ k (34)

[0092] When 1 ≤ U h ≤ HL, the discrete time - delay expression obtained after discretization is:

[0093]

[0094] When HL + S h + 1 ≤ U h ≤ H h L + S h , the discrete time - delay expression obtained after discretization is:

[0095]

[0096] For the single - layer time - delay line part of the hybrid single - and double - layer time - delay line structure, the time delay τ generated by the s - th time - delay line n,s is:

[0097] τ n,s = (s - 1)P h T d sinθ k (39)

[0098] The discrete time - delay expression τ′ n,s is:

[0099]

[0100] To sum up, when the frequency is f m , the phase ψ of the p - th antenna element in the u - th sub - array n,u,p is:

[0101]

[0102] Then the expression of the analog precoding matrix of the hybrid single - and double - layer time - delay line structure is:

[0103]

[0104] Among them, is the analog precoding vector of a single radio frequency chain, and the expression is:

[0105]

[0106] Finally, based on the equivalent channel matrix, a low-complexity zero-forcing precoding technique is used to design digital precoding, so as to obtain the digital precoding vector

[0107] Advantages of the present invention:

[0108] 1) Based on the sub-connected antenna structure of a single-layer delay line, the present invention analyzes the delay range of the delay line required for different antenna positions, and designs a method for deploying delay lines with different ranges according to the antenna positions, reducing the complexity of the terahertz antenna structure and maintaining high spectral efficiency. Since the hardware complexity of the delay line increases with the increase of the delay range, this method can effectively reduce the delay range and hardware complexity of the delay line in the middle part of the antenna.

[0109] 2) The present invention proposes a system model of a hybrid single- and double-layer delay line. According to the different delay requirements of the delay line for different antenna positions, a single-layer or double-layer delay line structure is flexibly adopted, that is, a single-layer delay line structure is adopted in the middle part of the antenna that needs to provide a small time delay, while a double-layer delay line structure is adopted at both ends of the antenna that needs to provide a large time delay; further reducing the number of delay lines in a large range, this model can effectively reduce the hardware complexity and power consumption of the system while sacrificing a small amount of sum rate.

[0110] 3) The present invention proposes an effective hybrid analog / digital precoding method, in which analog precoding is jointly designed by phase shifters and delay lines, while digital precoding is implemented by the zero-forcing precoding technique based on the equivalent channel matrix; by adjusting the ratio of the single-layer delay line part and the double-layer delay line part in the hybrid single- and double-layer delay line scheme, high performance of the system can be achieved with low hardware complexity. Description of the Drawings

[0111] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0112] Figure 1 is the system model based on a single-layer delay line.

[0113] Figure 2 is the system model based on the hybrid single- and double-layer delay line proposed by the present invention.

[0114] Figure 3 The relationship curve between the sum rate and the signal-to-noise ratio for the single-layer delay line scheme in different scenarios.

[0115] Figure 4 The relationship curve between the sum rate and the signal-to-noise ratio for different delay line schemes.

[0116] Figure 5 The relationship curve between the sum rate and the signal-to-noise ratio for different hybrid single- and double-layer delay line schemes. Detailed implementation manners

[0117] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0118] The embodiments of the present invention provide a terahertz antenna structure and a precoding method based on a hybrid single- and double-layer delay line. The specific steps are as follows:

[0119] Step 1: Analyze the relationship between the antenna position and the delay line delay range based on the single-layer delay line structure, and design a new delay line deployment scheme.

[0120] Step 2: Design a structure based on a hybrid single- and double-layer delay line based on the new delay line deployment scheme, that is, a single-layer delay line structure is adopted in the middle part of the antenna that needs to provide a small time delay, and a double-layer delay line structure is adopted in the two end parts that need to provide a large time delay.

[0121] Step 3: Calculate the maximum time delay of the hybrid single- and double-layer delay line structure, and quantify the hardware complexity of the hybrid single- and double-layer delay line structure based on the maximum time delay.

[0122] Step 4: Design a hybrid analog-digital precoding scheme based on the hybrid single- and double-layer delay line structure. Among them, the analog precoding is jointly determined by the phase shifter and the delay line, and the digital precoding is determined by using a low-complexity zero-forcing precoding technique.

[0123] Analog precoding architecture based on single-layer delay line: For the convenience of subsequent analysis, it is assumed that there is only one radio frequency chain at the base station, and this radio frequency chain serves a single-antenna user. The analog precoding architecture based on the single-layer delay line is as Figure 1 shown. The uniform linear array at the base station in the figure contains N antennas, and the radio frequency chain is connected to U delay lines; a sub-connection structure is adopted, each sub-array contains P = N / U antennas, and the azimuth angle of the single-antenna user is θ0 ∈ [-π / 2, π / 2].

[0124] The analog precoding architecture based on the hybrid single - and double - layer delay lines is as follows Figure 1 shown in the figure. In the figure, a base station is equipped with one radio frequency chain and serves a single - antenna user; the number of antennas is N, the number of delay lines in the first layer of the double - layer delay line part is H h = 2H, each unit of the first - layer delay line is connected to L second - layer delay lines, and the number of delay lines in the single - layer delay line part is S h = 2S, where H represents the number of delay devices in the first layer at the left end, and S represents the number of single - layer delay devices on the left side of the central axis. Similarly, using the sub - connection structure, these delay lines evenly divide the antennas into U h = H h L + S h sub - arrays, and each sub - array contains P h = N / U h antennas, and the azimuth angle of the user is θ0∈[-π / 2,π / 2].

[0125] Currently, in the antenna structure based on delay lines, whether considering delay lines with infinite resolution or finite resolution, delay lines with the same delay range are usually used. However, since the time delays to be compensated by antennas at different positions are different, the actual delay ranges of the corresponding delay lines are also different. Therefore, next, the maximum time delay required by the delay lines in different delay - line schemes will be analyzed to determine the delay range of the delay lines.

[0126] According to Figure 1 , in the single - layer delay - line structure, the time - delay difference between the first delay line and the u - th delay line is defined as τ u , u = 1, 2, …, U, then there is:

[0127] τ u =(u - 1)PT d sinθ0 (1)

[0128] where, T d = d / c is the time delay between adjacent two antennas.

[0129] Considering that the time delay τ u should be greater than 0, the time delay of the u - th delay line can be optimized as:

[0130]

[0131] Therefore, in the traditional single - layer delay - line structure, the maximum time delay of the delay line is (U - 1)PT d , and the delay range is τ u ∈[0, (U - 1)PT d .

[0132] In the two extreme cases where the user azimuth angles are θ0 = -π / 2 and θ0 = π / 2, analyze the maximum time delay that each delay line in the single-layer delay line scheme needs to provide.

[0133] When θ0 = -π / 2, from formula (2), the time delay τ that the delay line connecting the u-th subarray needs to provide is u =(1 - u)PT d sinθ0; Therefore, the time delay vector that U delay lines need to provide is:

[0134]

[0135] When θ0 = π / 2, from formula (2), the time delay τ that the delay line connecting the u-th subarray needs to provide is u =(U - u)PT d sinθ0; Therefore, the time delay vector that U delay lines need to provide is:

[0136]

[0137] In summary, when the number of delay lines U is even, the maximum time delay vector that the delay lines connecting U subarrays in the single-layer delay line scheme need to provide is:

[0138]

[0139] Therefore, the delay range of the u-th delay line is [0, τ max (u)].

[0140] From the above formula, the discrete delay set of the u-th delay line in the antenna structure based on the single-layer delay line can be obtained as:

[0141] τ u ∈Γ u ={0, D, 2D,..., τ max (u)D} (6)

[0142] where D = PT d represents the delay step.

[0143] In the antenna structure based on the single-layer delay line, not all delay lines need to provide the maximum time delay (U - 1)PT dIn fact, the maximum time delay required for the delay line in the middle part of the antenna is relatively small, while that required for the delay lines at both ends is relatively large. Based on this, a new delay line deployment scheme is designed, that is, delay lines with different delay ranges are deployed according to different antenna positions. Although this scheme effectively reduces the delay range and hardware complexity of the delay lines in the middle part of the antenna, the delay lines at both ends of the antenna still need to provide a relatively large time delay. To further reduce the number of delay lines with a large delay range, the present invention proposes an antenna structure based on a hybrid single- and double-layer delay line. In this antenna structure, the middle part that needs to provide a small time delay adopts a single-layer delay line structure, while the two ends that need to provide a large time delay use a double-layer delay line structure.

[0144] For the double-layer delay line part of the hybrid single- and double-layer delay line structure, the transmission delay generated by the first-layer delay line unit is:

[0145] τ h =(h - 1)LP h T d sinθ0 (7)

[0146] where h = 1,..., H for the double-layer delay line at the left end, and h = U h / L - H + 1,..., U h / L;

[0147] The transmission delay generated by the second-layer delay line unit is:

[0148] τ l =(l - 1)P h T d sinθ0, l = 1,..., L (8)

[0149] Therefore, the total transmission delay generated by the delay lines in the double-layer delay line part is:

[0150] τ h,l =[(h - 1)L + (l - 1)]P h T d sinθ0 (9)

[0151] For the single-layer delay line part of the hybrid single- and double-layer delay line structure, the transmission delay generated by the s-th delay line unit is:

[0152] τ s =(s - 1)P h T d sinθ0 (10)

[0153] where s = HL + 1,..., HL + S h ;

[0154] Considering that the time delay is greater than 0, for the double-layer time delay line part, the time delay of the l-th second-layer time delay line connected to the h-th first-layer time delay line should be modified to:

[0155]

[0156] For the single-layer time delay line part, the time delay of the s-th time delay line should be modified to:

[0157]

[0158] Divide the hybrid single- and double-layer time delay line structure into three parts: the left-end double-layer time delay line, the middle single-layer time delay line, and the right-end double-layer time delay line to analyze the time delay of the entire hybrid time delay line structure. Referring to the analysis process of the single-layer time delay line structure, when θ0 = -π / 2, the time delay vector is:

[0159]

[0160] When θ0 = π / 2, the time delay vector is:

[0161]

[0162] To sum up, the maximum time delay vector of the hybrid single- and double-layer time delay line structure is:

[0163]

[0164] Therefore, the delay range of the time delay line where the u-th subarray is located is [0, τ hmax (u)].

[0165] From the above formula, for the hybrid single- and double-layer time delay line structure, when h = 1,..., H, the discrete time delay set of the double-layer time delay line part is:

[0166]

[0167] When h = U h / L - H + 1,..., U h / L, the discrete time delay set of the double-layer time delay line part is:

[0168]

[0169] The discrete time delay set of the s-th time delay line in the single-layer time delay line part is:

[0170] τ s ∈Γ s = {0, D, 2D,..., τ hmax (s)D} (20).

[0171] The hardware complexity of the system mainly depends on the number of bits of a single delay line unit and the total number of delay lines. At the same time, since the delay range of the delay line increases with the increase in the number of bits of the delay line, the maximum time delay provided by the delay line can be used to approximately represent its number of bits. Therefore, the product of the maximum time delay of the delay line and the number of delay lines is used here to quantify the hardware complexity of the system.

[0172] Taking a radio frequency chain as an example to analyze the hardware complexity of the system, define λ to numerically measure the hardware complexity of the system; for a single-layer delay line structure with the same delay range of the delay line, its hardware complexity is expressed as:

[0173]

[0174] For a single-layer delay line structure with different delay ranges of the delay line, its hardware complexity is expressed as:

[0175]

[0176] Therefore, the degree of reduction in the hardware complexity of a single-layer delay line structure with different delay ranges compared to that with the same delay range is expressed as:

[0177]

[0178] For a hybrid single- and double-layer delay line structure with different delay ranges of the delay line, its hardware complexity is expressed as:

[0179]

[0180] Assume that each radio frequency chain in the double-layer delay line scheme is connected to H t first-layer delay lines, and each first-layer delay line unit is connected to L t second-layer delay lines. Then, for a double-layer delay line structure with different delay ranges of the delay line, its hardware complexity is expressed as:

[0181]

[0182] Similarly, when the delay ranges are different, compared with the single-layer delay line structure, the degrees of reduction in the hardware complexity of the hybrid single- and double-layer delay line structure and the double-layer delay line scheme are λ h / λ1 and λ2 / λ1, respectively.

[0183] The hybrid analog-digital precoding scheme based on the hybrid single- and double-layer delay line structure is:

[0184] According to the array response vector f(f c , θ c , θ k ) at the center frequency f n,p , the frequency-independent phase shift ψ generated by the phase shifter unit is:

[0185] ψ n,p =2πf c (p-1)T d sinθ k (26)

[0186] Where n = 1, 2, ..., N RF For a single-layer delay line structure, p=1,...,P; for a mixed single-layer and double-layer delay line structure, p=1,...,P h .

[0187] For a single-layer delay line structure, the frequency-dependent delay τ generated by the delay line where the u-th subarray is located n,u for:

[0188] τ n,u =(u-1)PT d sinθ k (27)

[0189] Based on the actual hardware limitations, considering the finite resolution delay line, the transmission delay τ n,u After discretization, the discretized time delay τ′ can be obtained n,u for:

[0190]

[0191] Therefore, the phase shift ψ generated by the delay line n,p for:

[0192] ψ n,u =2πf m τ′ n,u (29)

[0193] In the antenna structure based on a single-layer delay line, the phase of each antenna unit is jointly controlled by a frequency-independent phase shifter and a frequency-dependent delay line; therefore, when the frequency is f m When the phase of the pth antenna element in the uth subarray is n,u,p for:

[0194] ψ n,u,p =ψ n,p +ψ n,u (30)

[0195] Then the simulated precoding matrix of the single-layer delay line structure is The expression is:

[0196]

[0197] in, is the analog precoding vector of a single RF chain, expressed as:

[0198]

[0199] For the double - layer delay - line part of the hybrid single - and double - layer delay - line structure, the delay τ generated by the first - layer delay - line unit n,h is:

[0200] τ n,h =(h - 1)LP h T d sinθ k (33)

[0201] The delay τ generated by the second - layer delay - line unit connected to the first - layer delay - line unit n,l is:

[0202] τ n,l =(l - 1)P h T d sinθ k (34)

[0203] When 1≤U h ≤HL, the discrete delay expression obtained after discretization is:

[0204]

[0205] When HL + S h +1≤U h ≤H h L + S h , the discrete delay expression obtained after discretization is:

[0206]

[0207] For the single - layer delay - line part of the hybrid single - and double - layer delay - line structure, the delay τ generated by the s - th delay - line n,s is:

[0208] τ n,s =(s - 1)P h T d sinθ k (39)

[0209] The discrete delay expression τ′ n,s obtained after discretization is:

[0210]

[0211] In summary, when the frequency is f m , the phase ψ of the p - th antenna element in the u - th sub - array n,u,p is:

[0212]

[0213] Then, the analog precoding matrix of the hybrid single - and double - layer delay - line structure has the following expression:

[0214]

[0215] where, is the analog precoding vector of a single RF chain, and its expression is:

[0216]

[0217] Next, based on the equivalent channel matrix, a low - complexity zero - forcing precoding technique is used to design the digital precoding, thereby obtaining the digital precoding vector The specific process is as follows:

[0218] First, according to the channel vector h m,k and the analog precoding matrix A, the equivalent channel vector of the k - th user can be obtained as which is:

[0219]

[0220] Therefore, the equivalent channel matrix has the following expression:

[0221]

[0222] Using the low - complexity zero - forcing precoding scheme, the digital precoding matrix can be calculated as:

[0223]

[0224] In zero - forcing precoding, the precoding matrix is obtained by calculating the pseudo - inverse of the channel matrix. To ensure that the power of the transmitted signal is constant after precoding, the digital precoding vector needs to be normalized.

[0225] After normalization, the digital precoding vector of the k - th user is:

[0226]

[0227] Analysis of simulation results: The achievable sum - rate is used as the index to evaluate the system performance, and the system performance in different cases is analyzed through experimental simulation. The simulation parameters refer to Table 1.

[0228] Table 1 Simulation parameters

[0229]

[0230] First, in the antenna structure based on a single-layer delay line, the performance of the system is compared when the delay ranges of the delay lines are the same and different, so as to analyze the influence of the delay range of the delay line on the system performance. Then, the performance and hardware complexity of the system under the single-layer delay line scheme, the double-layer delay line scheme and the hybrid single-double layer delay line scheme are compared, thus verifying the advantages of the proposed scheme of the present invention. Finally, by adjusting the proportion of the single-layer delay line part in the hybrid single-double layer delay line scheme, the influence of different structural configurations on the system performance is analyzed.

[0231] Figure 3 Show the relationship between the sum rate and the signal-to-noise ratio for the single-layer delay line scheme in different cases. Set the number of delay lines as U = 32. In the figure, the sum rates of the single-layer delay line scheme in the ideal case (i.e., the delay lines are continuous), when the delay ranges of the delay lines are the same and different are compared. From Figure 3 it can be seen that among these single-layer delay line schemes in different cases, the performance of the system is the best when the delay lines are continuous, while the performance of the discrete delay lines decreases relatively. Specifically, when the signal-to-noise ratio is 20 dB, the sum rate of the discrete delay lines decreases by about 12% compared with the continuous delay lines. In addition, from Figure 3 it can also be observed that when the delay range of the discrete delay lines changes, the performance of the system only decreases slightly, but the reduction degree of the hardware complexity is λ1 / λ1 same ≈75.81%. Therefore, the delay range of the delay lines can be reduced by deploying delay lines with different delay ranges at different antenna positions, thereby reducing the hardware complexity and power consumption of the system to a certain extent.

[0232] Figure 4 Show the relationship between the sum rate and the signal-to-noise ratio for different delay line schemes, and these schemes all use finite-resolution delay lines with different delay ranges. Among them, the number of delay lines in the single-layer delay line scheme is U = 32, the number of the first-layer delay lines in the double-layer delay line scheme is H t = 8, and the number of the second-layer delay lines connected to each first-layer delay line unit is L t = 4. The number of delay lines in the single-layer part of the hybrid single-double layer delay line is S h = 16, the number of the first-layer delay lines in the double-layer part of the hybrid single-double layer delay line is H h = 4, and the number of the second-layer delay lines connected to each first-layer delay line unit is L = 4. Compared with the single-layer delay line scheme, the reduction degrees of the hardware complexity of the hybrid single-double layer delay line scheme and the double-layer delay line scheme are about λ h / λ1≈58.51% and λ2 / λ1≈29.79% respectively. From Figure 4It can be seen that the performance of the hybrid single / double-layer delay line scheme is better than that of the double-layer delay line scheme and is close to that of the single-layer delay line scheme. In addition, since the hybrid single / double-layer delay line scheme adopts a double-layer delay line structure at both ends, compared with the single-layer delay line scheme, the number of delay lines in the large delay range of this scheme is significantly reduced, thus significantly reducing the hardware complexity and power consumption. Through experimental simulation and comparative analysis, the proposed hybrid single / double-layer delay line scheme in the present invention can effectively reduce the hardware complexity and power consumption of the system at the cost of sacrificing a small amount of sum rate, verifying the superiority of the proposed scheme.

[0233] Figure 5 shows the relationship between the sum rate and the signal-to-noise ratio in the hybrid single / double-layer delay line scheme with different numbers of single-layer delay lines, where delay lines with different delay ranges are used. Considering three cases where the number of single-layer delay lines is S h =8, S h =16, S h =24, and the single-layer delay line scheme can be regarded as the case of S h =32. It can be seen from Figure 5 that as the proportion of the single-layer delay line part in the hybrid single / double-layer delay line scheme decreases, the sum rate of the hybrid single / double-layer delay line scheme also decreases. At the same time, the number of delay lines with a large range of delays and the hardware complexity also decrease accordingly. Specifically, compared with the single-layer delay line scheme, the degrees of reduction in hardware complexity of the hybrid single / double-layer delay line scheme in the cases of S h =8, S h =16, and S h =24 are approximately 36.17%, 58.51%, and 77.66% respectively. In addition, when S h =24, the performance of the hybrid single / double-layer delay line scheme is basically the same as that of the single-layer delay line scheme. Therefore, by adjusting the ratio of the single-layer delay line part to the double-layer delay line part in the hybrid single / double-layer delay line scheme, high performance of the system can be achieved with low hardware complexity.

[0234] This invention studies a subarray antenna structure based on a hybrid single- and double-layer delay line. First, the relationship between the antenna position and the delay range of the delay line is analyzed, and a method for deploying delay lines with different delay ranges according to different antenna positions is designed. This method can effectively reduce the delay range and hardware complexity of the delay lines in the middle part of the antenna. Then, to further reduce the number of delay lines with a large delay range, a hybrid single- and double-layer delay line scheme is proposed. This scheme uses a single-layer delay line structure in the middle part of the antenna that requires small time delays, and a double-layer delay line structure in the two end parts that require large time delays. Finally, based on the above scheme, an effective hybrid analog-digital precoding scheme is proposed. Among them, the analog precoding is jointly determined by the phase shifter and the delay line, and the digital precoding uses a low-complexity zero-forcing precoding technique. The simulation results show that compared with the traditional single-layer delay line scheme, the hybrid single- and double-layer delay line scheme not only has performance close to the former, but also significantly reduces its hardware complexity and power consumption.

[0235] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A terahertz antenna structure and precoding method based on a hybrid single- and double-layer delay line, characterized in that The steps are as follows: Step 1: Analyze the relationship between the antenna position and the delay range of the delay line based on the single-layer delay line structure, and design a brand-new delay line deployment scheme; Step 2: Design a structure based on a hybrid single- and double-layer delay line based on the brand-new delay line deployment scheme, that is, adopt a single-layer delay line structure in the middle part of the antennas that need to provide small time delays, and adopt a double-layer delay line structure in the two end parts that need to provide large time delays; Step 3: Calculate the maximum time delay of the hybrid single- and double-layer delay line structure, and quantify the hardware complexity of the hybrid single- and double-layer delay line structure based on the maximum time delay; Step 4: Design a hybrid analog-digital precoding scheme based on the hybrid single- and double-layer delay line structure. Among them, the analog precoding is jointly determined by the phase shifter and the delay line, and the digital precoding is determined by using a low-complexity zero-forcing precoding technique.

2. The terahertz antenna structure and precoding method based on a hybrid single- and double-layer delay line according to claim 1, wherein The single-layer delay line structure is: there is only one radio frequency chain at the base station, and this radio frequency chain serves a single-antenna user; the uniform linear array at the base station contains N antennas, and the radio frequency chain is connected to U delay lines; Adopt a sub-connection structure, each sub-array contains P = N / U antennas, and the azimuth angle of the single-antenna user is θ0 ∈ [-π / 2, π / 2].

3. The terahertz antenna structure and precoding method based on a hybrid single- and double-layer delay line according to claim 2, characterized in that The hybrid single- and double-layer delay line structure is as follows: One RF chain is equipped at the base station to serve a single-antenna user; the number of antennas is N, the number of delay lines in the first layer of the double-layer delay line part is H h = 2H, each unit of the first-layer delay line is connected to L second-layer delay lines, and the number of delay lines in the single-layer delay line part is S h = 2S, where H represents the number of delay elements at the left end of the first layer, and S represents the number of single-layer delay elements on the left side of the central axis; a sub-connection structure is adopted, and these delay lines evenly divide the antennas into U h = H h L + S h sub-arrays, each sub-array contains P h = N / U h antennas, and the azimuth angle of the user is θ0 ∈ [-π / 2, π / 2].

4. The terahertz antenna structure and precoding method based on a hybrid single- and double-layer delay line according to claim 3, wherein The method for determining the delay range of the delay line under the single-layer delay line structure is: In a single-layer delay line structure, the time delay difference between the first delay line and the \(u\)-th delay line is defined as \(\tau\). u , where \(u = 1, 2, \ldots, U\), then we have: τ u =(u - 1)PT d sinθ0 (1) where T d = d / c is the time delay between adjacent antennas; Considering the time delay τ u should be greater than 0, then the time delay of the u-th delay line can be optimized as follows: Therefore, in the traditional single-layer delay line structure, the maximum time delay of the delay line is (U-1)PT d , and the delay range is τ u ∈ [0, (U-1)PT d ; Under the two extreme cases of the user azimuth angle θ0 = -π / 2 and θ0 = π / 2, analyze the maximum time delay that each delay line needs to provide in the single-layer delay line scheme; When θ0 = -π / 2, according to formula (2), the time delay τ that the delay line connecting the u-th subarray needs to provide can be obtained as follows u =(1 - u)PT d sinθ0; Therefore, the time delay vector that the U delay lines need to provide is as follows: When θ0 = π / 2, from formula (2), the time delay τ that the time delay line connecting the u-th sub-array needs to provide can be obtained as follows u =(U - u)PT d sinθ0; Therefore, the time delay vector that the U time delay lines need to provide is as follows: To sum up, when the number of delay lines U is even, the maximum time delay vector that the delay lines connecting U sub-arrays need to provide in the single-layer delay line scheme is: Therefore, the delay range of the u-th delay line is [0, τ max (u)]; From the above formula, the discrete delay set of the u-th delay line in the antenna structure based on the single-layer delay line can be obtained as: τ u ∈ Γ u = {0, D, 2D, ..., τ max (u)D} (6) where D = PT d represents the time delay step size; In an antenna structure based on a single-layer delay line, not all delay lines need to provide the maximum time delay (U-1)PT d ; in fact, the maximum time delay required for the delay lines in the middle part of the antenna is relatively small, while that required for the delay lines at both ends is relatively large; based on this, a new delay line deployment scheme is designed, that is, delay lines with different delay ranges are deployed according to different antenna positions.

5. The terahertz antenna structure and precoding method based on a hybrid single- and double-layer delay line according to claim 4, wherein The method for determining the delay range of the delay line under the hybrid single- and double-layer delay line structure is: For the double-layer delay line part of the hybrid single- and double-layer delay line structure, the transmission delay generated by the first-layer delay line unit is: τ h =(h - 1)LP h T d sinθ0 (7) Among them, the left - hand double - layer delay line \(h = 1,\cdots,H\), and the right - hand double - layer delay line \(h=U - L - H + 1,\cdots,U - L\); h / L - H + 1,\cdots,U h / L; The transmission delay generated by the second-layer delay line unit is: τ l =(l - 1)P h T d sinθ0, l = 1, ..., L (8) Therefore, the total transmission delay generated by the delay lines in the double-layer delay line part is: τ h,l = [(h - 1)L+(l - 1)]P h T d sinθ0 (9) For the single-layer delay line part of the hybrid single- and double-layer delay line structure, the transmission delay generated by the s-th delay line unit is: τ s =(s - 1)P h T d sinθ0 (10) where s = HL + 1,..., HL + S h ; Considering that the time delay is greater than 0, therefore, for the double-layer delay line part, the time delay of the l-th second-layer delay line connected to the h-th first-layer delay line should be modified as: For the single-layer delay line part, the time delay of the s-th delay line should be modified as: Divide the hybrid single- and double-layer delay line structure into three parts: the left-end double-layer delay line, the middle single-layer delay line, and the right-end double-layer delay line. Referring to the analysis process of the single-layer delay line structure, when θ0 = -π / 2, the time delay vector is: When θ0 = π / 2, the time delay vector is: To sum up, the maximum time delay vector of the hybrid single- and double-layer delay line structure is: Therefore, the delay range of the delay line where the u-th sub-array is located is [0, τ hmax (u)]; From the above formula, for the hybrid single- and double-layer delay line structure, when h = 1,..., H, the discrete delay set of the double-layer delay line part is: When h = U h / L - H + 1,..., U h / L, the discrete delay set of the double - layer delay line part is as follows: The discrete delay set of the s-th delay line in the single-layer delay line part is: τ s ∈ Γ s = {0, D, 2D, ..., τ hmax (s)D} (20).

6. The terahertz antenna structure and precoding method based on a hybrid single- and double-layer delay line according to claim 5, characterized in that The method for quantifying the hardware complexity of the hybrid single- and double-layer delay line structure is: Taking a radio frequency chain as an example to analyze the hardware complexity of the system, define λ to numerically measure the hardware complexity of the system; for a single-layer delay line structure with the same delay range of the delay line, its hardware complexity is expressed as: For a single-layer delay line structure with different delay ranges of the delay line, its hardware complexity is expressed as: Therefore, the reduction degree of the hardware complexity of the single-layer delay line structure with different delay ranges compared to that with the same delay range is expressed as: For a hybrid single- and double-layer delay line structure with different delay ranges of the delay line, its hardware complexity is expressed as: Assume that each RF chain in the double-layer delay line scheme is connected to H t first-layer delay lines, and each first-layer delay line unit is connected to L t second-layer delay lines. Then, for the double-layer delay line structures with different delay ranges of the delay lines, its hardware complexity is expressed as: Similarly, when the delay range is different, compared with the single-layer delay line structure, the degrees of reduction in hardware complexity of the hybrid single- and double-layer delay line structure and the double-layer delay line scheme are λ h / λ1 and λ2 / λ1, respectively.

7. The terahertz antenna structure and precoding method based on a hybrid single- and double-layer delay line according to claim 6, characterized in that The hybrid analog-digital precoding scheme designed based on the hybrid single- and double-layer delay line structure is as follows: According to the array response vector f(f c at the center frequency f c , θ k ), the frequency-independent phase shift ψ n,p generated by the phase shifter unit is obtained as follows: ψ n,p = 2πf c (p - 1)T d sinθ k (26) where n = 1, 2,..., N RF , for the single-layer delay line structure p = 1,..., P, and for the hybrid single-double layer delay line structure p = 1,..., P h ; for the single-layer delay line structure, the frequency-dependent delay τ generated by the delay line where the u-th subarray is located n,u is:[[]]END]] τ n,u =(u - 1)PT d sinθ k (27) Based on the actual hardware limitations, considering a finite-resolution delay line, for the transmission delay τ n,u perform discretization processing to obtain the discretized delay τ′ n,u as follows: Therefore, the phase shift ψ generated by the delay line n,p is as follows: ψ n,u = 2πf m τ′ n,u (29) In the antenna structure based on a single-layer delay line, the phase of each antenna element is jointly regulated by a frequency-independent phase shifter and a frequency-dependent delay line; thus, when the frequency is f m , the phase ψ n,u,p of the p-th antenna element in the u-th subarray is: ψ n,u,p = ψ n,p + ψ n,u (30) The analog precoding matrix of the single-layer time delay line structure has the following expression: Among them, is the analog precoding vector of a single radio frequency chain, and the expression is: For the double-layer delay line part of the hybrid single / double-layer delay line structure, the delay τ generated by the first-layer delay line unit n,h is as follows: τ n,h =(h - 1)LP h T d sinθ k (33) The delay τ generated by the second-layer delay line unit connected to the first-layer delay line unit n,l is as follows: τ n,l =(l - 1)P h T d sinθ k (34) When 1 ≤ U h ≤ HL, the discrete time delay expression obtained after discretization processing is as follows: When HL + S h + 1 ≤ U h ≤ H h L + S h The discrete delay expression obtained after discretization processing is as follows: For the single-layer delay line part of the hybrid single- and double-layer delay line structure, the delay τ generated by the s-th delay line n,s is as follows: τ n,s =(s - 1)P h T d sinθ k (39) The discrete time delay expression τ′ obtained after discretization processing n,s is as follows: In summary, when the frequency is f m the phase ψ n,u,p of the p-th antenna element in the u-th sub-array is: The analog precoding matrix of the hybrid single- and double-layer time delay line structure has the following expression: Among them, is the analog precoding vector of a single radio frequency chain, and the expression is: Finally, based on the equivalent channel matrix, a low-complexity zero-forcing precoding technique is employed to design digital precoding, thereby obtaining the digital precoding vector

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