Code generation method and device, equipment and medium

Abstract

The embodiment of the invention provides a code generation method and device, equipment and a medium. The method comprises the steps of obtaining a hardware design file corresponding to a to-be-verified function module of a target chip; extracting interface information corresponding to an input interface and an output interface of the to-be-verified module from the hardware design document; based on the function verification code template, the interface information of the reference module and the interface information of the to-be-verified function module, verification codes for the to-be-verified function module are generated, and the reference module and the to-be-verified module have the same function. The verification code is used for controlling the input interfaces of the to-be-verified function module and the reference module to input the same excitation so as to verify whether the function of the to-be-verified function module is normal or not based on the output results of the output interfaces of the to-be-verified function module and the reference module. By adopting the method, the program code for verifying the function of the to-be-verified function module can be automatically generated, so that the verification efficiency of the target chip is improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and more specifically, to a code generation method, apparatus, device, and medium. Background Art

[0002] Currently, processors are widely used in multiple fields such as communications and industrial automation. As the scale of processor chips continues to expand, their application scenarios are also constantly evolving, which means that the number of modules inside the processor chip and the size of the circuit netlist are also increasing, and the verification workload is also increasing. How to efficiently perform functional verification on each functional module of the processor has become an important issue in the design and development of processor chips. In related technologies, the construction and debugging of the verification platform usually takes up a considerable amount of time and cost. As the number of modules inside the processor chip and the size of the circuit netlist increase, manually building the verification platform requires a lot of time, especially when co-verifying multiple modules, the debugging difficulty increases significantly. Verification engineers need to manually write test cases, configure stimulus signals and compare output results, which leads to inefficient verification of the processor. Summary of the Invention

[0003] In view of this, the embodiments of the present application propose a code generation method, apparatus, device and medium, which can automatically generate program code for verifying the functions of the functional module to be verified, so as to improve the verification efficiency of the target chip.

[0004] In the first aspect, an embodiment of the present application provides a code generation method, the method comprising: obtaining a hardware design file corresponding to a functional module to be verified of a target chip; extracting interface information corresponding to the input interface and output interface of the module to be verified from the hardware design document; generating a verification code for the functional module to be verified based on a functional verification code template, the interface information of a reference module, and the interface information of the functional module to be verified, wherein the reference module has the same function as the module to be verified, and the verification code is used to control the input interfaces of the functional module to be verified and the reference module to input the same stimulus respectively, so as to verify whether the function of the functional module to be verified is normal based on the output results of the output interfaces of the functional module to be verified and the reference module.

[0005] In the second aspect, an embodiment of the present application provides a code generation device, which includes: a file acquisition module for acquiring a hardware design file corresponding to a functional module to be verified of a target chip; an information extraction module for extracting interface information corresponding to the input interface and output interface of the module to be verified from the hardware design document; a code generation module for generating a verification code for the functional module to be verified based on a functional verification code template, the interface information of a reference module, and the interface information of the functional module to be verified, wherein the reference module has the same function as the module to be verified, and the verification code is used to control the input interfaces of the functional module to be verified and the reference module to input the same stimulus respectively, so as to verify whether the function of the functional module to be verified is normal based on the output results of the functional module to be verified and the reference module.

[0006] In one embodiment, the information extraction module includes a parsing submodule, a region determination submodule, and an information acquisition submodule. The parsing submodule is used to parse the hardware design document to obtain target keywords, wherein the target keywords include grammatical keywords used to identify interfaces or parameter definitions in the hardware design document; the region determination submodule is used to locate the interface area and the parameter definition area corresponding to the interface area in the hardware design document based on the target keywords; and the information acquisition submodule is used to parse each interface area and the parameter definition area corresponding to the interface area to obtain the interface type and interface information of the interface, wherein the interface type is used to indicate whether the interface to which it belongs includes an input interface or an output interface.

[0007] In one embodiment, the code generation module includes a format conversion submodule and a code generation submodule. The format conversion submodule is configured to convert the interface information of the input interface and the output interface of the reference module into a first interface description file in a structured data format; and convert the interface information of the input interface and the output interface of the module to be verified into a second interface description file in a structured data format; and the code generation submodule is configured to generate verification code for the functional module to be verified based on the functional verification code template, the first interface description file, and the second interface description file.

[0008] In one embodiment, the verification code includes top-level code and verification result analysis layer code. The top-level code is configured to instantiate the functional module to be verified and the reference module in the verification platform, control the input interfaces of the instantiated functional module to be verified and the reference module to input the same stimulus, and obtain the output results of the output interfaces of the functional module to be verified and the reference module. The verification platform includes a scoreboard component and an assertion checking component. The verification result analysis layer code is configured to call the scoreboard component to compare the output results of the output interfaces of the functional module to be verified and the reference module based on preset comparison rules to obtain a first verification result. The verification result analysis layer code is configured to call the assertion checking component in the verification platform to check whether the output result of the functional module to be verified complies with preset assertion rules to obtain a second verification result. The target verification result for the module to be verified is generated based on the first and second verification results.

[0009] In one possible implementation, the verification code also includes interface layer code and transaction layer code; the interface layer code is used to declare the input interface and output interface of the functional module to be verified; the transaction layer code is used to abstract the signals transmitted by the input interface and output interface of the functional module to be verified and the reference module into a transaction class.

[0010] In one possible implementation, the code generation apparatus further includes a result sending module, configured to send the target verification result to a terminal device associated with the verification platform.

[0011] In one embodiment, the target chip includes a field programmable gate array.

[0012] In a third aspect, an embodiment of the present application provides an electronic device comprising a processor and a memory; one or more programs are stored in the memory and configured to be executed by the processor to implement the above method.

[0013] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, in which program code is stored, wherein the above method is executed when the program code is executed by a processor.

[0014] In a fifth aspect, embodiments of the present application provide a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device retrieves the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the above-described method.

[0015] The embodiments of the present application provide a code generation method, device, equipment and medium. The method includes: obtaining the hardware design file corresponding to the target chip's function module to be verified; extracting the interface information corresponding to the input interface and output interface of the module to be verified from the hardware design document; generating a verification code for the function module to be verified based on a function verification code template, the interface information of a reference module and the interface information of the function module to be verified, wherein the reference module has the same function as the module to be verified, and the verification code is used to control the input interfaces of the function module to be verified and the reference module to input the same stimulus respectively, so as to verify whether the function of the function module to be verified is normal based on the output results of the output interfaces of the function module to be verified and the reference module. By adopting the above method, the input / output interface information of the module to be verified is first extracted from the hardware design file corresponding to the function module to be verified, without the need to manually analyze the signal list. Thereafter, based on the predefined function verification code template, the complete verification code is automatically generated, which can significantly reduce the manual coding time. In addition, by introducing a reference module during the code generation process, the test code finally generated can verify that the code controls the module to be verified and the reference module to receive the same stimulus, and automatically compares the output results of the two. There is no need to write comparison logic for each module separately, so that the output results of the verification code have been compared through automated scripts, reducing manual inspection errors, improving verification reliability, and improving the verification efficiency and quality of the functional modules to be verified on the target chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 A schematic diagram of a code generation method according to an embodiment of the present invention is shown;

[0018] Figure 2 Shown Figure 1 Flow chart of step S120;

[0019] Figure 3 Shown Figure 1 Flow chart of step S130;

[0020] Figure 4 Another flowchart of a code generation method provided by an embodiment of the present application is shown;

[0021] Figure 5A schematic diagram of a hardware-related document provided in an embodiment of the present application is shown;

[0022] Figure 6 A schematic diagram of structured data provided by an embodiment of the present application is shown;

[0023] Figure 7 A top-level code provided by an embodiment of the present application is shown;

[0024] Figure 8 An interface code provided by an embodiment of the present application is shown;

[0025] Figure 9 A transaction layer code proposed in an embodiment of the present application is shown;

[0026] FIG10( a ) shows a code corresponding to a scoreboard group price proposed in an embodiment of the present application;

[0027] FIG10( b ) shows the code corresponding to an assertion check group valence proposed in an embodiment of the present application;

[0028] Figure 11 A connection block diagram of a code generation device proposed in an embodiment of the present application is shown;

[0029] Figure 12 A structural block diagram of an electronic device for executing the method of an embodiment of the present application is shown. DETAILED DESCRIPTION

[0030] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art.

[0031] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner.In the following description, many specific details are provided so as to provide a full understanding of the embodiments of the present application. However, it will be appreciated by those skilled in the art that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps etc. can be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0032] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically separate entities. That is, these functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0033] The flowcharts shown in the accompanying drawings are for illustrative purposes only and do not necessarily include all contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may be decomposed, while others may be combined or partially combined. Therefore, the actual execution order may vary depending on the actual situation.

[0034] It should be noted that the term "plurality" used in this document refers to two or more. "And / or" describes a relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A alone, A and B together, or B alone. The character " / " generally indicates an "or" relationship between the associated objects.

[0035] It should also be noted that in the embodiments of the present application, the collection, use, processing and storage of application information are all subject to the user's permission and must comply with the regulations of the region.

[0036] Figure 1 The present application specifically provides a code generation method, which can be applied to an electronic device, which can be a terminal device or a server. The method includes:

[0037] Step S110: Obtain the hardware design file corresponding to the functional module to be verified of the target chip.

[0038] Among them, the target chip can be any one of the CPU (Central Processing Unit), GPU (Graphics Processing Unit), DSP (Digital Signal Processor), FPGA (Field-Programmable Gate Array), etc., which can support the definition of its functional modules through hardware description language (Verilog / VHDL).

[0039] In one possible implementation of the present application, the target chip includes a field programmable gate array (FPGA). FPGA is a semiconductor device that can be reprogrammed to implement the logic circuit required by the user and is widely used in many fields such as communications and industrial automation.

[0040] The functional module to be verified is a functional subunit in the target chip that requires independent verification. It has characteristics such as functional independence and clear interface names. Functional independence means that it can complete specific tasks (such as data encryption, signal filtering, and bus arbitration). Interface clarity refers to characteristics such as having clear input / output interfaces (such as data buses and control signals).

[0041] The functional module to be verified may be any one of a security detection functional module, a computing functional module, a storage control functional module, and the like.

[0042] The hardware design file is a design implementation file that describes the functional module to be verified. It may include: RTL code (Register-Transfer Level), constraint files, and configuration parameters, etc. Among them, the RTL code is used to define the module's input / output interface, internal logic and state machine, constraint files, etc.

[0043] Step S120: extracting interface information corresponding to the input interface and the output interface of the module to be verified from the hardware design document.

[0044] Step S120 may include keyword scanning of the hardware design document, where keywords include input, output, inout, parameter, and localparam. By scanning the keywords in the hardware code, the port and parameter definition areas can be located, the parameters in the areas can be parsed, and unidirectional and multidirectional ports can be distinguished. Simultaneously, the signal declarations within the interface are parsed line by line to extract the signal name, type, and bit width.

[0045] For details, please refer to Figure 2 As shown, the above step S120 includes:

[0046] Step S122: Parse the hardware design document to obtain target keywords, where the target keywords include grammatical keywords used to identify interfaces or parameter definitions in the hardware design document.

[0047] Specifically, the hardware design document may be parsed based on a predefined keyword list to extract target keywords from the hardware design document.

[0048] Step S124: Locate the interface area and the parameter definition area corresponding to the interface area in the hardware design file according to the target keyword.

[0049] Specifically, the line containing the target keyword and the adjacent code block can be used to determine the interface area and the parameter definition area corresponding to the interface area. For example, the port list range can be the content between the first (to the corresponding) after the module declaration; the parameter declaration range can be the parameter or localparam keyword and the subsequent semicolon or next keyword.

[0050] Step S126: Parse each of the interface areas and the parameter definition area corresponding to the interface area to obtain the interface type and interface information of the interface, wherein the interface type is used to indicate whether the interface includes an input interface or an output interface.

[0051] For example, by parsing the interface area, the port direction and signal properties can be captured. Subsequently, by parsing the parameter definition area corresponding to the interface area, the configuration value defined by parameter / localparam can be extracted and bound to the port width or mode. Finally, implicit signals (such as valid and ready) are supplemented according to the protocol rules. The bidirectional port is split into independent input and output control signals (such as data_in, data_out, data_oe). The interface information finally obtained may include interface-related information such as interface name, signal list, direction (input, output) and signal type.

[0052] It is worth mentioning that before performing keyword scanning on the hardware design document (i.e., before executing step S122), code normalization processing can be performed first, such as removing comments (such as / / , / ** / ) and irrelevant blank characters. Expand the macro definition (such as define WIDTH 32) to ensure that the port declaration is visible. Thereafter, the module declaration area of ​​the target module is located using a regular expression or a syntax analyzer. So that when the hardware design document is subsequently scanned, only the module declaration area of ​​the target module is scanned to improve the accuracy of the interface information corresponding to the input interface and output interface of the module to be verified.

[0053] Step S130: generating a verification code for the function module to be verified based on the function verification code template, the interface information of the reference module and the interface information of the function module to be verified.

[0054] In which, the reference module has the same function as the module to be verified, and the verification code is used to control the input interfaces of the functional module to be verified and the reference module to input the same stimulus respectively, so as to verify whether the function of the functional module to be verified is normal based on the output results of the output interfaces of the functional module to be verified and the reference module.

[0055] Among them, the reference module is a golden model used to simulate the expected behavior of the module to be verified in the verification environment. It implements the same functions as the functional module to be verified (such as the same algorithm, protocol or logic) and is usually written in a higher-level abstraction language (such as C / C++, SystemVerilog behavioral level modeling) to avoid sharing code with the functional module to be verified.

[0056] Wherein, function verification code template is a set of predefined, parameterizable verification environment framework code, and it has standardized structure, and the function verification code template adopted on different verification environments or verification platforms can be different.For example, function verification code template can be based on industry verification methodology (as UVM, Universal Verification Methodology, universal verification methodology) design, comprises fixed modules such as top layer, interface layer, transaction layer, test layer.In function verification code template, also be configured with placeholder, as, reserve the insertion position of variables such as interface signal name, bit width, protocol rule, it can move in UVM verification environment to treat verification function module and verify.

[0057] The above step S130 may be to extract parameters corresponding to the placeholders from the interface information of the reference module and the interface information of the functional module to be verified based on the placeholders in the functional verification code template and add them to the functional verification code template to obtain the verification code for the functional module to be verified.

[0058] To facilitate extracting parameters corresponding to the placeholders from the interface information of the reference module and the interface information of the functional module to be verified and adding them to the functional verification code template, in one embodiment of the present application, the above step S130 includes:

[0059] Step S132: converting the interface information of the input interface and output interface of the reference module into a first interface description file in a structured data format; converting the interface information of the input interface and output interface of the module to be verified into a second interface description file in a structured data format.

[0060] A structured data format is a standardized, machine-readable form of data organization that clearly describes the properties and relationships of module interfaces. In this application, the structured data format is used to store interface information (such as signal name, bit width, direction, clock domain, etc.) of the reference module and the module to be verified, so that verification code can be automatically generated later.

[0061] In this application, structured data formats include, but are not limited to, JSON (JavaScript Object Notation) key-value pairs, XML (eXtensible Markup Language), or YAML (YAML Ain't Markup Language, a human-readable data serialization format). It can also be automatically formatted based on actual needs.

[0062] The above step S132 can be to use regular expressions or dedicated parsing tools (such as Verilog parsing library pyverilog) to extract the interface information of the input interface and output interface of the reference module, and map them to structured fields to obtain a first interface description file; similarly, a second interface description file can be obtained.

[0063] Step S134: generating a verification code for the functional module to be verified based on the function verification code template, the first interface description file, and the second interface description file.

[0064] Specifically, according to the placeholder of the function verification code template, the corresponding fields (such as signal name, bit width) can be extracted from the first interface description file and the second interface description file respectively and dynamically filled into the placeholder of the function verification code template response to generate a complete verification code.

[0065] Since the structured data format unifies the representation of module interfaces, so that during the verification code generation process, the data corresponding to the placeholder of the required functional verification code template can be quickly and accurately extracted from the description file, the above-mentioned steps S132 and S134 can effectively improve the generation efficiency and accuracy of the verification code.

[0066] It's worth noting that when the functional module under verification and the reference module receive the same stimulus, the reference module's output is identical to the expected output of the functional module under verification. Therefore, the reference module serves as a reference for correct functionality, and its output represents the expected result; the output of the functional module under verification represents the actual result. By comparing the two, design errors in the functional module under verification can be identified.

[0067] Adopt the above-mentioned method of the present application, first by from the hardware design file (such as RTL code or netlist) corresponding to the functional module to be verified, extract the input / output interface information of the module to be verified, without manually analyzing the signal list. Thereafter, based on predefined functional verification code template, automatically generate complete verification code (such as Testbench, stimulus generation logic, output comparison logic, etc.), significantly reduce manual coding time. In addition, in the process of generating code, by introducing reference module (such as known functional correct model), make the test code that finally generates be able to verify that code can control the module to be verified and reference module to receive the same stimulus, and automatically compare the output results of the two, without writing comparison logic separately for each module, make the output result of verification code have been compared by automated script, reduce manual inspection error, improve verification reliability, improve verification efficiency and quality of the functional module to be verified of target chip.

[0068] In one possible implementation, if the functional verification code template is obtained based on UVM design, the verification code may include top-level code and verification result analysis layer code. The top-level code is used to instantiate the functional module to be verified and the reference module in the verification platform, control the input interfaces of the instantiated functional module to be verified and the instantiated reference module to input the same stimulus, and obtain the output results of the output interfaces of the functional module to be verified and the reference module, wherein a scoreboard component and an assertion check component are deployed in the verification platform; the verification result analysis layer code is used to call the scoreboard component to compare the output results of the output interfaces of the functional module to be verified and the reference module based on preset comparison rules to obtain a first verification result; and call the assertion check component in the verification platform to check whether the output result of the functional module to be verified meets the preset assertion rules to obtain a second verification result; and generate a target verification result for the module to be verified based on the first verification result and the second verification result.

[0069] Specifically, the sub-board component compares the output results of the output interfaces of the functional module to be verified and the reference module periodically based on preset comparison rules to obtain a first verification result indicating the difference between the reference module and the functional module to be verified; the assertion component is used to check the protocol compliance and / or data integrity of the functional module to be verified to obtain a second verification result indicating the protocol compliance and / or data integrity of the functional module to be verified. The above-mentioned generation of the target verification result for the module to be verified based on the first verification result and the second verification result can specifically be to merge the first verification result and the second verification result to obtain the target verification result, or to perform fault location based on the first verification result and the second verification result to obtain a target verification result including a fault location result.

[0070] In the case where the verification code includes top-level code and analysis-level code, the verification code verifies the functional module to be verified so that the instantiated functional module to be verified and the instantiated reference module run under exactly the same stimulus, thereby eliminating verification errors caused by output differences. In addition, since the scoreboard component compares the outputs of the two according to preset rules (such as cycle by cycle and tolerance error range), and checks the output of the functional module to be verified through the assertion check component, it is possible to verify whether the logic of the functional module to be verified is consistent with that of the reference module, and to check hardware behaviors such as timing and interference, thereby accurately locating errors. For example, when the first verification result indicates a comparison error, it is determined that there may be an algorithm defect problem, and when the second verification result indicates an abnormality, there may be a timing violation or protocol abnormality. In addition, when the target verification result is obtained through the first verification result and the second verification result, a multi-dimensional inspection of the module to be verified can be achieved, which can effectively improve the accuracy of the verification result of the functional module to be verified.

[0071] In this embodiment, optionally, the verification code also includes an interface layer code and a transaction layer code; the interface layer code is used to declare the input interface and output interface of the functional module to be verified; the transaction layer code is used to abstract the signals transmitted by the input interface and output interface of the functional module to be verified and the reference module respectively into a transaction class.

[0072] By setting the interface layer code in the test code, since the interface layer code can be used to declare the input interface and output interface of the functional module to be verified, the interface of the module to be verified can be decoupled from the verification platform, so that when multiple modules to be verified reuse the same input interface and / or output interface, the input interface and / or output interface can be reused in different test scenarios. By setting the transaction layer code in the test code, and the transaction layer code is used to abstract the signals transmitted by the input interface and output interface of the functional module to be verified and the reference module respectively into a transaction class, so that data transmission (stimulus and output results) can be transmitted at the transaction level, avoiding direct dependence on the signal interface. In addition, the above-mentioned physical class can also be registered in the verification platform factory (factory) to facilitate the use of the factory mechanism.

[0073] In one embodiment, the method further comprises:

[0074] Step S140: Use the verification code to instantiate the functional module to be verified and the reference module in the verification platform, control the input interfaces of the instantiated functional module to be verified and the instantiated reference module to input the same stimulus respectively, obtain the output results of the output interfaces of the functional module to be verified and the reference module respectively, and obtain the target verification result for the functional module to be verified based on the output result.

[0075] It is worth mentioning that verification code is usually deployed on a verification platform as part of a verification platform, which can be used to provide automated operation while performing result analysis and debugging.

[0076] In one possible implementation, the above-mentioned step S140 includes: using the top-level code to instantiate the functional module to be verified and the reference module in the verification platform, controlling the input interfaces of the instantiated functional module to be verified and the instantiated reference module to input the same stimulus respectively, and obtaining the output results of the output interfaces of the functional module to be verified and the reference module.

[0077] The verification result analysis layer code is used to call the scoreboard component to compare the output results of the output interfaces of the functional module to be verified and the reference module based on preset comparison rules to obtain a first verification result; and the assertion check component in the verification platform is called to check whether the output result of the functional module to be verified meets the preset assertion rules to obtain a second verification result; and a target verification result for the module to be verified is generated based on the first verification result and the second verification result.

[0078] By controlling the input interfaces of the instantiated functional module to be verified and the instantiated reference module to input the same stimulus respectively, the instantiated functional module to be verified and the instantiated reference module are operated under exactly the same stimulus, eliminating the verification error caused by the output difference. In addition, since the scoreboard component compares the outputs of the two according to preset rules (such as cycle by cycle, tolerance error range), and the output of the functional module to be verified is checked by the assertion check component, it is possible to verify that the logic of the functional module to be verified is consistent with that of the reference, and to check the hardware behavior such as timing and reference, so as to accurately locate the error. For example, when the first verification result indicates a comparison error, it is determined that there may be an algorithm defect problem, and when the second verification result indicates an abnormality, there may be a timing violation or protocol anomaly. Based on the above, it can be seen that by adopting the method of the present application, an automated process can be realized to reduce manual intervention, thereby effectively speeding up the verification. Further, when the target verification result is obtained through the first verification result and the second verification result, a multi-dimensional inspection of the module to be verified can be achieved, which can effectively improve the accuracy of the verification result of the functional module to be verified.

[0079] For example, taking the target chip as FPGA, Figure 5 The initial interface definition of the module to be verified carried in the hardware design document of the module to be verified presented in RTL code is shown, including input (clk, data_in), output (data_out) and parameter (WIDTH).

[0080] Figure 6The method extracts the interface information and CP parameters corresponding to the input interface and output interface of the module to be verified from the hardware design document and represents them in the form of structured data. The CP parameters are hardware parameters used to dynamically configure module behavior in FPGA design. They are used to adjust the module's operating mode, data bit width, timing, etc. without modifying the RTL code, and enable / disable specific functions as needed, thereby saving FPGA logic resources. Figure 7 The top-level code in the verification code is used to instruct the instantiation of the functional module to be verified and the reference module. The input ports of the functional module to be verified and the reference module are connected to the same stimulus, and the output ports are connected to the scoreboard component and the assertion check component for result comparison and analysis. Figure 8 As shown, the interface layer code is shown. The input port is declared in the interface layer code for stimulus transmission. The output port of the function module to be verified and the reference module is declared in the output interface code, and the result is checked and compared. The output interfaces of the function module to be verified and the reference module are respectively connected to the scoreboard component and the output interface of the function module to be verified is connected to the assertion check component. Figure 9 As shown, the input and output ports are declared in the transaction layer code and registered in the factory, that is, the transaction layer code includes the input transaction layer code and the output transaction layer code; FIG10(a) shows the code corresponding to the scoreboard component, and FIG10(b) shows the code corresponding to the assertion detection component. Specifically, FIG10(a) and FIG10(b) obtain the target verification results for the functional module to be verified, including a first verification result obtained by using the verification result analysis layer code to call the scoreboard component to compare the output results of the output interfaces of the functional module to be verified and the reference module based on the preset comparison rules, and a second verification result obtained by calling the assertion checking component in the verification platform to check whether the output results of the functional module to be verified meet the preset assertion rules. The above process is all completed automatically by the script. By classifying and processing the module ports and parameters and generating a partial verification environment based on this, the time cost of the verification environment design stage is greatly reduced, and the integrity and accuracy of the environment code are improved, effectively solving the problem of low verification efficiency caused by the long time of setting up and debugging the verification platform during the current module function verification.

[0081] It should be understood that, although the steps in the flowcharts of the above embodiments are shown in sequence as indicated by the arrows, these steps are not necessarily performed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be performed in other orders. Moreover, at least a portion of the steps in the flowcharts of the above embodiments may include multiple steps or multiple stages, and these steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily to be performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0082] See also Figure 11 Another embodiment of the present application provides a code generation device 200, and the code generation device 200 includes: a file acquisition module 210, used to obtain the hardware design file corresponding to the functional module to be verified of the target chip; an information extraction module 220, used to extract the interface information corresponding to the input interface and output interface of the module to be verified from the hardware design document; a code generation module 230, used to generate a verification code for the functional module to be verified based on the functional verification code template, the interface information of the reference module and the interface information of the functional module to be verified, the reference module has the same function as the module to be verified, and the verification code is used to control the input interfaces of the functional module to be verified and the reference module to input the same stimulus respectively, so as to verify whether the function of the functional module to be verified is normal based on the output results of the functional module to be verified and the reference module.

[0083] In one embodiment, the information extraction module 220 includes a parsing submodule, a region determination submodule, and an information acquisition submodule. The parsing submodule is used to parse the hardware design document to obtain target keywords, wherein the target keywords include grammatical keywords used to identify interfaces or parameter definitions in the hardware design document; the region determination submodule is used to locate the interface area and the parameter definition area corresponding to the interface area in the hardware design document based on the target keywords; the information acquisition submodule is used to parse each interface area and the parameter definition area corresponding to the interface area to obtain the interface type and interface information of the interface, wherein the interface type is used to indicate whether the interface to which it belongs includes an input interface or an output interface.

[0084] In one embodiment, the code generation module 230 includes a format conversion submodule and a code generation submodule. The format conversion submodule is configured to convert the interface information of the input interface and output interface of the reference module into a first interface description file in a structured data format; and to convert the interface information of the input interface and output interface of the module to be verified into a second interface description file in a structured data format; and the code generation submodule is configured to generate verification code for the functional module to be verified based on the functional verification code template, the first interface description file, and the second interface description file.

[0085] In one possible implementation, the code generation device 200 also includes: a verification module, which is used to use the verification code to instantiate the functional module to be verified and the reference module in the verification platform, control the input interfaces of the instantiated functional module to be verified and the instantiated reference module to input the same stimulus respectively, obtain the output results of the output interfaces of the functional module to be verified and the reference module, and obtain the target verification result for the functional module to be verified based on the output result.

[0086] In one possible implementation, the verification code includes top-level code and verification result analysis layer code; a scoreboard component and an assertion checking component are deployed in the verification platform; the verification module is also used to use the top-level code to instantiate the functional module to be verified and the reference module in the verification platform, control the input interfaces of the instantiated functional module to be verified and the instantiated reference module to input the same stimulus respectively, and obtain the output results of the output interfaces of the functional module to be verified and the reference module respectively; and use the verification result analysis layer code to call the scoreboard component to compare the output results of the output interfaces of the functional module to be verified and the reference module based on preset comparison rules to obtain a first verification result; and call the assertion checking component in the verification platform to check whether the output result of the functional module to be verified meets the preset assertion rules to obtain a second verification result; and generate a target verification result for the module to be verified based on the first verification result and the second verification result.

[0087] In one possible implementation, the code generating apparatus 200 further includes a result sending module, configured to send the target verification result to a terminal device associated with the verification platform.

[0088] In one embodiment, the target chip includes a field programmable gate array.

[0089] Each module in the above-mentioned device can be implemented in whole or in part by software, hardware, or a combination thereof. Each of the above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory in the computer device in the form of software, so that the processor can call and execute the operations corresponding to each of the above modules. It should be noted that the device embodiment in this application corresponds to the aforementioned method embodiment. The specific principles in the device embodiment can be found in the contents of the aforementioned method embodiment, which will not be repeated here.

[0090] The following will be combined Figure 12 An electronic device 100 provided in this application is described.

[0091] See also Figure 12 Based on the method provided in the above embodiment, the embodiment of the present application also provides another electronic device 100 including a processor 102 that can execute the above method. The electronic device 100 can be a server or a terminal device.

[0092] The electronic device 100 further includes a memory 104 . The memory 104 stores a program capable of executing the contents of the aforementioned embodiments, and the processor 102 can execute the program stored in the memory 104 .

[0093] The processor 102 may include one or more cores for processing data and a message matrix unit. The processor 102 utilizes various interfaces and circuits to connect various components within the electronic device 100. It executes various functions and processes data within the electronic device 100 by running or executing instructions, programs, code sets, or instruction sets stored in the memory 104, and by accessing data stored in the memory 104. Optionally, the processor 102 may be implemented using at least one of the following hardware forms: a digital signal processing (DSP), a field-programmable gate array (FPGA), or a programmable logic array (PLA). The processor 102 may integrate one or a combination of a central processing unit (CPU), a graphics processing unit (GPU), and a modem. The CPU primarily processes the operating system, user interface, and application programs; the GPU is responsible for rendering and drawing display content; and the modem handles wireless communications. It is understandable that the above-mentioned modem may not be integrated into the processor 102, but may be implemented separately through a communication chip.

[0094] The memory 104 may include a random access memory (RAM) or a read-only memory (ROM). The memory 104 may be used to store instructions, programs, codes, code sets, or instruction sets. The memory 104 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for implementing at least one function, instructions for implementing the various method embodiments described below, and the like. The data storage area may also store data (e.g., parking location, environmental information, and images) acquired by the electronic device 100 during use.

[0095] The electronic device 100 may also include a network module and a screen. The network module is used to receive and send electromagnetic waves, realize the mutual conversion between electromagnetic waves and electrical signals, and thus communicate with a communication network or other devices, such as communicating with an audio playback device. The network module may include various existing circuit components for performing these functions, such as an antenna, a radio frequency transceiver, a digital signal processor, an encryption / decryption chip, a user identity module (SIM) card, a memory, and the like. The network module can communicate with various networks such as the Internet, an intranet, a wireless network, or communicate with other devices via a wireless network. The above-mentioned wireless network may include a cellular telephone network, a wireless local area network, or a metropolitan area network. The screen can display interface content and perform data interaction, such as displaying the aforementioned interface and triggering operations through the screen.

[0096] The embodiment of the present application also provides a structural block diagram of a computer-readable storage medium. The computer-readable storage medium stores program code, which can be called by a processor to execute the method described in the above method embodiment.

[0097] The computer-readable storage medium can be an electronic memory such as a flash memory, an EEPROM (Electrically Erasable Programmable Read-Only Memory), an EPROM, a hard disk, or a ROM. Alternatively, the computer-readable storage medium includes a non-volatile computer-readable storage medium. The computer-readable storage medium has storage space for program codes that execute any of the method steps in the above method. These program codes can be read from or written into one or more computer program products. The program code can be compressed, for example, in an appropriate form.

[0098] The present application also provides a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the methods described in the various optional implementations described above.

[0099] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A code generation method, characterized in that: The method comprises: Obtain the hardware design file corresponding to the functional module to be verified of the target chip; Extracting interface information corresponding to the input interface and output interface of the module to be verified from the hardware design document; Based on the function verification code template, the interface information of the reference module and the interface information of the function module to be verified, a verification code is generated for the function module to be verified. The reference module has the same function as the module to be verified. The verification code is used to control the input interfaces of the function module to be verified and the reference module to input the same stimulus respectively, so as to verify whether the function of the function module to be verified is normal based on the output results of the output interfaces of the function module to be verified and the reference module.

2. The method according to claim 1, characterized in that The step of extracting interface information corresponding to the input interface and the output interface of the module to be verified from the hardware design document includes: Parsing the hardware design document to obtain target keywords, wherein the target keywords include grammatical keywords used to identify interfaces or parameter definitions in the hardware design document; Locating the interface area and the parameter definition area corresponding to the interface area in the hardware design file according to the target keyword; Each interface area and the parameter definition area corresponding to the interface area are parsed to obtain the interface type and interface information of the interface, wherein the interface type is used to indicate whether the interface to which it belongs includes an input interface or an output interface.

3. The method according to claim 1, characterized in that The step of generating a verification code for the functional module to be verified based on the functional verification code template, the interface information of the reference module, and the interface information of the functional module to be verified includes: Converting the interface information of the input interface and the output interface of the reference module into a first interface description file in a structured data format; converting the interface information of the input interface and the output interface of the module to be verified into a second interface description file in a structured data format; Based on the function verification code template, the first interface description file and the second interface description file, a verification code for the function module to be verified is generated.

4. The method according to claim 1, wherein The verification code includes a top-level code and a verification result analysis layer code; The top-level code is used to instantiate the functional module to be verified and the reference module in the verification platform, control the input interfaces of the instantiated functional module to be verified and the instantiated reference module to input the same stimulus, and obtain output results of the output interfaces of the functional module to be verified and the reference module, wherein a scoreboard component and an assertion checking component are deployed in the verification platform; The verification result analysis layer code is used to call the scoreboard component to compare the output results of the output interfaces of the functional module to be verified and the reference module based on preset comparison rules to obtain a first verification result; and to call the assertion check component in the verification platform to check whether the output result of the functional module to be verified complies with the preset assertion rules to obtain a second verification result; and generate a target verification result for the module to be verified based on the first verification result and the second verification result.

5. The method according to claim 4, characterized in that The verification code also includes an interface layer code and a transaction layer code; The interface layer code is used to declare the input interface and output interface of the functional module to be verified; The transaction layer code is used to abstract the signals transmitted by the input interface and output interface of the functional module to be verified and the reference module into a transaction class.

6. The method according to claim 5, characterized in that The method further comprises: The target verification result is sent to a terminal device associated with the verification platform.

7. The method according to any one of claims 1 to 6, characterized in that The target chip includes a field programmable gate array.

8. A code generating device, characterized in that: The device comprises: A file acquisition module is used to obtain the hardware design file corresponding to the functional module to be verified of the target chip; An information extraction module is used to extract interface information corresponding to the input interface and output interface of the module to be verified from the hardware design document; A code generation module is used to generate verification code for the functional module to be verified based on a functional verification code template, the interface information of a reference module, and the interface information of the functional module to be verified. The reference module has the same function as the module to be verified. The verification code is used to control the input interfaces of the functional module to be verified and the reference module to input the same stimulus respectively, so as to verify whether the function of the functional module to be verified is normal based on the output results of the functional module to be verified and the reference module.

9. An electronic device, characterized in that: include: one or more processors; Memory; One or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, and the one or more programs are configured to perform the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores program code, and the program code can be called by a processor to execute the method according to any one of claims 1 to 7.

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