Code generation method and device, equipment and medium
By automatically generating verification code and utilizing hardware design files and functional verification code templates, the problem of low efficiency in processor chip module verification is solved, and efficient and reliable module verification is achieved.
CN120610706APending Publication Date: 2025-09-09SHENZHEN PANGO MICROSYST CO LTD
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Patent Information
- Application Number
- CN202510463955.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-14
- Publication Date
- 2025-09-09
AI Technical Summary
Technical Problem
In the existing technology, the verification efficiency of processor chip modules is low, and it is difficult to manually build a verification platform and debug, especially when multiple modules are collaboratively verified.
Method used
By automatically generating verification code, using hardware design files to extract the input and output interface information of the module to be verified, generating verification code based on the functional verification code template, introducing a reference module to automatically compare the output results, and reducing manual intervention.
Benefits of technology
It improves the efficiency and quality of processor chip verification, reduces manual coding time, and improves the reliability and accuracy of verification.
✦ Generated by Eureka AI based on patent content.
Abstract
The embodiment of the invention provides a code generation method and device, equipment and a medium. The method comprises the steps of obtaining a hardware design file corresponding to a to-be-verified function module of a target chip; extracting interface information corresponding to an input interface and an output interface of the to-be-verified module from the hardware design document; based on the function verification code template, the interface information of the reference module and the interface information of the to-be-verified function module, verification codes for the to-be-verified function module are generated, and the reference module and the to-be-verified module have the same function. The verification code is used for controlling the input interfaces of the to-be-verified function module and the reference module to input the same excitation so as to verify whether the function of the to-be-verified function module is normal or not based on the output results of the output interfaces of the to-be-verified function module and the reference module. By adopting the method, the program code for verifying the function of the to-be-verified function module can be automatically generated, so that the verification efficiency of the target chip is improved.
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