Semiconductor Devices

The semiconductor device addresses short-circuit resistance issues by employing specific semiconductor region configurations with varying impurity concentrations and geometries, enhancing resistance and reliability under high voltage conditions.

JP7765318B2Active Publication Date: 2025-11-06KK TOSHIBA +1
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Patent Information

Application Number
JP2022042059
Authority / Receiving Office
JP · JP
Patent Type
Patents
Current Assignee / Owner
Filing Date
2022-03-17
Publication Date
2025-11-06
Estimated Expiration
2042-03-17

AI Technical Summary

Technical Problem

Existing semiconductor devices face challenges in improving short-circuit resistance, which can lead to reduced reliability and increased on-resistance when subjected to high voltage conditions.

Method used

The semiconductor device incorporates specific semiconductor regions and electrodes with varying impurity concentrations and geometries, including a p-type semiconductor region with a longer lower width and an n-type semiconductor region formed along the gate insulating layer, to narrow the current path during short circuits, thereby enhancing short-circuit resistance while minimizing on-resistance.

Benefits of technology

This design improves short-circuit resistance and reduces on-resistance, ensuring stable operation under high voltage conditions and maintaining reliability even with miniaturized structures.

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Abstract

To provide a semiconductor device capable of improving short-circuit resistance.SOLUTION: A semiconductor device comprises a first electrode, a first semiconductor region, a gate electrode, a second semiconductor region of a second conductivity type, a third semiconductor region of the second conductivity type, a fourth semiconductor region of a first conductivity type, a fifth semiconductor region of the first conductivity type, and a second electrode. The first semiconductor region includes a first region of the first conductivity type. The gate electrode is provided on the first semiconductor region. The second semiconductor region faces the gate electrode in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region. The third semiconductor region is provided between the first semiconductor region and the second semiconductor region in the first direction. A width at a lower part of the third semiconductor region is longer than that at an upper part of the third semiconductor region. The fourth semiconductor region is provided between the third semiconductor region and the gate electrode, having an impurity concentration of the first conductivity type higher than that of the first region. The fifth semiconductor region is provided on the second semiconductor region.SELECTED DRAWING: Figure 1
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