Semiconductor equipment

The insulated gate semiconductor device addresses misalignment issues by using a specific planar pattern of embedded regions, ensuring consistent device performance and reducing on-resistance.

JP7916849B2Active Publication Date: 2026-09-08FUJI ELECTRIC CO LTD
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Patent Information

Application Number
JP2023137285
Authority / Receiving Office
JP · JP
Patent Type
Patents
Current Assignee / Owner
Filing Date
2023-08-25
Publication Date
2026-09-08
Estimated Expiration
2039-03-22

AI Technical Summary

Technical Problem

Trench gate type MOSFETs made from wide-bandgap semiconductors like silicon carbide face issues with misalignment between lower and upper embedded regions due to manufacturing processes, leading to variations in device characteristics and increased cell pitch.

Method used

The design incorporates a first conductivity type carrier transport layer with a second conductivity type lower embedded region and dispersed upper embedded regions, arranged in a specific planar pattern with intermittent placement, including an insulated gate structure that controls surface potential, to mitigate misalignment effects.

Benefits of technology

This configuration suppresses variations in device characteristics and prevents an increase in cell pitch, reducing on-resistance and enhancing the reliability of the semiconductor device.

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Abstract

To provide an insulated-gate semiconductor device capable of suppressing variation in device characteristics caused by displacement between relative positions of a lower embedded region and an upper embedded region around a trench bottom part derived from manufacturing steps while suppressing increase of a cell pitch.SOLUTION: A semiconductor device comprises: a carrier transfer layer of a first conductivity-type made of a semiconductor material of which the inhibition bandwidth is wider than that of silicon; a lower embedded region 4 of a second conductivity-type embedded in an upper part of the carrier transfer layer; a plurality of upper embedded regions 6a-6f of the second conductivity-type embedded dispersedly deposited on the lower embedded region 4; an injection control region of the second conductivity-type deposited on the upper embedded regions 6a-6f; and an insulation gate structure controlling a surface potential of the injection control region which is positioned on a sidewall of a trench 10. Therein, the trench 10 is stripe-shaped, the lower embedded region 4 includes a first stripe part 41 which is provided separately from the trench 10, and the plurality of upper embedded regions 6a-6f is respectively provided at intervals on the first stripe part 41.SELECTED DRAWING: Figure 3
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