A fan-out multi-chip packaging structure and preparation method thereof
By setting conductive posts and multi-layer chips in the fan-out multi-chip package structure, compact interconnection between multiple chips is achieved, solving the problem of difficulty in thinning of stacked packaging structures, and achieving a smaller package thickness and a more compact chip layout.
CN110444535BActive Publication Date: 2025-03-25SHANGHAI XIANFANG SEMICON CO LTD
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Patent Information
- Application Number
- CN201910689430.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2019-07-29
- Publication Date
- 2025-03-25
- Estimated Expiration
- 2039-07-29
AI Technical Summary
Technical Problem
The existing stacked packaging structure is difficult to thin the thickness of the multi-chip packaging structure, resulting in difficulty in reducing the thickness of the packaging body.
Method used
Adopting a fan-out multi-chip packaging structure, by setting a conductive post and mounting the first chip on the conductive post, and then directly setting the second chip on the first chip, interconnection between chips is achieved, and a third chip is provided on the rewiring layer to increase the number of chips and layout compactness.
Benefits of technology
The number of packages is reduced, the thickness of multi-chip packages is reduced, and the compactness of the package structure is improved.
✦ Generated by Eureka AI based on patent content.
Abstract
The present invention relates to the field of chip packaging, and specifically to a fan-out multi-chip packaging structure and a preparation method thereof, wherein the fan-out multi-chip packaging structure comprises: a redistribution layer; a first chip; a conductive column, one end of which is connected to the redistribution layer and the other end of which is connected to the first chip; a second chip, the second chip being arranged on the first chip and electrically connected to the first chip, the second chip being located between the redistribution layer and the first chip, and a packaging layer, which is arranged on the redistribution layer and is used to plastic-encapsulate the first chip, the conductive column and the second chip. By arranging the conductive column and mounting the first chip on the conductive column, the first chip has a certain height, and then by directly arranging the second chip on the first chip, the interconnection between the first chip and the second chip is realized. With such an arrangement, the interconnection between the two chips is realized in one package, the number of packages is reduced, and thus the thickness of the multi-chip package can be reduced.
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