Semiconductor Devices

By designing multi-layer metal structure pads in semiconductor devices, the problem that semiconductor devices in the prior art is difficult to achieve fine pad structure, and the connection reliability and electrical reliability with external electronic devices are improved.

CN110610913BActive Publication Date: 2025-03-25SAMSUNG ELECTRONICS CO LTD
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Patent Information

Application Number
CN201910508897.1
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Priority Date
2018-06-15
Filing Date
2019-06-13
Publication Date
2025-03-25
Estimated Expiration
2039-06-13

AI Technical Summary

Technical Problem

Under the trend of miniaturization, it is difficult to achieve fine pad structures in existing semiconductor devices, which affects the reliability of electrical connection with other semiconductor devices or printed circuit boards.

Method used

A semiconductor device is designed, including a conductive pattern, a passivation layer and a pad structure. The pad structure consists of a first metal layer and a second metal layer, the first metal layer filling the opening of the passivation layer and having a width greater than the opening width, and the second metal layer is located on the first metal layer, with different thickness and curvature characteristics.

Benefits of technology

Through this structural design, the connection reliability and electrical reliability of semiconductor devices and external electronic devices are improved, the occurrence of impurities on the surface of the pad structure is reduced, and the stability of the structure is enhanced.

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Abstract

A semiconductor device is disclosed, comprising: a conductive pattern located on a substrate; a passivation layer located on the substrate and comprising an opening partially exposing the conductive pattern; and a pad structure, the pad structure being arranged on the passivation layer and in the opening of the passivation layer and connected to the conductive pattern. The pad structure comprises a first metal layer filling the opening of the passivation layer and having a width greater than the width of the opening and a second metal layer located on the first metal layer. The first metal layer has a first thickness at an outer wall of the first metal layer, a second thickness on a top surface of the passivation layer, and a third thickness on a top surface of the conductive pattern. The second thickness is greater than the first thickness, and the third thickness is greater than the second thickness.
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