Display device

Abstract

The present application relates to a display device, which includes a light-emitting element. A first transistor transmits a driving current to the light-emitting element. A second transistor is connected to a first electrode of the first transistor to transmit a data signal. A third transistor has a first electrode connected to a second electrode of the first transistor. An auxiliary transistor is connected between the second electrode of the third transistor and a gate electrode of the first transistor to transmit a data signal to the gate electrode of the first transistor. Each of the first transistor, the second transistor, and the auxiliary transistor is a first type transistor, and the third transistor is a second type transistor different from the first type transistor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2018-0070129, filed on Jun. 19, 2018, and Korean Patent Application No. 10-2019-0062730, filed on May 28, 2019, which are hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0003] Exemplary embodiments of the present invention generally relate to display devices, and more particularly, to an organic light emitting display having pixels each including a P-channel metal oxide semiconductor field effect transistor (PMOS transistor) and an N-channel metal-oxide semiconductor field effect transistor (NMOS transistor). Background Art

[0004] With the development of multimedia, display devices are becoming more and more important. Accordingly, various types of display devices are being used, such as liquid crystal display devices and display devices including self-luminous elements. Among them, the display device including the self-luminous element displays an image using the self-luminous element. The display device including the self-luminous element includes a plurality of transistors that provide a driving current to the self-luminous element.

[0005] P-channel metal oxide semiconductor field effect transistors (PMOS transistors) are widely used as transistors for display devices. However, research is being conducted to use N-channel metal oxide semiconductor field effect transistors (NMOS transistors) or to use both PMOS transistors and NMOS transistors.

[0006] PMOS transistors and NMOS transistors have different characteristics from each other. Depending on the parasitic capacitance, they also differ in the direction of the kickback voltage (positive or negative). Therefore, if some or all of the PMOS transistors are changed to NMOS transistors, the kickback voltage characteristics can be changed.

[0007] The above information disclosed in this Background section is only for understanding the background of the present inventive concept and therefore it may contain information that does not constitute the prior art. Summary of the invention

[0008] The device constructed according to the exemplary embodiment of the present invention can provide a display device that prevents the gate voltage of a transistor from being kicked back and lowered.

[0009] Additional features of the inventive concept will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the inventive concept.

[0010] According to an exemplary embodiment, a display device includes a light emitting element. A first transistor transmits a driving current to the light emitting element. A second transistor is connected to a first electrode of the first transistor to transmit a data signal. A third transistor has a first electrode connected to a second electrode of the first transistor. An auxiliary transistor is connected between the second electrode of the third transistor and a gate electrode of the first transistor to transmit a data signal to the gate electrode of the first transistor. Each of the first transistor, the second transistor, and the auxiliary transistor is a first type transistor, and the third transistor is a second type transistor different from the first type transistor.

[0011] The first type transistor may be a P-channel metal oxide semiconductor field effect transistor (PMOS transistor), and the second type transistor may be an N-channel metal oxide semiconductor field effect transistor (NMOS transistor).

[0012] The first type transistor may be a top gate transistor in which a gate electrode is arranged above the semiconductor layer, and the second type transistor may be a bottom gate transistor in which a gate electrode is arranged below the semiconductor layer.

[0013] The first type transistor may include an oxide semiconductor, and the second type transistor may include polysilicon.

[0014] The display device may further include a fourth transistor connected between the gate electrode of the first transistor and the initialization voltage line. Here, the fourth transistor may be a second type transistor.

[0015] The display device may further include: a fifth transistor connected between the first electrode of the first transistor and the first power supply voltage wiring; a sixth transistor connected between the second electrode of the first transistor and the first electrode of the light emitting element; a seventh transistor connected between the first electrode of the light emitting element and the initialization voltage line; and a storage capacitor formed between the first electrode of the first transistor and the first power supply voltage wiring. Here, each of the fifth transistor, the sixth transistor, and the seventh transistor may be a first type transistor.

[0016] The display device may further include a first scan line and a second scan line. Here, a gate electrode of the second transistor may be connected to the first scan line, a gate electrode of the auxiliary transistor may be connected to the first scan line, and a gate electrode of the third transistor may be connected to the second scan line.

[0017] The second transistor and the auxiliary transistor may be turned on in a first period in response to a first scan signal provided through the first scan line, and the third transistor may be turned on in the first period in response to a second scan signal provided through the second scan line.

[0018] The second transistor and the auxiliary transistor may be turned on in a first period in response to a first scan signal provided through the first scan line, the third transistor may be turned on in a second period in response to a second scan signal provided through the second scan line, and the second period may be greater than and include the first period.

[0019] The second scan signal may have a turn-on voltage level in a second period, and the second period of the second scan signal may partially overlap with the second period of the second scan signal at a previous time point.

[0020] In a plan view, the second scan line can be arranged in a first direction based on the first transistor and can extend in a second direction perpendicular to the first direction, the first scan line can be arranged in the first direction based on the second scan line and can be parallel to the second scan line, the third transistor can partially overlap with the second scan line, and the auxiliary transistor can partially overlap with the first scan line.

[0021] The third transistor may have a channel extending in the first direction, the auxiliary transistor may have a channel extending in the first direction, and the channel of the auxiliary transistor may be arranged on a line different from a line on which the channel of the third transistor extends.

[0022] The display device may further include a data pattern extending in the second direction. Here, one end of the data pattern may form an electrode of the third transistor, and the data pattern may be connected to the electrode of the third transistor through the first contact hole.

[0023] A first insulating layer may be disposed on the third transistor, a first scan line and a gate electrode of the third transistor may be disposed on the first insulating layer, and the second scan line may be disposed on a layer different from a layer on which the first scan line is disposed.

[0024] The display device may further include: a fourth transistor connected between the gate electrode of the first transistor and the initialization voltage line; a fifth transistor connected between the first electrode of the first transistor and the first power supply voltage wiring; a sixth transistor connected between the second electrode of the first transistor and the first electrode of the light-emitting element; a seventh transistor connected between the cathode electrode of the light-emitting element and the initialization voltage line; and a storage capacitor formed between the first electrode of the first transistor and the first power supply voltage wiring. Here, each of the fourth transistor and the seventh transistor may be a second type transistor, and each of the fifth transistor and the sixth transistor may be a first type transistor.

[0025] The display device may further include an emission control signal line connected to a gate electrode of each of the fifth to seventh transistors. Here, the fifth and sixth transistors may be turned on in response to an emission control signal provided by the emission control signal line during the third period, and the seventh transistor may be turned off in response to the emission control signal during the third period.

[0026] The light emitting element may be a quantum dot light emitting element.

[0027] According to another exemplary embodiment, the display device includes a light emitting element. The first transistor transmits a driving current to the light emitting element. The second transistor is connected to the first electrode of the first transistor to transmit a data signal. The third transistor is connected between the second electrode of the first transistor and the gate electrode of the first transistor to transmit the data signal to the gate electrode of the first transistor. Here, the third transistor may include a first sub-transistor and a second sub-transistor having different channel types and connected in series with each other.

[0028] The first sub-transistor may be a PMOS transistor, and the second sub-transistor may be an NMOS transistor.

[0029] The first sub-transistor may be a top-gate transistor in which a gate electrode is arranged above the semiconductor layer, and the second sub-transistor may be a bottom-gate transistor in which a gate electrode is arranged below the semiconductor layer.

[0030] The first sub-transistor may include an oxide semiconductor, and the second sub-transistor may include polysilicon.

[0031] The light emitting element may be a quantum dot light emitting element.

[0032] Therefore, the display device according to the exemplary embodiment can effectively prevent the gate voltage of the first transistor from being kicked back and dropped without significantly modifying the layout.

[0033] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the inventive concept.

[0035] Figure 1 is a block diagram of a display device according to an exemplary embodiment.

[0036] Figure 2 is included in Figure 1 A circuit diagram of a pixel in a display device.

[0037] Figure 3A , Figure 3B and Figure 3C is provided to Figure 2 Waveform diagram of the pixel signal.

[0038] Figure 4 yes Figure 2 Layout diagram of pixels.

[0039] Figure 5 is included in Figure 4 A plan view of the lower semiconductor layer in a pixel.

[0040] Figure 6 is included in Figure 4 A plan view of the fourth conductive layer and the fifth conductive layer overlapping each other in a pixel.

[0041] Figure 7 is along Figure 4 Cross-sectional views taken along lines AA' and BB'.

[0042] Figure 8 According to an exemplary embodiment, Figure 4 A cross-sectional view of another pixel taken along lines AA' and BB'.

[0043] Fig. 9 is a circuit diagram of a pixel according to an exemplary embodiment. DETAILED DESCRIPTION

[0044] In the following description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of various exemplary embodiments or implementations of the present invention. "Embodiment" and "implementation" as used herein are interchangeable words, which are non-limiting examples of one or more devices or methods in the inventive concept disclosed herein. However, it is apparent that various exemplary embodiments can be practiced without these specific details or with one or more equivalent arrangements. In other examples, known structures and devices are shown in block diagram form to avoid unnecessary confusion of various exemplary embodiments. In addition, various exemplary embodiments may be different, but not necessarily exclusive. For example, without departing from the inventive concept, the specific shape, configuration and characteristics of the exemplary embodiment may be used or implemented in another exemplary embodiment.

[0045] Unless otherwise specified, the embodiments shown should be understood as providing exemplary features of different details that can implement some ways of the present invention in practice. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects of various embodiments (hereinafter individually or collectively referred to as "elements") can be combined, separated, interchanged and / or rearranged in other ways without departing from the present invention.

[0046] The use of cross hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of cross hatching or shading will not convey or indicate any preference or requirement for a particular material, material property, size, ratio, commonality between the elements shown, and / or any other characteristics, features, attributes, etc. of the elements. In addition, in the drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. When the exemplary embodiments can be implemented differently, the specific process sequence can be performed differently from the described sequence. For example, two processes described in succession can be performed substantially simultaneously or in an order opposite to the described sequence. And, the same reference numerals represent the same elements.

[0047] When an element such as a layer is referred to as being "on" another element or layer, "connected to" or "coupled to" another element or layer, it may be directly on, connected to or coupled to another element or layer, or there may be an intermediate element or layer. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there are no intermediate elements or layers. For this reason, the term "connected" may indicate a physical, electrical and / or fluid connection with or without an intermediate element. In addition, the D1-axis, D2-axis and D3-axis are not limited to the three axes of a rectangular coordinate system (such as the x-axis, the y-axis and the z-axis), and may be interpreted in a broader sense. For example, the D1-axis, the D2-axis and the D3-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0048] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0049] Spatially relative terms such as "beneath," "below," "lower," "above," "upper," "over," "higher," "side" (e.g., as in "sidewall"), and the like may be used herein for descriptive purposes, and thus, to describe the relationship of one element to another element or elements as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientations depicted in the figures. For example, if the device in the figures is turned over, elements described as being "below" or "beneath" other elements or features would subsequently be oriented to be "above" the other elements or features. Thus, the exemplary term "below" may include both orientations of above and below. Furthermore, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and thus, the spatially relative terms used herein to describe the description are interpreted accordingly.

[0050] The terms used herein are for the purpose of describing specific embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" as used herein are also intended to include the plural forms. In addition, when the terms "comprise", "comprising", "include" and / or "including" are used in this specification, the existence of the stated features, wholes, steps, operations, elements, parts and / or clusters thereof is indicated, but the existence or addition of one or more other features, wholes, steps, operations, elements, parts and / or clusters thereof is not excluded. It is also noted that, as used herein, the terms "substantially", "about" and similar terms are used as terms of approximation rather than terms of degree, and thus, are used to take into account the inherent deviations of measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0051] Various exemplary embodiments are described herein with reference to cross-sectional views and / or exploded views, which are schematic diagrams of idealized exemplary embodiments and / or intermediate structures. Thus, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, the exemplary embodiments disclosed herein should not necessarily be limited to specific illustrated shapes of regions, but rather include shape deviations due to, for example, manufacturing. In this way, the regions shown in the drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and thus, are not necessarily intended to be limiting.

[0052] As is customary in the art, in terms of functional blocks, units and / or modules, some exemplary embodiments are shown and described in the accompanying drawings. It will be understood by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc. that can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques). In the case of blocks, units and / or modules implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and can be driven by firmware and / or software. It is also contemplated that each block, unit and / or module can be implemented by dedicated hardware, or implemented as a combination of dedicated hardware that performs some functions and processors that perform other functions (e.g., one or more programmed microprocessors and associated circuits). Moreover, without departing from the scope of the inventive concept, each block, unit and / or module of some exemplary embodiments can be physically separated into two or more interactive and discrete blocks, units and / or modules. Furthermore, the blocks, units and / or modules of some exemplary embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope of the inventive concept.

[0053] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. Unless explicitly defined as such herein, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and should not be interpreted in an idealized or overly formal sense.

[0054] Figure 1 is a block diagram of a display device 1 according to an exemplary embodiment.

[0055] Reference Figure 1 The display device 1 may include a display unit 10 , a scan driver 20 , a data driver 30 , an emission driver 40 , and a controller 50 . The display unit 10 includes pixels PX (or reference pixels or unit pixels).

[0056] The display device 1 (or the display unit 10) includes scan lines SL11 to SL1n, SL21 to SL2n, SL31 to SL3n, and SL41 to SL4n (where n is an integer of 2 or more), data lines DL1 to DLm (where m is an integer of 2 or more), and emission control lines EL1 to ELn. Pixels PX may be arranged at intersections of scan lines (SL11 to SL1n, SL21 to SL2n, SL31 to SL3n, and SL41 to SL4n) (where n is an integer of 2 or more), data lines (DL1 to DLm) (where m is an integer of 2 or more), and emission control lines (EL1 to ELn). The pixels PX may be arranged in a matrix form.

[0057] The scan lines SL11 to SL1n, SL21 to SL2n, SL31 to SL3n, and SL41 to SL4n may extend in a row direction. The emission control lines EL1 to ELn may extend in a row direction. The data lines DL1 to DLm may extend in a column direction. The row direction and the column direction may be reversed without departing from the scope of the inventive concept.

[0058] In addition, the display device 1 may include an initialization voltage wiring (or an initialization voltage supply line), a first power supply voltage wiring (or a first power supply voltage supply line), and a second power supply voltage wiring (or a second power supply voltage supply line).

[0059] The initialization voltage wiring is a wiring for supplying an initialization voltage VINT to the pixel PX, and each initialization voltage wiring may branch in each row to extend in the row direction. The first power supply voltage wiring is a wiring for supplying a first power supply voltage ELVDD to the pixel PX, and each wiring may branch in each column to extend in the column direction. The second power supply voltage wiring is a wiring for supplying a second power supply voltage ELVSS different from the first power supply voltage ELVDD to the pixel PX, and may be arranged in a mesh form. However, the present disclosure is not limited to the above, and the extension direction of the initialization voltage wiring and the extension direction of the first power supply voltage wiring may be changed differently.

[0060] Each of the pixels PX may be connected to four scan lines, one data line, one emission control line, one initialization voltage wiring, and one first power supply voltage wiring. For example, a pixel PX (hereinafter referred to as the 11th pixel) positioned in the first row (or first pixel row) and the first column (or first pixel column) may be connected to the first scan line SL11, the second scan line SL21, the third scan line SL31, and the fourth scan line SL41, the first data line DL1, the first emission control line EL1, one initialization voltage wiring, and one first power supply voltage wiring.

[0061] The scan driver 20 may generate first to fourth scan signals and provide the first to fourth scan signals to the pixels PX through the scan lines SL11 to SL1n, SL21 to SL2n, SL31 to SL3n, and SL41 to SL4n. Figure 2 The first scanning signal to the fourth scanning signal are described.

[0062] The data driver 30 may provide data signals to the pixels PX through the data lines DL1 to DLm. For example, when the first scan signal is provided to the pixel PX in the first row and the first column (ie, the 11th pixel) through the first scan line SL11, the data signal may be provided to the 11th pixel.

[0063] The emission driver 40 may generate an emission control signal and provide the emission control signal to the pixel PX through the emission control lines EL1 to ELn. The emission driver 40 (or the display device 1) may adjust the emission time of the pixel PX based on the emission control signal. Although the emission driver 40 is shown as being implemented separately from the scan driver 20, the present disclosure is not limited to this case. For example, the emission driver 40 may be integrally included in the scan driver 20. As another example, the emission driver 40 may be omitted depending on the circuit configuration of the pixel PX.

[0064] The controller 50 may convert image signals R, G, and B received from the outside (or an external device such as an application processor) into image data signals DR, DG, and DB, and may transmit the image data signals DR, DG, and DB to the data driver 30. In addition, the controller 50 may receive a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a clock signal MCLK, generate control signals for controlling the operation (or driving) of the scan driver 20, the data driver 30, and the emission driver 40, and transmit the control signals to the scan driver 20, the data driver 30, and the emission driver 40, respectively. Here, the control signal may include a scan drive control signal SCS for controlling the scan driver 20, a data drive control signal DCS for controlling the data driver 30, and a light emission drive control signal ECS for controlling the emission driver 40.

[0065] The display device 1 may further include a power supply unit (not shown). The power supply unit may generate a first power supply voltage ELVDD, a second power supply voltage ELVSS, and an initialization voltage VINT, and provide the first power supply voltage ELVDD, the second power supply voltage ELVSS, and the initialization voltage VINT to the pixel PX through a first power supply voltage wiring, a second power supply voltage wiring, and an initialization voltage wiring, respectively. The first power supply voltage ELVDD may be a predetermined high level voltage, and the second power supply voltage ELVSS may be a predetermined low level voltage. The voltage level of the second power supply voltage ELVSS may be lower than the voltage level of the first power supply voltage ELVDD. The power supply unit may be implemented as an external voltage source.

[0066] Each of the pixels PX may emit light of a certain brightness based on a driving current supplied to the organic light emitting element according to a data signal received through one of the data lines DL1 to DLm.

[0067] Figure 2 is included in Figure 1 1 is a circuit diagram of a pixel PX in a display device 1.

[0068] Reference Figure 2 , the pixel PX may include a light emitting element EL, a first transistor T1 to an eighth transistor T8, and a storage capacitor CST. The data signal DATA, the first scan signal GW_P, the second scan signal GW_N, the third scan signal GI, and the fourth scan signal GB may be provided to the pixel PX. Here, the third scan signal GI may be the same as the second scan signal GW_N at a previous time point or a previous row. For example, the third scan signal GI[n] provided to the pixel PX in the nth row may be the same as the second scan signal GW_N[n-1] provided to the pixel PX in the (n-1)th row. Similarly, the fourth scan signal GB may be the same as the first scan signal GW_P at a previous time point or a previous row. For example, the fourth scan signal GB[n] provided to the pixel PX in the nth row may be the same as the first scan signal GW_P[n-1] provided to the pixel PX in the (n-1)th row.

[0069] Each of the first to eighth transistors T1 to T8 may include a first electrode, a second electrode, and a gate electrode. One of the first and second electrodes may be a source electrode, and the other of the first and second electrodes may be a drain electrode.

[0070] Each of the first to eighth transistors T1 to T8 may be a thin film transistor. Each of the first to eighth transistors T1 to T8 may be a P-channel metal oxide semiconductor field effect transistor (PMOS transistor) or an N-channel metal oxide semiconductor field effect transistor (NMOS transistor).

[0071] In an exemplary embodiment, each of the first transistor T1, the second transistor T2, and the fifth transistor T5 to the eighth transistor T8 may be a PMOS transistor, and each of the third transistor T3 and the fourth transistor T4 may be an NMOS transistor. Compared with the PMOS transistor, the NMOS transistor has a relatively good turn-off characteristic. When each of the third transistor T3 and the fourth transistor T4 is an NMOS transistor, the leakage of the driving current Id in the emission period of the light emitting element EL can be reduced.

[0072] Each element of the pixel PX will now be described in detail.

[0073] First, the light emitting element EL may include an anode and a cathode. The anode of the light emitting element EL may be connected to the fifth node N5, and the cathode of the light emitting element EL may be connected to the second power supply voltage wiring for the second power supply voltage ELVSS.

[0074] The first transistor T1 (or driving transistor) may include a first electrode connected to the first node N1, a second electrode connected to the second node N2, and a gate electrode connected to the fourth node N4. The first transistor T1 may provide a driving current Id to the light emitting element EL based on a voltage of the fourth node N4 (or a data voltage stored in a storage capacitor CST to be described later).

[0075] The second transistor T2 (or the switching transistor) may include a first electrode connected to the data line (or receiving the data signal DATA), a second electrode connected to the first node N1, and a first electrode connected to the first scan line (eg, Figure 1 The second transistor T2 may be turned on in response to the first scan signal GW_P and may transmit the data signal DATA to the first node N1.

[0076] The third transistor T3 and the eighth transistor T8 (or the auxiliary transistor) may be connected in series between the second electrode and the gate electrode of the first transistor T1 (or between the second node N2 and the fourth node N4). The third transistor T3 and the eighth transistor T8 may transmit the data signal DATA received through the first node N1 and the second node N2 to the fourth node N4 (or the storage capacitor CST).

[0077] The third transistor T3 may include a first electrode connected to the second node N2, a second electrode connected to the third node N3, and a second electrode connected to the second scan line (eg, Figure 1The third transistor T3 may be turned on in response to the second scan signal GW_N and may transmit the data signal DATA to the third node N3.

[0078] The eighth transistor T8 may include a first electrode connected to the third node N3, a second electrode connected to the fourth node N4, and a gate electrode connected to the first scan line (e.g., the first scan line SL11) or receiving the first scan signal GW_P. The eighth transistor T8 may be turned on in response to the first scan signal GW_P and may transmit the data signal DATA to the fourth node N4.

[0079] As described above, the third transistor T3 can be implemented as an NMOS transistor to prevent the driving current Id from leaking from the second node N2 to the fourth node N4 during the emission driving period of the light emitting element EL. The eighth transistor T8 can be implemented as a PMOS transistor to prevent the voltage of the fourth node N4 (or the gate electrode of the first transistor T1) from dropping due to the kickback voltage of the third transistor T3.

[0080] The storage capacitor CST may be connected or formed between the fourth node N4 and the first power supply voltage ELVDD. The storage capacitor CST may store the supplied data signal DATA.

[0081] The fourth transistor T4 may include a first electrode connected to a fourth node N4, a second electrode connected to an initialization voltage wiring or receiving an initialization voltage VINT, and a third scan line (eg, Figure 1 The third scan line SL31 shown in ) or the gate electrode receiving the third scan signal GI.

[0082] Before the data signal DATA is stored in the storage capacitor CST or after the light emitting element EL emits light, the fourth transistor T4 may be turned on in response to the third scan signal GI and may initialize the fourth node N4 (or the storage capacitor CST) using the initialization voltage VINT.

[0083] As described above, the fourth transistor T4 implemented as an NMOS transistor can prevent the voltage of the fourth node N4 from dropping when the light emitting element EL emits light.

[0084] The fifth transistor T5 and the sixth transistor T6 (or the first emission control transistor and the second emission control transistor) are connected between the first power supply voltage wiring and the light emitting element EL, and may form a current path through which the drive current Id generated by the first transistor T1 flows.

[0085] The fifth transistor T5 may include a first electrode connected to the first power voltage wiring to receive the first power voltage ELVDD, a second electrode connected to the first node N1, and a second electrode connected to the emission control signal line (eg, Figure 1 The first emission control line EL1 shown in FIG. 8 or the gate electrode receiving the emission control signal EM.

[0086] Similarly, the sixth transistor T6 may include a first electrode connected to the second node N2, a second electrode connected to the fifth node N5 (or the anode of the organic light emitting element OLED), and a first electrode connected to the emission control signal line (eg, Figure 1 The first emission control line EL1 shown in FIG. 8 or the gate electrode receiving the emission control signal EM.

[0087] The fifth transistor T5 and the sixth transistor T6 may be turned on in response to the emission control signal EM. In this case, the driving current Id may be supplied to the light emitting element EL, and the light emitting element EL may emit light of brightness corresponding to the driving current Id.

[0088] The seventh transistor T7 may include a first electrode connected to the fifth node N5, a second electrode connected to the initialization voltage wiring (or the initialization voltage VINT), and a fourth scan line (eg, Figure 1 The fourth scan line SL41 shown in FIG. 8 or the gate electrode receiving the fourth scan signal GB.

[0089] Before or after the light emitting element EL emits light, the seventh transistor T7 may be turned on in response to the fourth scan signal GB, and the anode of the light emitting element EL may be initialized using the initialization voltage VINT. The light emitting element EL may have a parasitic capacitance CP_EL formed between the anode and the cathode (or the second power supply voltage ELVSS), and the parasitic capacitance CP_EL may be charged while the light emitting element EL emits light, so that the anode of the light emitting element EL can have a specific voltage. Therefore, the light emitting element EL may be initialized by the seventh transistor T7.

[0090] exist Figure 2 In FIG. 1 , the eighth transistor T8 is shown to be independent of the third transistor T3. However, the present disclosure is not limited to this case. For example, the third transistor T3 and the eighth transistor T8 may be implemented as or referred to as a dual-gate transistor.

[0091] FIG. 3A to FIG. 3C is provided to Figure 2 Graph showing a waveform of a signal of a pixel PX.

[0092] Reference Figure 2 and Figure 3A, the emission control signal EM may have a high level voltage (or a logic high level or an off voltage) in a first period PERIOD1 (e.g., a specific period starting from a first time point P1), and may have a low level voltage (or a logic low level or an on voltage) in the remaining time except the first period PERIOD1.

[0093] The third scan signal GI (or the previous second scan signal GW_N[n-1]) may have a high level voltage in the period between the second time point P2 and the third time point P3. The third scan signal GI may have a low level voltage in other periods of the first period PERIOD1 (for example, the period from the first time point P1 to the second time point P2 and the period after the third time point P3). The third scan signal GI (or the previous second scan signal GW_N[n-1]) may be a pulse signal having a first pulse width PW1.

[0094] In this case, reference Figure 2 The described fourth transistor T4 may be turned on in a period between the second time point P2 and the third time point P3 , and may initialize the fourth node N4 using the initialization voltage VINT.

[0095] The fourth scan signal GB (or the previous first scan signal GW_P[n-1]) may have a low level voltage in a period between the fifth time point P5 and the sixth time point P6. Here, the fifth time point P5 may be after the second time point P2, and the sixth time point P6 may be before the third time point P3. The fourth scan signal GB may be a pulse signal having a second pulse width PW2, and the second pulse width PW2 may be less than the first pulse width PW1, and may completely overlap with the first pulse width PW1.

[0096] In this case, reference Figure 2 The described seventh transistor T7 may be turned on in a period between the fifth time point P5 and the sixth time point P6 (or in a period between the second time point P2 and the third time point P3 ), and may initialize the light emitting element EL using the initialization voltage VINT.

[0097] The second scan signal GW_N (or the current second scan signal GW_N[n]) may have a high level voltage in a period between the third time point P3 and the fourth time point P4. Similar to the third scan signal GI, the second scan signal GW_N (or the current second scan signal GW_N[n]) may be a pulse signal having a first pulse width PW1. That is, the second scan signal GW_N may be a signal obtained by delaying the third scan signal GI by the first pulse width PW1.

[0098] The first scan signal GW_P (or the current first scan signal GW_P[n]) may have a low level voltage in a period between the seventh time point P7 and the eighth time point P8. Here, the seventh time point P7 may be after the third time point P3, and the eighth time point P8 may be before the fourth time point P4. The first scan signal GW_P may be a pulse signal having a second pulse width PW2. That is, the first scan signal GW_P may be a signal obtained by delaying the fourth scan signal GB by the first pulse width PW1.

[0099] exist Figure 2 The third transistor T3 shown in FIG. 1 may be turned on at a third time point P3 in response to the second scan signal GW_N. In this case, the third node voltage V_N3, which is the voltage of the third node N3, may be temporarily increased due to the kickback voltage (or turn-on kickback) of the third transistor T3. Since the third transistor T3 is implemented as an NMOS transistor, the kickback voltage caused by the turn-on of the third transistor T3 may be generated in the positive direction.

[0100] Then, in response to the first scan signal GW_P, the eighth transistor T8 may be turned on at the seventh time point P7. In this case, the third node voltage V_N3 may be temporarily reduced (or decreased) due to the kickback voltage (or turn-on kickback) of the eighth transistor T8. Since the eighth transistor T8 is implemented as a PMOS transistor, the kickback voltage caused by the turn-on of the eighth transistor T8 may be generated in the negative direction. When the capacitance of the eighth transistor T8 is similar to the capacitance of the third transistor T3 and the position of the eighth transistor T8 in the cross-sectional view is similar to the position of the third transistor T3, the magnitude of the kickback voltage of the eighth transistor T8 may be the same or similar to the magnitude of the kickback voltage of the third transistor T3.

[0101] When the third transistor T3 and the eighth transistor T8 are turned on (i.e., in the period between the seventh time point P7 and the eighth time point P8), the data signal DATA can be transmitted from the second node N2 to the fourth node N4 via the third node N3, and the third node voltage V_N3 (and the voltage of the fourth node N4) may increase linearly due to the transmission of the data signal DATA.

[0102] Then, in response to the first scan signal GW_P, the eighth transistor T8 may be turned off at an eighth time point P8. In this case, the third node voltage V_N3 may be temporarily increased due to the kickback voltage of the eighth transistor T8.

[0103] In response to the second scan signal GW_N, the third transistor T3 may be turned off at a fourth time point P4. In this case, the third node voltage V_N3 may temporarily drop due to a kickback voltage of the eighth transistor T8.

[0104] exist Figure 2 In the pixel circuit shown in FIG. 1 , if the second node N2 and the third node N3 are connected only by the third transistor T3, the voltage of the fourth node N4 (i.e., the gate voltage of the first transistor T1) may drop at the third time point P3 due to the kickback voltage of the third transistor T3. Accordingly, the pixel PX may emit light different from the desired brightness.

[0105] Therefore, the eighth transistor T8 can be additionally placed between the second node N2 and the third node N3 of the pixel PX, and can be turned on and off in the period when the third transistor T3 is turned on. Therefore, the drop of the third node voltage V_N3 (or the gate voltage of the first transistor T1) caused by the kickback voltage of the third transistor T3 can be compensated.

[0106] exist Figure 3A , the second scan signal GW_N is shown not to overlap with the third scan signal GI. However, this is merely an example, and the present disclosure is not limited to this example.

[0107] Reference Figure 3B , for example, the second scan signal GW_N may be transformed into a high level voltage at a ninth time point P9 before the third time point P3. In this case, the second scan signal GW_N may overlap with the third scan signal GI in the period between the ninth time point P9 and the third time point P3 (i.e., during the first time D1). At the same time, the first scan signal GW_P may be transformed into a low level voltage at the third time point P3, and may be transformed into a high level voltage at the tenth time point P10. That is, the first scan signal GW_P may be included in the second scan signal GW_N or overlap with the second scan signal GW_N, but may not overlap with the third scan signal GI.

[0108] exist Figure 3A , the second scan signal GW_N is illustrated as having a width greater than that of the first scan signal GW_P. However, this is merely an example, and the present disclosure is not limited to this example.

[0109] Reference Figure 3C , for example, the first to fourth scan signals GW_P to GW_N, GI and GB may have the same width.

[0110] As referenced above FIG. 3A to FIG. 3C As described above, the first scan signal GW_P may overlap the second scan signal GW_N, and a kickback voltage caused by the third transistor T3 operating in response to the second scan signal GW_N may be compensated by a kickback voltage caused by the eighth transistor T8 (a transistor operating in response to the first scan signal GW_P).

[0111] Figure 4 yes Figure 2 Layout diagram of pixel PX. Figure 5 is included in Figure 4 1 is a plan view of a lower semiconductor layer 100 in a pixel PX. Figure 6 is included in Figure 4 FIG. 1 is a plan view showing that the fourth conductive layer 600 and the fifth conductive layer 700 overlap each other in the pixel PX. Figure 7 is along Figure 4 Cross-sectional views taken along lines AA' and BB'.

[0112] In the following embodiments, in order to facilitate the description of the arrangement and connection relationship between the elements, even if some elements are Figure 1 and Figure 2 Elements mentioned in are substantially the same and these elements are also given new reference numerals.

[0113] Reference Figure 2 as well as Figures 4 to 7 , the pixel PX may include first to eighth transistors T1 to T8 , a storage capacitor CST, and a light emitting element EL.

[0114] Each of the first transistor T1 to the eighth transistor T8 may include a conductive layer forming an electrode, a semiconductor layer forming a channel, and an insulating layer. The first transistor T1, the second transistor T2, and the fifth transistor T5 to the eighth transistor T8 as PMOS transistors may be top-gate transistors in which the gate electrode is arranged above the semiconductor layer, and the third transistor T3 and the fourth transistor T4 as NMOS transistors may be bottom-gate transistors in which the gate electrode is arranged below the semiconductor layer.

[0115] The storage capacitor CST may include conductive layers forming electrodes and insulating layers disposed between the conductive layers.

[0116] The light emitting element EL may include conductive layers forming an anode and a cathode and a light emitting layer arranged between the conductive layers.

[0117] In some embodiments, the light emitting layer of the light emitting element EL may be an organic light emitting layer. That is, in some embodiments, the light emitting element EL may be an organic light emitting diode.

[0118] Alternatively, in some embodiments, the light emitting layer of the light emitting element EL may include a quantum dot material. That is, in some embodiments, the light emitting element EL may be a quantum dot light emitting diode.

[0119] Quantum dots can be particulate materials that emit light of a specific color when electrons transfer from the conduction band to the valence band.

[0120] Quantum dots can be semiconductor nanocrystal materials. Quantum dots can have specific band gaps depending on their composition and size. Therefore, quantum dots can absorb light and then emit light with a unique wavelength. Examples of semiconductor nanocrystals of quantum dots include IV group nanocrystals, II-VI group compound nanocrystals, III-V group compound nanocrystals, IV-VI group nanocrystals, and combinations thereof.

[0121] The II-VI compounds may be selected from: binary compounds selected from CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS and mixtures thereof; binary compounds selected from InZnP, AgInS, CuInS, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, Cd Ternary compounds of ZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, MgZnS and mixtures thereof; and quaternary compounds selected from HgZnTeS, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe and mixtures thereof.

[0122] The III-V compounds may be selected from: binary compounds selected from GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb and mixtures thereof; ternary compounds selected from GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InGaP, InNP, InAIP, InNAs, InNSb, InPAs, InPSb, GaAlNP and mixtures thereof; and quaternary compounds selected from GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb and mixtures thereof.

[0123] The IV-VI group compound may be selected from: a binary compound selected from SnS, SnSe, SnTe, PbS, PbSe, PbTe and mixtures thereof; a ternary compound selected from SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe and mixtures thereof; and a quaternary compound selected from SnPbSSe, SnPbSeTe, SnPbSTe and mixtures thereof. The IV group element may be selected from silicon (Si), germanium (Ge) and mixtures thereof. The IV group compound may be a binary compound selected from silicon carbide (SiC), silicon germanium (SiGe) and mixtures thereof.

[0124] Here, the binary, ternary or quaternary compounds may be present in the particles at a uniform concentration, or may be present in the same particles at partially different concentrations. In addition, they may have a core / shell structure in which one quantum dot surrounds another quantum dot. The interface between the core and the shell may have a concentration gradient in which the concentration of the element present in the shell decreases toward the center.

[0125] In some embodiments, quantum dots can have a core-shell structure, which includes a core containing the above-mentioned nanocrystals and a shell surrounding the core. The shell of each quantum dot can be used as a protective layer for maintaining semiconductor properties by preventing chemical denaturation of the core and / or as a charging layer for giving electrophoretic properties to quantum dots. The shell can be a single layer or multiple layers. The interface between the core and the shell can have a concentration gradient, wherein the concentration of the elements present in the shell decreases toward the center. The shell of each quantum dot can be, for example, a metal or non-metal oxide, a semiconductor compound, or a combination thereof.

[0126] For example, metal or non-metal oxides may be, but are not limited to, binary compounds such as SiO 2 、Al 2 O 3 、TiO 2 、ZnO、MnO、Mn 2 O 3 , Mn 3 O 4 , CuO, FeO, Fe 2 O 3 , Fe 3 O 4 , CoO, Co 3 O 4 or NiO; or ternary compounds such as MgAl 2 O 4 、CoFe 2 O 4 、NiFe 2 O 4 or CoMn2 O 4 .

[0127] In addition, the semiconductor compound can be but is not limited to: CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, ZnTeS, GaAs, GaP, GaSb, HgS, HgSe, HgTe, InAs, InP, InGaP, InSb, AlAs, AlP or AlSb.

[0128] When the light-emitting layer of the light-emitting element EL includes quantum dots, the light emitted from the light-emitting element EL may have a full width of half maximum (FWHM) of an emission wavelength spectrum of about 45 nm or less, about 40 nm or less, or about 30 nm or less. Therefore, the color purity and color gamut of the display device 1 may be further improved.

[0129] The electrical connection between the elements can be achieved through wiring made of a conductive layer and / or a through hole made of a conductive material. Conductive materials, conductive layers, semiconductor layers, insulating layers, light emitting layers, etc. are arranged on the substrate 910.

[0130] The pixel PX may include a substrate 910, a buffer layer 920, a lower semiconductor layer 100, a first insulating layer 810, a first conductive layer 200, a second insulating layer 820, a second conductive layer 300, a third insulating layer 830, an upper semiconductor layer 400, a third conductive layer 500, a fourth insulating layer 840, a fourth conductive layer 600, a fifth insulating layer 850, and a fifth conductive layer 700. The substrate 910, the buffer layer 920, the lower semiconductor layer 100, the first insulating layer 810, the first conductive layer 200, the second insulating layer 820, the second conductive layer 300, the third insulating layer 830, the upper semiconductor layer 400, the third conductive layer 500, the fourth insulating layer 840, the fourth conductive layer 600, the fifth insulating layer 850, and the fifth conductive layer 700 may be sequentially arranged or stacked.

[0131] Each of the above-mentioned layers may be a single layer or a laminated layer including a plurality of layers. Another layer may also be arranged between the layers.

[0132] The substrate 910 supports the layers arranged thereon. If the display device 1 is a bottom emission type or a dual emission type, a transparent substrate may be used. If the display device 1 is a top emission type, not only a transparent substrate but also a semi-transparent or opaque substrate may be used.

[0133] The substrate 910 may be made of an insulating material such as glass, quartz or a polymer resin. Examples of polymer materials may include polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP) and combinations thereof. The substrate 910 may also include a metal material.

[0134] The substrate 910 may be a rigid substrate or a flexible substrate that can be bent, folded, or rolled. An example of a material forming the flexible substrate may be polyimide (PI).

[0135] The buffer layer 920 may be arranged on the entire surface of the substrate 910. The buffer layer 920 may prevent the diffusion of impurity ions, prevent the penetration of moisture or external air, and perform a surface planarization function. The buffer layer 920 may include silicon nitride, silicon oxide, or silicon oxynitride. Depending on the type of the substrate 910 or process conditions, the buffer layer 920 may be omitted.

[0136] The lower semiconductor layer 100 is an active layer forming channels of the first transistor T1 , the second transistor T2 , and the fifth to eighth transistors T5 to T8 .

[0137] The lower semiconductor layer 100 may be provided separately in each pixel, but the present disclosure is not limited to this case. For example, two pixels adjacent in the row direction may have a horizontally inverted pixel structure relative to each other and may share one lower semiconductor layer 100 .

[0138] The lower semiconductor layer 100 may include a first lower semiconductor pattern and a second lower semiconductor pattern separated from each other within the pixel PX.

[0139] The lower semiconductor layer 100 may include a first vertical portion 110, a second vertical portion 120, a third vertical portion 130, and a horizontal portion 140 generally extending in a row direction. The first vertical portion 110, the second vertical portion 120, and the horizontal portion 140 may be physically connected to form a first lower semiconductor pattern. The third vertical portion 130 may form a second lower semiconductor pattern.

[0140] The first vertical portion 110 may be arranged adjacent to the left side of the pixel PX, the second vertical portion 120 may be arranged adjacent to the right side of the pixel PX, and the third vertical portion 130 may be arranged adjacent to the left side of the pixel PX. The first vertical portion 110, the second vertical portion 120, and the third vertical portion 130 may be spaced apart from each other. The length of the second vertical portion 120 in the column direction may be greater than the length of the first vertical portion 110, and may also be greater than the length of the third vertical portion 130. In addition, the length of the first vertical portion 110 may be greater than the length of the third vertical portion 130.

[0141] The horizontal portion 140 may connect one end (eg, the upper end) of the first vertical portion 110 to the middle portion of the second vertical portion 120. In this specification, based on Figure 4 , the “upper portion 121” of the second vertical portion 120 may refer to a portion positioned above the connection portion with the horizontal portion 140 in a plan view, and the “lower portion 122” of the second vertical portion 120 may refer to a portion positioned below the connection portion with the horizontal portion 140 in a plan view.

[0142] The horizontal portion 140 may connect the first vertical portion 110 and the second vertical portion 120 at the shortest distance, but may include a first curved portion on the left side and a second curved portion on the right side, such as Figure 5 The total length of the horizontal portion 140 can be increased by multiple bends.

[0143] The third vertical portion 130 may be spaced apart from the first vertical portion 110 , the second vertical portion 120 , and the horizontal portion 140 to be arranged in an island shape.

[0144] A channel of the first transistor T1 may be arranged in the horizontal portion 140, a channel of the second transistor T2 may be arranged in the upper portion 121 of the second vertical portion 120, a channel of the fifth transistor T5 may be arranged in the lower portion 122 of the second vertical portion 120, a channel of the sixth transistor T6 may be arranged in the first vertical portion 110, and a channel of the eighth transistor T8 may be arranged in the third vertical portion 130. Although not shown, a channel of the seventh transistor T7 may be arranged below the first vertical portion 110.

[0145] The lower semiconductor layer 100 may include polycrystalline silicon. Polycrystalline silicon may be formed by crystallizing amorphous silicon. Examples of crystallization methods include rapid thermal annealing (RTA), solid phase crystallization (SPC), excimer laser annealing (ELA), metal induced crystallization (MIC), metal induced lateral crystallization (MILC), and sequential lateral solidification (SLS). In another example, the lower semiconductor layer 100 may include single crystal silicon, low temperature polycrystalline silicon, amorphous silicon, etc.

[0146] Portions (source / drain regions) of the lower semiconductor layer 100 connected to the corresponding source / drain electrodes of the first transistor T1, the second transistor T2, and the fifth transistor T5 to the eighth transistor T8 may be doped with impurity ions (P-type impurities in the case of a PMOS transistor). A trivalent dopant such as boron (B) may be used as the P-type impurity ions.

[0147] The first insulating layer 810 may be disposed on the lower semiconductor layer 100, and may be disposed substantially on the entire surface of the substrate 910. The first insulating layer 810 may be a gate insulating layer having a gate insulating function.

[0148] The first insulating layer 810 may include a silicon compound, a metal oxide, or the like. For example, the first insulating layer 810 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or the like. These materials may be used alone or in combination with one another. The first insulating layer 810 may be a single layer or a multilayer consisting of laminated layers of different materials.

[0149] The first conductive layer 200 is disposed on the first insulating layer 810. The first conductive layer 200 may include a first scan line 210 transmitting a first scan signal GW_P, an emission control line 220 transmitting an emission control signal EM, and a gate electrode 230 of the first transistor T1.

[0150] The first scan line 210 may include a gate electrode of the second transistor T2 and a gate electrode of the eighth transistor T8 , and the emission control line 220 may include a gate electrode of the fifth transistor T5 and a gate electrode of the sixth transistor T6 .

[0151] Each of the first scan line 210 and the emission control line 220 may extend in a row direction. Each of the first scan line 210 and the emission control line 220 may extend in the row direction to an adjacent pixel beyond a boundary of the pixel PX.

[0152] In a plan view, the first scan line 210 may be positioned at an upper portion of the pixel PX. The first scan line 210 may overlap with an upper portion 121 of the second vertical portion 120 of the lower semiconductor layer 100, and a gate electrode of the second transistor T2 may be formed in an overlapping region where the first scan line 210 and the second vertical portion 120 of the lower semiconductor layer 100 overlap. The second vertical portion 120 of the lower semiconductor layer 100 positioned above the overlapping region may be a first electrode region (or a region where the first electrode is formed) of the second transistor T2, and the second vertical portion 120 of the lower semiconductor layer 100 positioned below the overlapping region may be a second electrode region of the second transistor T2.

[0153] Similarly, the first scan line 210 may overlap the third vertical portion 130 of the lower semiconductor layer 100, and the gate electrode of the eighth transistor T8 may be formed in an overlapping region where the first vertical scan line 210 and the third vertical portion 130 of the lower semiconductor layer 100 overlap. The third vertical portion 130 of the lower semiconductor layer 100 positioned above the overlapping region may be a first electrode region of the eighth transistor T8, and the third vertical portion 130 of the lower semiconductor layer 100 positioned below the overlapping region may be a second electrode region of the eighth transistor T8.

[0154] In a plan view, the emission control line 220 may be positioned at a lower portion of the pixel PX. The emission control line 220 may be positioned below the first scan line 210. The emission control line 220 may overlap the first vertical portion 110 and the lower portion 122 of the second vertical portion 120 of the lower semiconductor layer 100.

[0155] The gate electrode of the sixth transistor T6 may be formed in an overlapping region where the emission control line 220 overlaps the first vertical portion 110 of the lower semiconductor layer 100. The first vertical portion 110 of the lower semiconductor layer 100 positioned above the overlapping region may be a second electrode region of the sixth transistor T6, and the first vertical portion 110 of the lower semiconductor layer 100 positioned below the overlapping region may be a first electrode region of the sixth transistor T6.

[0156] Similarly, the gate electrode of the fifth transistor T5 may be formed in an overlapping region where the emission control line 220 overlaps the lower portion 122 of the second vertical portion 120 of the lower semiconductor layer 100. The second vertical portion 120 of the lower semiconductor layer 100 positioned above the overlapping region may be a first electrode region of the fifth transistor T5, and the second vertical portion 120 of the lower semiconductor layer 100 positioned below the overlapping region may be a second electrode region of the fifth transistor T5.

[0157] The gate electrode of the second transistor T2 , the gate electrode of the fifth transistor T5 , and the gate electrode of the sixth transistor T6 may be, but not necessarily, wider than surrounding lines.

[0158] The gate electrode 230 of the first transistor T1 may be positioned in the central portion of the pixel PX. In a plan view, the gate electrode 230 of the first transistor T1 may be positioned between the first scan line 210 and the emission control line 220. The gate electrode 230 of the first transistor T1 may be individually arranged in each pixel and may be arranged in an island shape.

[0159] The gate electrode 230 of the first transistor T1 may overlap the horizontal portion 140 of the lower semiconductor layer 100. The horizontal portion 140 of the lower semiconductor layer 100 positioned on the left side of the overlapping region where the gate electrode 230 of the first transistor T1 overlaps the horizontal portion 140 of the lower semiconductor layer 100 may be a first electrode region of the first transistor T1, and the horizontal portion 140 of the lower semiconductor layer 100 positioned on the right side of the overlapping region may be a second electrode region of the first transistor T1.

[0160] The first conductive layer 200 may include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first conductive layer 200 may be a single layer or multiple layers.

[0161] The second insulating layer 820 may be disposed on the first conductive layer 200, and may be disposed over the entire surface of the substrate 910. The second insulating layer 820 may serve to insulate the first conductive layer 200 from the second conductive layer 300, and may be an interlayer insulating film.

[0162] The second insulating layer 820 may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, or zinc oxide, or an organic insulating material such as polyacrylates resin, epoxy resin, phenolic resin, polyamides resin, polyimides resin, unsaturated polyesters resin, poly phenylenethers resin), polyphenylenesulfides resin, or benzocyclobutene (BCB). The second insulating layer 820 may be a single layer or a multilayer consisting of laminated layers of different materials.

[0163] The second conductive layer 300 is disposed on the second insulating layer 820. The second conductive layer 300 may include an initialization voltage line 310 transmitting an initialization voltage VINT, a second scan line 320 transmitting a second scan signal GW_N, a third scan line 330 transmitting a third scan signal GI, and an electrode line 340 of a storage capacitor CST. In addition, the second conductive layer 300 may include gate wirings of the third transistor T3 and the fourth transistor T4.

[0164] Each of the initialization voltage line 310, the second scan line 320, the third scan line 330, and the electrode line 340 of the storage capacitor CST may extend in the row direction. Each of the initialization voltage line 310, the second scan line 320, the third scan line 330, and the electrode line 340 of the storage capacitor CST may extend to an adjacent pixel beyond a boundary of the pixel PX in the row direction.

[0165] In a plan view, the initialization voltage line 310 may be positioned at the top of the pixel PX.

[0166] In a plan view, the second scan line 320 may be positioned above the first scan line 210 and below the initialization voltage line 310. The second scan line 320 may include a gate electrode of the third transistor T3.

[0167] In a plan view, the third scan line 330 may be positioned below the initialization voltage line 310 and above the second scan line 320. The third scan line 330 may include a gate electrode of the fourth transistor T4.

[0168] The gate electrode of the third transistor T3 and the gate electrode of the fourth transistor T4 may be, but not necessarily, wider than surrounding lines.

[0169] The electrode line 340 of the storage capacitor CST may cross the central portion of the pixel PX and may be arranged between the second scan line 320 and the emission control line 220 in a plan view. The electrode line 340 of the storage capacitor CST may overlap with the gate electrode 230 of the first transistor T1 with the second insulating layer 820 interposed therebetween. The gate electrode 230 of the first transistor T1 may be a first electrode of the storage capacitor CST, and an extended region of the electrode line 340 of the storage capacitor CST overlapping with the gate electrode 230 of the first transistor T1 may be a second electrode of the storage capacitor CST, and the second insulating layer 820 interposed between the electrode line 340 of the storage capacitor CST and the gate electrode 230 of the first transistor T1 may be a dielectric of the storage capacitor CST.

[0170] The width of the electrode line 340 of the storage capacitor CST may have an extended area in a region overlapping the gate electrode 230 of the first transistor T1. The electrode line 340 of the storage capacitor CST may include an opening overlapping the gate electrode 230 of the first transistor T1 in the extended area.

[0171] The second conductive layer 300 may include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W) and copper (Cu).

[0172] The third insulating layer 830 may be disposed on the second conductive layer 300 and may cover the second conductive layer 300. The third insulating layer 830 may be disposed substantially over the entire surface of the substrate 910. The third insulating layer 830 may be a gate insulating layer having a gate insulating function. The third insulating layer 830 may include the same material as the first insulating layer 810, or may include one or more materials selected from the example materials as the material of the first insulating layer 810. The third insulating layer 830 may be a single layer or a multilayer consisting of laminated layers of different materials.

[0173] The upper semiconductor layer 400 may be disposed on the third insulating layer 830. The upper semiconductor layer 400 may include a first upper semiconductor pattern 410 and a second upper semiconductor pattern 420 separated from each other within the pixel PX.

[0174] The first upper semiconductor pattern 410 may overlap with the gate electrode of the third transistor T3 to form a channel of the third transistor T3. Similarly, the second upper semiconductor pattern 420 may overlap with the gate electrode of the fourth transistor T4 to form a channel of the fourth transistor T4. The first upper semiconductor pattern 410 may have, but is not limited to, a rectangular shape.

[0175] The upper semiconductor layer 400 may include an oxide semiconductor. Examples of the oxide semiconductor may include a binary compound (AB) containing indium, zinc, gallium, tin, titanium, aluminum, hafnium (Hf), zirconium (Zr), magnesium (Mg), etc. X ), ternary compounds (AB X C Y ) and quaternary compounds (AB X C Y D Z In an exemplary embodiment, the upper semiconductor layer 400 may include ITZO (oxide including indium, tin, and titanium) or IGZO (oxide including indium, gallium, and tin).

[0176] The third conductive layer 500 may include first to fourth data patterns 510 to 530 .

[0177] The first to fourth data patterns 510 to 530 may be physically spaced apart from each other. Each of the first to fourth data patterns 510 to 530 may electrically connect the distal end portions of the first transistor T1, the third transistor T3, the fourth transistor T4, and the eighth transistor T8, and may form a first electrode or a second electrode of an NMOS transistor (e.g., the third transistor T3). When the third conductive layer 500 overlaps the upper semiconductor layer 400, it may directly contact or contact the upper surface of the upper semiconductor layer 400 through an ohmic contact layer.

[0178] The first data pattern 510 may overlap the gate electrode 230 of the first transistor T1. In the overlap region (i.e., the region where the first data pattern 510 overlaps the gate electrode 230 of the first transistor T1), a first contact hole CNT1 may be formed that penetrates the third insulating layer 830 and the second insulating layer 820 to expose the gate electrode 230 of the first transistor T1. The first data pattern 510 may be electrically connected to the gate electrode 230 of the first transistor T1 through the first contact hole CNT1.

[0179] The first contact hole CNT1 may be positioned in the opening of the electrode line 340 of the storage capacitor CST. In the first contact hole CNT1, the first data pattern 510 and the electrode line 340 of the storage capacitor CST adjacent to the first data pattern 510 may be insulated from each other by the third insulating layer 830.

[0180] The first data pattern 510 may extend upward from a region overlapping the gate electrode 230 of the first transistor T1, and may overlap the second scan line 320 while being insulated from the second scan line 320. The first data pattern 510 may further extend upward and overlap a lower portion of the third vertical portion 130 (or the second lower semiconductor pattern) of the lower semiconductor layer 100.

[0181] A second contact hole CNT2 penetrating the first insulating layer 810 to the third insulating layer 830 to expose the second electrode of the eighth transistor T8 may be formed in an area where the first data pattern 510 overlaps the third vertical portion 130 of the lower semiconductor layer 100. The first data pattern 510 may be electrically connected to the second electrode of the eighth transistor T8 through the second contact hole CNT2.

[0182] In addition, the first data pattern 510 may further extend upward and overlap the second upper semiconductor pattern 420. A portion of the first data pattern 510 overlapping the second upper semiconductor pattern 420 may form a first electrode of the fourth transistor T4.

[0183] The second data pattern 520 may overlap the first vertical portion 110 (or the horizontal portion 140) of the lower semiconductor layer 100. In a region where the second data pattern 520 overlaps the first vertical portion 110 of the lower semiconductor layer 100, a third contact hole CNT3 may be formed that penetrates the first insulating layer 810 to the third insulating layer 830 to expose the first vertical portion 110 of the lower semiconductor layer 100. The second data pattern 520 may be electrically connected to the second electrode of the first transistor T1 and / or the second electrode of the sixth transistor T6 through the third contact hole CNT3.

[0184] The second data pattern 520 may extend upward and overlap the first upper semiconductor pattern 410. A portion of the second data pattern 520 overlapping the first upper semiconductor pattern 410 may form a first electrode of the third transistor T3.

[0185] The third data pattern 530 may overlap the first upper semiconductor pattern 410. A portion of the third data pattern 530 overlapping the first upper semiconductor pattern 410 may form a second electrode of the third transistor T3.

[0186] In addition, the third data pattern 530 may overlap the third vertical portion 130 of the lower semiconductor layer 100. In the region where the third data pattern 530 overlaps the first upper semiconductor pattern 410, a fourth contact hole CNT4 may be formed that penetrates the first insulating layer 810 to the third insulating layer 830 to expose the third vertical portion 130 of the lower semiconductor layer 100. The third data pattern 530 may be electrically connected to the first electrode of the eighth transistor T8 through the fourth contact hole CNT4.

[0187] The third conductive layer 500 may include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W) and copper (Cu). The third conductive layer 500 may be a single layer or a multilayer. For example, the third conductive layer 500 may have a stacked structure of Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo or Ti / Cu.

[0188] The fourth insulating layer 840 may be disposed on the third conductive layer 500, and may be disposed over the entire surface of the substrate 910. The fourth insulating layer 840 may be an interlayer insulating layer that insulates the third conductive layer 500 from the fourth conductive layer 600. The fourth insulating layer 840 may include the same material as the above-described second insulating layer 820, or may include one or more materials selected from the materials exemplified as the materials of the second insulating layer 820. The fourth insulating layer 840 may be a single layer or a multilayer consisting of laminated layers of different materials.

[0189] The fourth conductive layer 600 is disposed on the fourth insulating layer 840. The fourth conductive layer 600 may include a first power voltage wiring 610 for supplying a first power voltage ELVDD, a bridge wiring 620 of the initialization voltage line 310, and fifth and sixth data patterns 630 and 640.

[0190] like Figure 6As shown in , the first power supply voltage wiring 610 may extend in the row direction through the central portion of the pixel PX. The first power supply voltage wiring 610 may extend along the row direction to an adjacent pixel beyond the boundary of the pixel PX. The first power supply voltage wiring 610 may extend upward from one side of the pixel PX and downward from the other side of the pixel PX. For example, the first power supply voltage wiring 610 may extend upward from the central left portion of the pixel PX and downward from the central right portion of the pixel PX. The first power supply voltage wiring 610 may also extend along the column direction to an adjacent pixel beyond the boundary of the pixel PX.

[0191] The first power supply voltage wiring 610 may cover most of the pixel PX except the bridge wiring 620 and the fifth and sixth data patterns 630 and 640. That is, the first power supply voltage wiring 610 may be formed as wide as possible. In this case, a relatively uniform current may be supplied to the pixel through the first power supply voltage wiring 610, and a long area of ​​the display device 1 may have a long range uniformity (LRU) of 90% or more. In addition, the first power supply voltage wiring 610, i.e., a direct current (DC) voltage wiring, may be formed between the gate electrode 230 of the first transistor T1 and the data line, which will be described later, to reduce crosstalk caused by the data line.

[0192] The bridge wiring 620 may overlap the initialization voltage line 310 and extend downward.

[0193] The fifth data pattern 630 may overlap the upper portion 121 of the second vertical portion 120 of the lower semiconductor layer 100. In a region where the fifth data pattern 630 overlaps the upper portion 121 of the second vertical portion 120 of the lower semiconductor layer 100, a sixth contact hole CNT6 may be formed that penetrates the first insulating layer 810 to the fourth insulating layer 840 to expose the lower semiconductor layer 100. The fifth data pattern 630 may be electrically connected to the first electrode of the second transistor T2 through the sixth contact hole CNT6.

[0194] The sixth data pattern 640 may overlap the first vertical portion 110 of the lower semiconductor layer 100. A fifth contact hole CNT5 may be formed in a region where the sixth data pattern 640 overlaps the first vertical portion 110 of the lower semiconductor layer 100. The sixth data pattern 640 may be electrically connected to the first electrode of the sixth transistor T6 through the fifth contact hole CNT5.

[0195] The fourth conductive layer 600 may include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W) and copper (Cu). The fourth conductive layer 600 may be a single layer or a multilayer. For example, the fourth conductive layer 600 may have a stacked structure of Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo or Ti / Cu.

[0196] The fifth insulating layer 850 may be disposed on the fourth conductive layer 600, and may be disposed substantially over the entire surface of the substrate 910. The fifth insulating layer 850 may insulate the fourth conductive layer 600 from the fifth conductive layer 700. The fifth insulating layer 850 may include the same material as the above-described second insulating layer 820, or may include one or more materials selected from the materials exemplified as the materials of the second insulating layer 820. The fifth insulating layer 850 may be a single layer or a multilayer consisting of laminated layers of different materials.

[0197] The fifth conductive layer 700 is disposed on the fifth insulating layer 850. The fifth conductive layer 700 may include a data line 710 and a via electrode 720.

[0198] The data line 710 may be arranged on the right side of the pixel PX and extend in the column direction. In the area where the data line 710 overlaps with the fifth data pattern 630, a twenty-first contact hole CNT21 penetrating the fifth insulating layer 850 to expose the fifth data pattern 630 may be formed. In this case, the data line 710 may be electrically connected to the fifth data pattern 630 through the twenty-first contact hole CNT21, and may also be electrically connected to the first electrode of the second transistor T2 through the fifth data pattern 630 and the eleventh contact hole CNT11.

[0199] The via electrode 720 may overlap the sixth data pattern 640. In a region where the via electrode 720 overlaps the sixth data pattern 640, a 22nd contact hole CNT22 penetrating the fifth insulating layer 850 to expose the sixth data pattern 640 may be formed. In this case, the via electrode 720 may be electrically connected to the sixth data pattern 640 through the 22nd contact hole CNT22, and may also be electrically connected to the second electrode of the sixth transistor T6 through the sixth data pattern 640 and the 12th contact hole CNT12.

[0200] The fifth conductive layer 700 may include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W) and copper (Cu). The fifth conductive layer 700 may be a single layer or a multilayer. For example, the fifth conductive layer 700 may have a stacked structure of Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo or Ti / Cu.

[0201] The sixth insulating layer 860 may be disposed on the fifth conductive layer 700, and may be disposed substantially over the entire surface of the substrate 910. The sixth insulating layer 860 may insulate the fifth conductive layer 700 from the light emitting element EL. The sixth insulating layer 860 may include the same material as the above-described second insulating layer 820, or may include one or more materials selected from the materials exemplified as the materials of the second insulating layer 820. The sixth insulating layer 860 may be a single layer or a multilayer consisting of laminated layers of different materials.

[0202] The anode ANODE of the light emitting element EL may be disposed on the sixth insulating layer 860. The anode ANODE may overlap the through-hole electrode 720. In a region where the anode ANODE overlaps the through-hole electrode 720, a contact hole (not shown) may be formed that penetrates the sixth insulating layer 860 to expose the through-hole electrode 720. The anode ANODE may be electrically connected to the through-hole electrode 720 through the contact hole (not shown).

[0203] In addition, the anode ANODE may overlap the third transistor T3 and the fourth transistor T4. In this case, the anode ANODE may block external light incident from above the third transistor T3 and the fourth transistor T4 (ie, bottom gate transistors).

[0204] The pixel defining layer PDL is arranged along the edge of the anode ANODE. Although not shown, the cathode CATHOD of the light emitting element EL may be arranged on the anode ANODE.

[0205] As referenced above Figures 4 to 6As described, each of the first transistor T1, the second transistor T2, and the fifth transistor T5 to the eighth transistor T8 may be a top-gate PMOS transistor, and each of the third transistor T3 and the fourth transistor T4 may be a bottom-gate NMOS transistor. In a plan view, the initialization voltage line 310, the third scan line 330, the first scan line 210, the second scan line 320, and the emission control line 220 may be arranged in sequence from the top to the bottom of the pixel PX. The third transistor T3 may overlap with the second scan line 320, and the eighth transistor T8 positioned above the third transistor T3 in the pixel PX may overlap with the first scan line 210. In addition, the third transistor T3, the eighth transistor T8, and the fourth transistor T4 may be arranged in sequence from the left side to the right side of the pixel PX.

[0206] exist Figure 7 In FIG. 1 , each of the third transistor T3 and the fourth transistor T4 is shown as a bottom-gate NMOS transistor. However, the present disclosure is not limited to this case. For example, each of the third transistor T3 and the fourth transistor T4 may also be a top-gate NMOS transistor.

[0207] Figure 8 is a cross-sectional view of a pixel according to an exemplary embodiment.

[0208] Reference Figure 2 , Figure 4 , Figure 7 and Figure 8 , the second scan line 320_1 (or the third conductive layer) may be disposed on the first upper semiconductor pattern 410 (or the upper semiconductor layer 400 ) instead of on the second insulating layer 820 .

[0209] The gate insulating layer GI3 may be disposed on the first upper semiconductor pattern 410 (or the upper semiconductor layer 400). The gate insulating layer GI3 may be disposed on the first upper semiconductor pattern 410 only in a region overlapping the second scan line 320_1.

[0210] The second scan line 320_1 may be disposed on the gate insulating layer GI3.

[0211] Although not shown, the fourth transistor T4 may have substantially the same stack structure as the third transistor T3 .

[0212] Therefore, the third transistor T3 (and the fourth transistor T4 ) may also be implemented as top-gate NMOS transistors.

[0213] Fig. 9 is a circuit diagram of a pixel PX_1 according to an exemplary embodiment.

[0214] Reference Figure 2 and Fig. 9 , pixel PX_1 and Figure 2 The pixel PX of FIG. 1 is different in that it includes the ninth transistor T9 but does not include the seventh transistor T7.

[0215] The light emitting element EL, the storage capacitor CST, and the first to sixth transistors T1 to T6 and the eighth transistor T8 are substantially the same as the light emitting element EL, the storage capacitor CST, and the first to sixth transistors T1 to T6 and the eighth transistor T8. Therefore, redundant descriptions are not repeated.

[0216] The ninth transistor T9 may include a first electrode connected to the fifth node N5, a second electrode connected to the initialization voltage line (or initialization voltage VINT), and a gate electrode connected to the emission control signal line or receiving the emission control signal EM.

[0217] The ninth transistor T9 may be an NMOS transistor. The ninth transistor T9 may receive the emission control signal EM in the same manner as the fifth transistor T5 and the sixth transistor T6, but may be turned on in a period different from the conduction period (or conduction timing) of the fifth transistor T5 and the sixth transistor T6. For example, when the emission control signal EM is a high level voltage (or a logic high level), the ninth transistor T9 may be turned on and the fifth transistor T5 and the sixth transistor T6 may be turned off. For another example, when the emission control signal EM is a low level voltage (or a logic low level), the ninth transistor T9 may be turned off and the fifth transistor T5 and the sixth transistor T6 may be turned on. Therefore, the initialization operation by the ninth transistor T9 may not be performed at the emission time when the fifth transistor T5 and the sixth transistor T6 are turned on, and may be performed at the non-emission time when the fifth transistor T5 and the sixth transistor T6 are turned off.

[0218] The display device according to the exemplary embodiments can effectively prevent the gate voltage of the first transistor from being kicked back and lowered without significantly modifying the layout.

[0219] Although certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Accordingly, the inventive concept is not limited to these embodiments, but to the broader scope of the appended claims and to various obvious modifications and equivalent arrangements apparent to those of ordinary skill in the art.

Claims

1. A display device, comprising: Light emitting element; a first transistor configured to transmit a driving current to the light emitting element; a second transistor connected to the first electrode of the first transistor and configured to transmit a data signal; a third transistor comprising a first electrode connected to the second electrode of the first transistor; as well as an auxiliary transistor connected between the second electrode of the third transistor and the gate electrode of the first transistor and configured to transmit the data signal to the gate electrode of the first transistor, wherein each of the first transistor, the second transistor and the auxiliary transistor is a first type transistor, and wherein the third transistor is a second type transistor different from the first type transistor, wherein the first type transistor is a P-channel metal oxide semiconductor field effect transistor, and wherein the second type transistor is an N-channel metal oxide semiconductor field effect transistor, Wherein, the display device further includes: a first scanning line, a second scanning line and a third scanning line, Initializing voltage lines; and a fourth transistor connected between the gate electrode of the first transistor and the initialization voltage line, wherein the fourth transistor is the second type transistor, wherein the gate electrode of the second transistor is connected to the first scan line, wherein the gate electrode of the auxiliary transistor is connected to the first scan line, wherein the gate electrode of the third transistor is connected to the second scan line, wherein the gate electrode of the fourth transistor is connected to the third scan line, wherein the second transistor and the auxiliary transistor are configured to be turned on in a first period in response to a first scan signal provided through the first scan line, and The third transistor is configured to be turned on in the first period in response to a second scan signal provided through the second scan line.

2. The display device according to claim 1, wherein: The first type transistor is a top gate transistor, in which the gate electrode is arranged above the semiconductor layer, and Wherein, the second type transistor is a bottom gate transistor, wherein the gate electrode is arranged below the semiconductor layer.

3. The display device according to claim 1, wherein: The first type transistor includes an oxide semiconductor, and Wherein, the second type transistor comprises polysilicon.

4. The display device according to claim 1, further comprising: a fifth transistor connected between the first electrode of the first transistor and a first power supply voltage wiring; a sixth transistor connected between the second electrode of the first transistor and the first electrode of the light emitting element; a seventh transistor connected between the first electrode of the light emitting element and the initialization voltage line; as well as a storage capacitor formed between the first electrode of the first transistor and the first power supply voltage wiring, Each of the fifth transistor, the sixth transistor and the seventh transistor is the first type transistor.

5. The display device according to claim 1, wherein: In a plan view, the second scan line is arranged in a first direction based on the first transistor and extends in a second direction perpendicular to the first direction, wherein the first scan line is arranged in the first direction based on the second scan line and is parallel to the second scan line, wherein the third transistor partially overlaps the second scan line, and The auxiliary transistor partially overlaps the first scan line.

6. The display device according to claim 5, wherein: The third transistor has a channel extending in the first direction, wherein the auxiliary transistor has a channel extending along the first direction, and The channel of the auxiliary transistor is located on a line different from a line along which the channel of the third transistor extends.

7. The display device according to claim 6, further comprising: a data pattern extending in a second direction, wherein one end of the data pattern forms an electrode of the third transistor, and The data pattern is connected to the electrode of the auxiliary transistor through a first contact hole.

8. The display device according to claim 1, wherein: A first insulating layer is disposed on the third transistor, the first scan line and a gate electrode of the third transistor are disposed on the first insulating layer, and the second scan line is disposed on a layer different from a layer on which the first scan line is disposed.

9. The display device according to claim 1, further comprising: a fifth transistor connected between the first electrode of the first transistor and a first power supply voltage wiring; a sixth transistor connected between the second electrode of the first transistor and the first electrode of the light emitting element; a seventh transistor connected between the cathode electrode of the light emitting element and an initialization voltage line; as well as a storage capacitor formed between the first electrode of the first transistor and a first power supply voltage wiring, wherein the seventh transistor is the second type transistor, and Wherein, each of the fifth transistor and the sixth transistor is the first type transistor.

10. The display device according to claim 9, further comprising: an emission control signal line connected to a gate electrode of each of the fifth transistor to the seventh transistor, wherein the fifth transistor and the sixth transistor are configured to be turned on in a third period in response to an emission control signal provided through the emission control signal line, and The seventh transistor is configured to be turned off in the third period in response to the emission control signal.

11. The display device according to claim 1, wherein: The light-emitting element is a quantum dot light-emitting element.

12. A display device, comprising: Light emitting element; a first transistor configured to transmit a driving current to the light emitting element; a second transistor connected to the first electrode of the first transistor and configured to transmit a data signal; a third transistor comprising a first electrode connected to the second electrode of the first transistor; as well as an auxiliary transistor connected between the second electrode of the third transistor and the gate electrode of the first transistor and configured to transmit the data signal to the gate electrode of the first transistor, wherein each of the first transistor, the second transistor and the auxiliary transistor is a first type transistor, and wherein the third transistor is a second type transistor different from the first type transistor, wherein the first type transistor is a P-channel metal oxide semiconductor field effect transistor, and wherein the second type transistor is an N-channel metal oxide semiconductor field effect transistor, Wherein, the display device further includes: a first scanning line, a second scanning line and a third scanning line, Initializing voltage lines; and a fourth transistor connected between the gate electrode of the first transistor and the initialization voltage line, wherein the fourth transistor is the second type transistor, wherein the gate electrode of the second transistor is connected to the first scan line, wherein the gate electrode of the auxiliary transistor is connected to the first scan line, wherein the gate electrode of the third transistor is connected to the second scan line, wherein the gate electrode of the fourth transistor is connected to the third scan line, The second transistor and the auxiliary transistor are configured to be turned on in a first period in response to a first scan signal provided through the first scan line. wherein the third transistor is configured to be turned on in a second period in response to a second scan signal provided through the second scan line, and The second time period is greater than the first time period and includes the first time period.

13. The display device according to claim 12, wherein: The second scanning signal has a turn-on voltage level in the second period, The second time period of the second scanning signal partially overlaps with the second time period of the second scanning signal provided by the second scanning line of the previous row.

14. A display device, comprising: Light emitting element; a first transistor configured to transmit a driving current to the light emitting element; a second transistor connected to the first electrode of the first transistor and configured to transmit a data signal; as well as a third transistor connected between the second electrode of the first transistor and the gate electrode of the first transistor and configured to transmit a data signal to the gate electrode of the first transistor, The third transistor includes a first sub-transistor and a second sub-transistor having different channel types and connected in series with each other, wherein the first sub-transistor is a PMOS transistor, and wherein the second sub-transistor is an NMOS transistor, Wherein, the display device further includes: a first scanning line, a second scanning line and a third scanning line, Initializing voltage lines; and a fourth transistor connected between the gate electrode of the first transistor and the initialization voltage line, Wherein, the fourth transistor is an NMOS transistor, wherein the gate electrode of the second transistor is connected to the first scan line, wherein the gate electrode of the first sub-transistor is connected to the first scan line, wherein the gate electrode of the second sub-transistor is connected to the second scan line, wherein the gate electrode of the fourth transistor is connected to the third scan line, wherein the second transistor and the first sub-transistor are configured to be turned on in a first period in response to a first scan signal provided through the first scan line, and The second sub-transistor is configured to be turned on in the first period in response to a second scan signal provided through the second scan line.

15. The display device according to claim 14, wherein: The first sub-transistor is a top-gate transistor having a gate electrode arranged above the semiconductor layer, and The second sub-transistor is a bottom-gate transistor whose gate electrode is arranged below the semiconductor layer.

16. The display device according to claim 14, wherein: The light-emitting element is a quantum dot light-emitting element.

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