77results about How to "Lower gate voltage" patented technology

The present invention provides a high quality thin film comparable to a bulk single crystal and providres a semiconductor device with superior characteristics. A channel layer 11, for example, is formed of a semiconductor such as zinc oxide ZnO or the like. A source 12, a drain 13, a gate 14 and a gate insulating layer 15 are formed on the channel layer 111 to form an FET. For a substrate 16, a proper material is selected depending on a thin film material of the channel layer 11 in consideration of compatibility of both lattice constants. For example, if ZnO is used for the semiconductor of the channel layer as a base material, ScAlMgO₄ or the like can be used for the substrate 16.

The invention relates to a circuit (20, 50) for voltage stabilization in an onboard power supply (10), particularly for motor vehicles, which is electrically connected between the onboard power supply (10) to be stabilized and a first energy store (E1). The circuit (20, 50) comprises a diode element (24) which contains a plurality of semiconductor switches (34) connected in parallel, a pilot and control circuit (33) which determines the level of a current flowing through the diode element (24) and controls the semiconductor switches (34) of the diode element (24) on the basis of the determined current level, and a second energy store (E2) which is electrically connected to the diode element (24) and to the onboard power supply (10).

A circuit and method for reducing losses in a DC/DC converter by optimizing gate drive voltage. The circuit and method detect a change in the output load, or more specifically the output current, and adjust the gate voltage accordingly; in other words, providing adaptive gate drive voltage. In response to a reduction of output current, the invention reduces the gate voltage so as to reduce both conduction and switching losses in the semiconductor switching devices in the output stage.

An IGBT is disclosed which separated into two groups (first and second IGBT portioZenerns). First and second Zener diodes each composed of series-connected Zener diode parts are disposed so as to correspond to the groups respectively. Each of the first and second Zener diodes has an anode side connected to a corresponding one of first and second polysilicon gate wirings, and a cathode side connected to an emitter electrode. Temperature dependence of a forward voltage drop of each of first and second Zener diodes is used for reducing a gate voltage of a group rising in temperature to throttle a current flowing in the group and reduce the temperature of the group to thereby attain equalization of the temperature distribution in a surface of a chip. In this manner, it is possible to provide an MOS type semiconductor device in which equalization of the temperature distribution in a surface of a chip or among chips can be attained.

An organic light emitting diode display includes a substrate, a semiconductor disposed on the substrate that includes a channel for each of a plurality of transistors and doping regions formed at both sides of each channel; a gate insulating layer disposed on the semiconductor that includes an insulating layer opening through which the doping regions of two different transistors are exposed; a gate electrode disposed on the gate insulating layer that overlaps each channel; an interlayer insulating layer disposed on the gate electrode that includes a first and second contact holes through which the doping regions exposed within the insulating layer opening are each exposed; and data wirings disposed on the interlayer insulating layer that are each connected to the doping regions. The interlayer insulating layer includes an organic layer, and the first and second contact holes each include a first side wall positioned within the insulating layer opening.

A TFT having a high threshold voltage is connected to the source electrode of each TFT that constitutes a CMOS circuit. In another aspect, pixel thin-film transistors are constructed such that a thin-film transistor more distant from a gate line drive circuit has a lower threshold voltage. In a further aspect, a control film that is removable in a later step is formed on the surface of the channel forming region of a TFT, and doping is performed from above the control film.

The invention discloses a low drop-out linear voltage stabilizer and a regulation circuit thereof. The low drop-out linear voltage stabilizer comprises a first PMOS (P-channel metal oxide semiconductor) transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS (N-channel metal oxide semiconductor) transistor and a first current source, wherein the grid electrode of the first PMOS transistor is connected with the drain electrode of the third PMOS transistor and the drain electrode of the first NMOS transistor; first voltage is input into the source electrode of the first PMOS transistor; the drain electrode is connected with the source electrode of the second PMOS transistor; the drain electrode of the first PMOS transistor is suitable to connect with the output end of the low drop-out linear voltage stabilizer; the grid electrode of the second PMOS transistor is suitable to connect with the output end of an error amplifier or buffer unit of the low drop-out linear voltage stabilizer; the drain electrode of the second PMOS transistor is connected with the source electrode of the first NMOS transistor and the first end of first current source; second voltage is input into the grid electrode of the third PMOS transistor, and the first voltage is input into the source electrode of the third PMOS transistor; the first voltage is input to the grid electrode of the first NMOS transistor; the second voltage is input into the second end of the first current source; and the voltage value of the first voltage is more than the voltage value of the second voltage.

A collector voltage of a power management semiconductor device is detected by a first comparator, and when the detected collector voltage exceeds a first reference voltage, the first comparator outputs a first detection signal. Furthermore, a gate voltage of the power management semiconductor device is detected by a second comparator, and when the detected gate voltage exceeds a second reference voltage, the second comparator outputs a second detection signal. The second reference voltage is a minimum gate voltage for feeding a rated power to the power management semiconductor device or over, and less than a line power voltage of a drive circuit of the power management semiconductor device. When both the first detection signal and second detection signal are being outputted, the gate voltage is reduced by a gate voltage reduction means so as to protect the power management semiconductor device from overcurrent and overvoltage.

A semiconductor memory has plural cell transistors that are arranged in a matrix. The cell transistor comprises a silicon substrate, a control gate, a pair of electrically isolated floating gates. Plural projections are formed in the P type silicon substrate, and a pair of N type diffusion regions as the source and the drain is formed in both sides of the projection. The control gate faces the projection via a fourth insulation layer. The side surface of the floating gates faces the side surfaces of the projection via a first insulation layer, and faces the control gate via a third insulation layer. The floating gate faces the diffusion region via the first insulation layer.

A driving circuit for driving an insulated gate semiconductor device based on a voltage of an externally-inputted gate signal, where the insulated gate semiconductor device has a source, a drain and a gate, and a parasitic capacitor exists between the drain and the gate. The driving circuit includes a gate voltage controlling semiconductor device disposed between, and connecting, the gate and the source of the insulated gate semiconductor device. The gate voltage controlling semiconductor device has a source and a gate, and is driven by a current charging the parasitic capacitor. The driving circuit also includes a pull-up device disposed between, and connecting, the source and the drain of the gate voltage controlling semiconductor device.

The present invention relates to a symmetric quadrupole structured field emission display without spacer comprising the upper and under substrates with a dielectric layer in between, wherein comb-like dielectric layer with lateral connection belts and a number of longitudinal working belts and longitudinal anodes are arranged on the upper substrate, bus electrodes are arranged longitudinally along the center on each anode, on the top, longitudinal alternating phosphor layer and dielectric layer for isolation on anode, gate electrodes are arranged on both sides of each longitudinal work belts, with the bus electrode as symmetry center, forming interdigital gate electrodes, horizontal cathode electrodes and longitudinal auxiliary electrodes are on the under substrate, resistor layer for current limiting and dielectric layer for cathode protection are arranged alternating horizontally on each cathode electrode, each intersect of the auxiliary electrode and cathode is isolated by the dielectric layer for cathode

A pseudo resistor circuit and a charge amplifier include a first field effect transistor; a second field effect transistor having electrical characteristics matched with electrical characteristics of the first field effect transistor; and a voltage dividing circuit with terminal of a reference resistor electrically connected to a source terminal of the second field effect transistor. Further, a first operational amplifier with an output terminal is connected to a gate terminal of the first field effect transistor and a gate terminal of the second field effect transistor and in which midpoint voltage of the voltage dividing circuit is input into either an inverting or non-inverting input terminal and reference voltage is input into the other of the inverting and non-inverting input terminal. Furthermore, a second operational amplifier supplies voltage resulting from inversion and amplification of drain voltage of the first field effect transistor into the other terminal of the resistor.