Electronic device and noise cancellation system

Abstract

The present invention provides an electronic device and a noise removal system, wherein the electronic device can remove burr noise of an input signal, and count and record the number of times the burr noise is removed. The electronic device involved in the present disclosure has a function of removing burrs contained in a signal, and comprises: a burr removal circuit that removes burrs of an input signal; and a counting unit that counts the number of times the burrs are removed.

Description

Technical Field

[0001] The present invention relates to an electronic device and a noise removal system. Background Art

[0002] In circuits, whisker-shaped pulse noise that is narrower than the normal pulse width is called a glitch. In logic circuits, when two input signals change at close times, a glitch may occur in the output. This phenomenon is mainly caused by the signal delay time of the two signals and is called racing.

[0003] In addition, when multiple output terminals in an integrated circuit change in the same direction at the same time, glitches may occur at adjacent terminals, which is called simultaneous switching noise. As another example, when there are two parallel signals, glitches may occur at the other terminal when one changes, which is called crosstalk. In addition, glitches may also occur due to various reasons such as electrostatic discharge and radiated electromagnetic fields.

[0004] These glitches may adversely affect the logic circuits of the next stage and the next stage thereafter. Therefore, a circuit for removing the glitches has been proposed (see, for example, Patent Document 1).

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Publication No. 2009-225153 Summary of the invention

[0008] Problem that the invention aims to solve

[0009] In the glitch removal circuit described in Patent Document 1, a signal is input to an n-stage D flip-flop circuit. When the outputs of the D flip-flop circuits in the n-stage D flip-flop circuits are consistent, the output of the last stage of the n-stage D flip-flop circuits is output. On the other hand, when the outputs of the D flip-flop circuits in the n-stage D flip-flop circuits are inconsistent, it is determined that glitch noise has occurred. Then, the previous output of the last stage of the n-stage D flip-flop circuits is maintained, thereby removing the glitch noise.

[0010] In addition, when a glitch noise with a large pulse width that cannot be removed by the glitch removal circuit is generated, it is a fatal error. Therefore, it is desirable to avoid the generation of such glitch noise with a large pulse width that cannot be removed. As the main reasons for the generation of glitch noise in the signal, the setting environment of the logic circuit, the non-conformity (deterioration) of the components, etc. can be considered. In addition, before the generation of glitch noise with a large pulse width that cannot be removed, the possibility of generating glitch noise with a small pulse width that can be removed is considered. Therefore, it is desirable to record the removal of the glitch noise at the stage where the glitch noise with a small pulse width that can be removed is generated. It is desirable to record the number of times the glitch noise has been removed in advance.

[0011] Solutions for solving problems

[0012] An electronic device according to one aspect of the present disclosure is an electronic device having a function of removing glitches included in a signal, and includes a glitch removal circuit that removes glitches from an input signal, and a counting unit that counts the number of times the glitches are removed.

[0013] Effects of the Invention

[0014] According to one aspect of the present disclosure, it is possible to remove glitch noise of an input signal, and it is possible to count and record the number of times the glitch noise is removed. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 1 is a circuit diagram showing an electronic device according to a first embodiment of the present disclosure.

[0016] Figure 2 1 is a circuit diagram showing an electronic device according to a second embodiment of the present disclosure.

[0017] Figure 3 It is shown Figure 2 A timing diagram of the changes in input signals, output signals, and increment values ​​of an electronic device.

[0018] Figure 4 : is a circuit diagram showing an electronic device according to a third embodiment of the present disclosure.

[0019] Figure 5 : is a circuit diagram showing an electronic device according to a fourth embodiment of the present disclosure.

[0020] Figure 6 1 is a circuit diagram showing an electronic device according to a fifth embodiment of the present disclosure.

[0021] Figure 7 : is a circuit diagram showing an electronic device according to a sixth embodiment of the present disclosure.

[0022] Figure 8: is a circuit diagram showing an electronic device according to a seventh embodiment of the present disclosure.

[0023] Fig. 9 This is a circuit diagram showing an initialization circuit that can be added to the electronic devices according to the first to fifth embodiments of the present disclosure.

[0024] Fig.10 1 is a circuit diagram showing an electronic device according to an eighth embodiment of the present disclosure.

[0025] Fig.11 : is a circuit diagram showing an electronic device according to a ninth embodiment of the present disclosure.

[0026] Fig.12 1 is a circuit diagram showing an electronic device according to a tenth embodiment of the present disclosure.

[0027] Fig.13 1 is a circuit diagram showing an electronic device according to an eleventh embodiment of the present disclosure.

[0028] Fig.14 This is a circuit diagram showing wiring when an initialization circuit is added to the electronic device according to the tenth and eleventh embodiments of the present disclosure.

[0029] Fig.15 1 is a circuit diagram showing an electronic device according to a twelfth embodiment of the present disclosure.

[0030] Fig.16 It is a block diagram showing the structure of one embodiment of the noise removal system according to the present disclosure.

[0031] Description of Reference Numerals

[0032] 1, 1a, 1b, 1c, 1d, 1e, 1f, 1g, 1h, 1i, 1k: electronic device; 2: information processing device; 10, 10a, 10b, 10c, 10d: glitch removal circuit; 12: original signal delay element; 13, 13a, 13b, 13c, 13d: output signal generation unit; 20, 20a, 20b, 20c, 20d, 20e, 20i, 20j, 20k: counting unit; 21: output signal delay element; 22, 22a, 22b, 22c, 22e: judgment signal generating unit; 23, 23e, 23i, 23k: incrementing unit; 30: electronic device control unit (judgment unit); 40: notification unit; 50: electronic device recording unit; 60: electronic device communication unit (counting and sending unit); 80: initialization circuit; 131: output generating OR circuit; 132: output generating AND circuit; 133: first switch; 134: second switch; 231, 232, 233: incrementers. DETAILED DESCRIPTION

[0033] Below, refer to Figure 1 to Figure 15 Various embodiments of the electronic device according to the present disclosure will be described.

[0034] [First embodiment]

[0035] Figure 1 1 is a circuit diagram showing an electronic device 1 according to a first embodiment of the present disclosure. The electronic device 1 has a function of removing glitch included in a signal. In the following description, "glitch noise" and "glitch" may be simply referred to as "glitch".

[0036] The electronic device 1 comprises: a glitch removal circuit 10 that removes glitches from an input signal; a counting unit 20 that counts the number of times the glitch removal circuit 10 removes glitches; an electronic device control unit 30 that performs control based on the count value of the counting unit 20; a notification unit 40 that notifies a user of the count value when the count value of the counting unit 20 exceeds a predetermined threshold value; an electronic device recording unit 50 that records the count value of the counting unit 20 in a log periodically or when a predetermined event occurs; and an electronic device communication unit 60 that communicates with an external device.

[0037] The glitch removal circuit 10 includes a signal input terminal 11 , n-stage (n is an integer greater than or equal to 1) original signal delay elements 12 , an output signal generation unit 13 for generating an output signal, and a signal output terminal 14 for outputting the output signal.

[0038] The signal input terminal 11 is a terminal connected to an external device not shown in the figure. The signal input terminal 11 is used to receive input of a signal output from an external device. The signal input terminal 11 is used, for example, to receive input of a signal that may contain glitches due to the influence of the installation environment of the external device, the defect (deterioration) of a component, etc. In addition, when the signal input to the signal input terminal 11 is not synchronized with the glitch removal circuit 10, a multi-stage (typically 2-stage or 3-stage) D flip-flop called a synchronizer (not shown) is inserted between the signal input terminal 11 and the glitch removal circuit 10 to synchronize the input signal. Hereinafter, the signal input to the signal input terminal 11 or the signal after passing through the synchronizer is also referred to as the "original signal".

[0039] The n-stage original signal delay element 12 is a circuit to which the original signal is input. The input terminal of the first-stage original signal delay element 12 among the n-stage original signal delay elements 12 is connected to the signal input terminal 11. In addition, the output terminal of the first-stage original signal delay element 12 is connected to the input terminal of the next-stage original signal delay element 12. The output terminal of the next-stage original signal delay element 12 is connected to the input terminal of the next-stage original signal delay element 12. In this way, the n-stage original signal delay element 12 is configured to be connected in series with the signal input terminal 11. In this embodiment, each of the n-stage original signal delay elements 12 is, for example, a D flip-flop. A clock signal including the same rising timing is input to each of the n-stage original signal delay elements 12. The first-stage original signal delay element 12 latches the output (original signal) of the signal input terminal 11 or the synchronizer at the rising time of the clock signal. In addition, each of the second-stage and the n-1-stage original signal delay elements 12 after the second-stage latches the output of the previous stage at the rising time of the clock signal. Furthermore, illustration of a circuit for inputting a clock signal is omitted for simplicity.

[0040] The output signal generating unit 13 is a circuit that generates an output signal based on the signal output from each original signal delay element in the n-stage original signal delay element 12 and the original signal. The input terminal of the output signal generating unit 13 is connected to the output of each original signal delay element in the n-stage original signal delay element 12 and the signal input terminal 11.

[0041] The signal output terminal 14 is a terminal for outputting a signal after burring is removed and is connected to an output terminal of the output signal generating unit 13 .

[0042] The counting unit 20 includes: an n-stage output signal delay element 21 to which an output signal is input; a determination signal generating unit 22 that generates a determination signal indicating whether the glitch removal circuit 10 has removed the glitch; and an incrementing unit 23 that counts the number of times the glitch has been removed based on the determination signal generating unit 22.

[0043] The n-stage output signal delay element 21 is a circuit to which the original signal is input. The input terminal of the first-stage output signal delay element 21 among the n-stage output signal delay elements 21 is connected to the output terminal of the output signal generating unit 13. In addition, the output terminal of the first-stage output signal delay element 21 is connected to the input terminal of the output signal delay element 21 of the next stage. The output terminal of the output signal delay element 21 of the next stage is connected to the input terminal of the output signal delay element 21 of the next stage. In this way, the n-stage output signal delay element 21 is configured to be cascade-connected to the output signal generating unit 13. In the present embodiment, each of the n-stage output signal delay elements 21 is, for example, a D flip-flop. A clock signal including the same rising timing is input to each of the n-stage output signal delay elements 21. The first-stage output signal delay element 21 latches the current output signal when the clock signal rises. In addition, the second-stage and subsequent-stage output signal delay elements 21 latch the output of the respective previous-stage output signal delay elements 21 when the clock signal rises.

[0044] The determination signal generating section 22 generates a determination signal indicating whether the glitch is removed based on the current output signal, the signal output from the output signal delay element 21 , and the signal output from the final stage of the original signal delay element 12 .

[0045] The incrementing unit 23 has an incrementer 231 that increments the number of times the burrs are removed and maintains the incremented number. The incrementer 231 is a circuit that increments (counts) the number of times the burrs are removed. The incrementing unit of this embodiment directly inputs the determination signal output by the determination signal generating unit 22 to the input terminal of the incrementer 231. The output terminal of the incrementer 231 is connected to the electronic device control unit 30 described later via the bus 70 or the like.

[0046] The incrementer 231 is composed of, for example, an adder and a register. When the determination signal is at a high level, the incrementer 231 increases the number of times the glitch is removed stored in the register by +1 (increments).

[0047] The counting unit 20 checks whether the glitch is removed in each clock cycle and increments the incrementer 231. That is, when the duration of the glitch removed by the glitch removal circuit 10 is two or more clock cycles, the counting unit 20 counts the number of times the glitch is removed as a plurality of times.

[0048] The electronic device control unit 30 may be configured to include a processor (CPU) that performs operations instructed by a program. The output value of the incrementer 231 is acquired to control the notification unit 40, the electronic device recording unit 50, and the electronic device communication unit 60 described later.

[0049] As a specific example, the electronic device control unit 30 has a function as a judgment unit for judging whether the number of times the burr is removed exceeds a predetermined threshold value in order to control the notification unit 40. In addition, the electronic device control unit 30 has a function of judging the timing for causing the electronic device recording unit 50 to record the count value. In addition, the electronic device control unit 30 has a function of transmitting the count value to be sent to the outside to the electronic device communication unit 60. Such various functions of the electronic device control unit 30 can be realized by a part of a program for respectively instructing the operation of the processor.

[0050] The notification unit 40 is, for example, a display device such as a monitor having a screen, a playback device that generates sound, an output device having a light source that is turned on, etc. The notification unit 40 can be configured to notify that the number of times counted exceeds a predetermined threshold value by displaying, generating sound, turning on a light source, etc. The notification unit 40 can also promote improvement of the installation environment and replacement of parts.

[0051] The electronic device recording unit 50 may be configured to include a storage device such as a memory or a hard disk drive. The electronic device recording unit 50 preferably records the count value of the counting unit 20 and the time when the count value is confirmed.

[0052] As an event for recording the count value in the electronic device recording unit 50 , for example, the occurrence of a fatal error can be cited.

[0053] The electronic device communication unit 60 functions as a count transmission unit that transmits the count value of the counter unit 20 to the outside. The electronic device communication unit 60 can be configured to include, for example, an Ethernet communication module, a wireless communication module, or the like.

[0054] Furthermore, the electronic device communication unit 60 can also be used as a second notification unit that transmits information indicating that the count value of the counting unit 20 exceeds a predetermined threshold to an external device when the number of times the burrs are removed exceeds a predetermined threshold.

[0055] According to the electronic device 1 of the first embodiment of the present disclosure described above, the following effects are achieved.

[0056] The electronic device 1 is an electronic device 1 having a function of removing glitches contained in a signal, and comprises: a glitch removal circuit 10, which removes glitches of an input signal; and a counting unit 20, which counts the number of times the glitches are removed. Thus, the number of times the glitches of the input signal are removed can be counted and recorded. Therefore, the electronic device 1 can confirm the number of times the glitches are removed, for example, the number of times the glitches are removed in the factory test of the electronic device 1. Thus, if the number of times the glitches are removed is other than 0, the individual of the electronic device 1 can be rejected. In addition, during the development of a substrate or a device, a test in which noise is applied is performed, thereby evaluating the noise resistance of a substrate or a device. If the number of times the glitches are removed is small, it can be said that the noise resistance of the substrate or the device is high (good design). On the contrary, if the number of times the glitches are removed is large, it can be said that the noise resistance of the substrate or the device is low (bad design). In this way, it can be beneficial to improve the design of the substrate or the device.

[0057] In the electronic device 1, the glitch removal circuit 10 includes: an n-stage original signal delay element 12 to which an original signal is input; and an output signal generating unit 13, which generates an output signal based on a signal output from the original signal delay element 12 and the original signal. Thus, an output signal from which glitch is appropriately removed can be output. In addition, in the electronic device 1, the counting unit 20 includes: an n-stage output signal delay element 21 to which an output signal is input; a determination signal generating unit 22, which generates a determination signal indicating whether glitch is removed based on a current output signal, a signal output from the output signal delay element, and a signal output from the last stage of the original signal delay element 12; and an incrementing unit 23, which includes an incrementer 231 that increments the number of times the glitch is removed and holds the incremented number, and increments the incrementer 231 based on the determination signal. Thus, the number of times the glitch is removed can be accurately counted.

[0058] The electronic device 1 further includes: an electronic device control unit 30 that determines whether the count value of the counting unit 20 exceeds a predetermined threshold value; and a notification unit 40 that notifies that the count value of the counting unit 20 exceeds the predetermined threshold value. Thus, notification can be made when the number of glitches exceeds the predetermined number. According to this structure, notification can be made before a large glitch that cannot be removed is input, so improvement can be promoted before an error caused by the large glitches occurs.

[0059] In the electronic device 1, the notification unit 40 can display on the screen that the count value of the counting unit 20 exceeds a predetermined threshold value. This can clearly notify that the glitch exceeds the predetermined number of times.

[0060] In the electronic device 1, the electronic device communication unit 60 as the second notification unit transmits information indicating that the count value of the counter unit 20 exceeds a predetermined threshold value to the outside. This allows an external device to recognize that the glitch has exceeded the predetermined number of times, thereby forming a system that can grasp the status of multiple electronic devices 1 at once.

[0061] The electronic device 1 further includes an electronic device recording unit 50 that records the count value of the counter unit in a log periodically or when a predetermined event occurs. This allows the change in the occurrence of burrs to be confirmed later.

[0062] [Second embodiment]

[0063] Figure 2 1 is a circuit diagram of an electronic device 1a according to a second embodiment of the present disclosure. The electronic device 1a is a device for removing low-level glitches that appear in a high-level input signal. In the following description, the same reference numerals are used to mark the same components as those in the previously described embodiment to omit repeated descriptions.

[0064] The electronic device 1a of this embodiment includes a glitch removal circuit 10a that removes glitch from an input signal, a counting unit 20a that counts the number of times the glitch removal circuit 10a removes glitch, and an electronic device control unit 30 that performs control based on the count value of the counting unit 20a.

[0065] The electronic device control unit 30 of the electronic device 1a of this embodiment is the same as the electronic device control unit 30 of the electronic device 1 of the first embodiment. The electronic device 1a of this embodiment can also include a notification unit 40, an electronic device recording unit 50, and an electronic device communication unit 60, but illustration and description thereof are omitted.

[0066] The glitch removal circuit 10a includes a signal input terminal 11, n-stage (n is an integer greater than or equal to 1) original signal delay elements 12, an output signal generation unit 13a for generating an output signal, and a signal output terminal 14 for outputting the output signal.

[0067] The output signal generating unit 13a is an output generating OR circuit 131 that outputs a logical sum. The output signal generating unit 13a outputs a logical sum of a signal output from each of the original signal delay elements 12 of the n-stage original signal and the original signal.

[0068] In the above glitch removal circuit 10a, the original signal is input to the signal input terminal 11. Therefore, a signal that may contain glitch noise in the low-level direction when at a high level is input to the original signal delay element 12. The n-stage original signal delay element 12 latches the original signal or the output signal of the original signal delay element 12 of the previous stage according to the rising of the clock signal. The original signal is input to the output signal generating unit 13a. In addition, the output of each original signal delay element 12 is input to the output signal generating unit 13a.

[0069] When the glitch overlaps with the rising of the clock and has a pulse width sufficient to satisfy the setup time and the hold time, the original signal delay element 12 of the first stage latches a low level according to the rising of the clock. At this time, when the next clock rises, the original signal delay element 12 of the second stage latches a low level as the output of the original signal delay element 12 of the first stage. When the next clock rises, the original signal delay element 12 of the third stage latches a low level as the output of the original signal delay element 12 of the second stage. In this way, the original signal delay element 12 of the nth stage latches a low level when the nth clock signal rises. However, since the other original signal delay elements 12 latch a high level, the output signal generating unit 13a outputs a high level.

[0070] Unless the original signal is at a low level and all the n-stage original signal delay elements 12 latch the low level, the output signal generating unit 13a outputs a high level. That is, unless the low level continues for n+1 times in the original signal, the output signal generating unit 13a outputs a high level. Thus, the glitch removal circuit 10a can remove glitches in the low level direction with a width as large as n clock cycles.

[0071] The counting unit 20a includes: an n-stage output signal delay element 21 to which an output signal is input; a determination signal generating unit 22a, which generates a determination signal indicating whether the burr removal circuit 10 has removed the burr; and an incrementing unit 23, which counts the number of times the burr has been removed based on the determination signal generating unit 22a.

[0072] The determination signal generating unit 22a comprises: a delayed signal inverter 221, which inverts the signal output from the final stage of the original signal delay element 12; and a determination AND circuit 222, which receives the output of the delayed signal inverter 221, the current output signal, and the signals output from all the output signal delay elements 21, and outputs their logical AND.

[0073] The determination signal generating unit 22a outputs a determination signal which is high level indicating that the burr has been removed only when the current output signal and the output signals of the past n times are high level and the original signal n times ago is low level. In other cases, the determination signal is low level.

[0074] exist Figure 3 , the clock signal, the original signal, the output signal and the count of the incrementer 231 in the electronic device 1a are shown in FIG. Figure 3 This is the case where n=1.

[0075] When the original signal becomes high level, the output signal generating unit 13a changes the output signal to high level. When the output signal is high level, unless the original signal is low level when the clock signal rises for more than n+1 consecutive times, the output signal generating unit 13a keeps the output signal at high level. Therefore, when the clock signal rises after the original signal becomes low level by n clock cycles, the output signal changes to low level. Therefore, even if the original signal is low level for a short time of less than n clock cycles due to glitch noise, the output signal generating unit 13a keeps the output signal at high level, that is, outputs an output signal with glitch removed.

[0076] The determination signal generating unit 22a sets the determination signal to a high level only when the output signal of the final-stage original signal delay element 12, which has been at a high level for n+1 times from n times before to the present and has output the same value as the original signal n times before, is at a low level indicating a glitch. That is, when the output signal remains at a high level n+1 times despite the original signal being at a low level at the rise of the clock n times before, the determination signal generating unit 22a outputs a determination signal indicating that the glitch has been removed.

[0077] Every time the determination signal output from the determination signal generating unit 22a changes to a high level, the incrementing unit 23 increases the count of the incrementer 231 by 1. When n is greater than 2 and the glitch spans the rise of multiple clocks, the determination signal generating unit 22a keeps the determination signal at a high level for multiple clock cycles. Therefore, when the width of the glitch is large, the count of the incrementer 231 increases by 1 or more.

[0078] According to the electronic device 1 a of the second embodiment described above, in addition to the effects of the first embodiment described above, the following effects are achieved.

[0079] In the electronic device 1a, when the current output signal is equal to the signals output from all the output signal delay elements 21 and the current output signal is different from the signal output from the final stage of the original signal delay element 12, the determination signal generating unit 22a generates a determination signal having a value indicating that the burr has been removed. Thus, the number of times the burr has been removed can be accurately counted.

[0080] In the electronic device 1a, the original signal delay element 12 is input with a signal that may contain glitch noise in the low-level direction when it is at a high level, and the output signal generation unit 13a outputs the logical OR of the signal output from each original signal delay element and the original signal. Thus, the output signal generation unit 13a outputs a high level except when the outputs of all the original signal delay elements 12 and the original signal are not at a high level. Therefore, even when the pulse width of the glitch spans the rise of multiple clocks, the glitch can be removed.

[0081] [Third Embodiment]

[0082] Figure 4 1 is a circuit diagram showing an electronic device 1 b according to a third embodiment of the present disclosure. The electronic device 1 b is a device for removing a high-level glitch that appears in a low-level input signal.

[0083] The electronic device 1b of this embodiment includes a glitch removal circuit 10b that removes glitch from an input signal, a counting unit 20b that counts the number of times the glitch removal circuit 10b removes glitch, and an electronic device control unit 30 that performs control based on the count value of the counting unit 20b.

[0084] The electronic device control section 30 of the electronic device 1 b of the third embodiment is the same as the electronic device control section 30 of the electronic device 1 of the first embodiment.

[0085] The glitch removal circuit 10b includes a signal input terminal 11, n-stage (n is an integer greater than or equal to 1) original signal delay elements 12, an output signal generation unit 13b for generating an output signal, and a signal output terminal 14 for outputting the output signal.

[0086] The output signal generating unit 13 b is an output generating AND circuit 132 that outputs a logical product of a signal output from each of the n-stage original signal delay elements 12 and an original signal.

[0087] In the glitch removal circuit 10 b , a signal which may contain glitch noise in the low-level direction when at a high level is input to the original signal delay element 12 .

[0088] Unless the original signal is at a high level and all the n-stage original signal delay elements 12 latch a high level, the output signal generating unit 13b outputs a low level. That is, unless the high level continues for n+1 times in the original signal, the output signal generating unit 13b outputs a low level. Thus, the glitch removal circuit 10b can remove glitches in the low level direction with a width as large as n clock cycles.

[0089] The counting unit 20b includes: an n-stage output signal delay element 21 to which an output signal is input; a determination signal generating unit 22b, which generates a determination signal indicating whether the burr removal circuit 10 has removed the burr; and an incrementing unit 23, which counts the number of times the burr has been removed based on the determination signal generating unit 22b.

[0090] The determination signal generating unit 22b comprises: a delay signal inverter 221, which inverts the signal output from the final stage of the original signal delay element 12; and a determination NOR circuit 223, which receives the output of the delay signal inverter 221, the current output signal, and the signals output from all the output signal delay elements 21, and outputs their logical negation.

[0091] The determination signal generating unit 22b outputs a determination signal which is high level indicating that the burr has been removed only when the current output signal and the output signals of the past n times are low level and the original signal n times ago is high level. In other cases, the determination signal is low level.

[0092] According to the electronic device 1 b of the third embodiment described above, in addition to the effects of the first embodiment described above, the following effects are achieved.

[0093] In the electronic device 1b, when the current output signal is equal to the signals output from all the output signal delay elements 21 and the current output signal is different from the signal output from the final stage of the original signal delay element 12, the determination signal generating unit 22b generates a determination signal having a value indicating that the burr has been removed. Thus, the number of times the burr has been removed can be accurately counted.

[0094] In the electronic device 1b, when the original signal delay element 12 is input with a signal that may contain glitch noise in the high-level direction at a low level, the output signal generating unit 13b outputs the logical AND of the signal output from each original signal delay element 12 and the original signal. Thus, except when the outputs of all the original signal delay elements of the n-stage original signal delay element 12 and the original signal are not at a high level, the output signal generating unit 13b outputs a low level as an output signal. Therefore, the output signal generating unit 13b can appropriately remove the high-level signal that is not continuous for more than n+1 cycles contained in the original signal as glitch noise.

[0095] [Fourth Embodiment]

[0096] Figure 5 1 is a circuit diagram showing an electronic device 1 c according to a fourth embodiment of the present disclosure. The electronic device 1 c is a device for removing high-level glitches appearing in a low-level input signal and removing low-level glitches appearing in a high-level input signal.

[0097] The electronic device 1c includes a glitch removal circuit 10c for removing glitches from an input signal, a counting unit 20c for counting the number of times the glitch removal circuit 10c removes glitches, and an electronic device control unit 30 for performing control based on the count value of the counting unit 20c.

[0098] The electronic device control unit 30 of the electronic device 1 c of the fourth embodiment is the same as the electronic device control unit 30 of the electronic device 1 of the first embodiment.

[0099] The glitch removal circuit 10c includes a signal input terminal 11, n-stage (n is an integer greater than or equal to 1) original signal delay elements 12, an output signal generation unit 13c for generating an output signal, and a signal output terminal 14 for outputting the output signal.

[0100] The output signal generating unit 13c includes: an output generating OR circuit 131, which outputs a logical sum of the output signals of all the original signal delay elements 12 and the original signal; an output generating AND circuit 132, which outputs a logical sum of the output signals of all the original signal delay elements 12 and the original signal; a first switch 133, which can invalidate the logical sum of the output generating OR circuit 131; a second switch 134, which can invalidate the logical sum of the output generating AND circuit 132; an XOR circuit 135, which outputs a logical exclusive OR of the output of the first switch 133 and the output of the second switch 134; an output latch delay element 136, which latches the output signal output by the output signal generating unit 13c; an output selector 137, which selects the original signal or the output of the output latch delay element 136 as the output signal output of the output signal generating unit 13c; a first selection terminal 138, which inputs a selection signal for selecting whether to remove the low-level burr contained in the high-level original signal; and a second selection terminal 139, which inputs a selection signal for selecting whether to remove the high-level burr contained in the low-level original signal.

[0101] The first switch 133 is a selector that receives the output of the output generating OR circuit 131 and the original signal, and receives the selection signal from the first selection terminal 138. When the selection signal is at a high level, the output of the output generating OR circuit 131 is output to the XOR circuit 135. When the selection signal is at a low level, the output of the output generating OR circuit 131 is invalidated and the original signal is output to the XOR circuit 135. The second switch 134 is a selector that receives the original signal and the output of the output generating AND circuit 132, and receives the selection signal from the second selection terminal 139. When the selection signal is at a high level, the output of the output generating AND circuit 132 is output to the XOR circuit 135. When the selection signal is at a low level, the output of the output generating AND circuit 132 is invalidated and the original signal is output to the XOR circuit 135. The output of the XOR circuit 135 is output as a selection signal to the output selector 137. The output latch delay element 136 is, for example, a D flip-flop, and stores the output signal of one clock cycle ago. When the output of the XOR circuit 135 is at a high level, the output selector 137 outputs the output of the output latch delay element 136, that is, the signal of the same value as the previous time, as the output signal. When the output of the XOR circuit 135 is at a low level, the output selector 137 outputs the original signal as the output signal.

[0102] Regarding the operation of the output signal generating unit 13 c having such a configuration, first, the operation when a high-level signal is input to each of the first selection terminal 138 and the second selection terminal 139 will be described separately.

[0103] (When the original signal is a high-level signal that may contain glitches)

[0104] Unless the original signal is at a low level and all the original signal delay elements 12 of the n-stage latch a low level, the output generation OR circuit 131 outputs a high level. Therefore, unless the low level continues n+1 times in the original signal, the output generation OR circuit 131 outputs a high level. At this time, the output generation AND circuit 132 outputs a high level only when the original signal is at a high level and all the original signal delay elements 12 of the n-stage latch a high level. On the other hand, when a part of the original signal delay elements 12 of the n-stage latch a low level, the output generation AND circuit 132 outputs a low level.

[0105] When both the output generation AND circuit 132 and the output generation OR circuit 131 output high levels, the XOR circuit 135 outputs low levels to the output selector 137. On the other hand, when the output generation AND circuit 132 outputs low levels, the XOR circuit 135 outputs high levels to the output selector 137.

[0106] When a low level is output from the XOR circuit 135, the output selector 137 outputs the original signal, i.e., a high level, to the signal output terminal 14. On the other hand, when a high level is output from the XOR circuit 135, the output of the output selector 137 one clock before latched by the output latch delay element 136 is output, i.e., a high level. Thus, glitches in the low level direction included in the high level signal can be removed.

[0107] (When the original signal is a low-level signal that may contain glitches)

[0108] Unless the original signal is at a high level or any of the original signal delay elements 12 in the n-stage latches a high level, the output generation OR circuit 131 outputs a low level. At this time, unless the original signal is at a low level and all the original signal delay elements 12 in the n-stage latch a low level, the output generation AND circuit 132 outputs a high level. Therefore, unless the high level continues for n+1 times in the original signal, the output generation AND circuit 132 outputs a low level.

[0109] When both the output generation AND circuit 132 and the output generation OR circuit 131 output low levels, the XOR circuit 135 outputs low levels to the output selector 137. On the other hand, when the output generation OR circuit 131 outputs high levels, the XOR circuit 135 outputs high levels to the output selector 137.

[0110] When a low level is output from the XOR circuit 135, the output selector 137 outputs the original signal, i.e., a high level, to the signal output terminal 14. On the other hand, when a high level is output from the XOR circuit 135, the output of the output selector 137 one clock before latched by the output latch delay element 136 is output, i.e., a high level. Thus, glitches in the high level direction included in the low level signal can be removed.

[0111] As described above, the glitch removal circuit 10 c can remove both the glitch in the high-level direction and the glitch in the low-level direction.

[0112] Next, the operation when a low-level signal is input to at least one of the first selection terminal 138 and the second selection terminal 139 will be described.

[0113] When the selection signal input from the first selection terminal 138 to the first switch 133 is at a low level and the selection signal input from the second selection terminal 139 to the second switch 134 is at a high level, the logical OR of the output generation OR circuit 131 is invalid, and the logical AND of the output generation AND circuit 132 is valid. Figure 5 The glitch removal circuit 10c is Figure 2 The glitch removal circuit 10a is equivalent to Figure 2 The glitch removal circuit 10a similarly removes the low-level glitch included in the high-level original signal.

[0114] When the selection signal input from the first selection terminal 138 to the first switch 133 is at a high level and the selection signal input from the second selection terminal 139 to the second switch 134 is at a low level, the logical OR of the output generation OR circuit 131 is valid, and the logical AND of the output generation AND circuit 132 is invalid. Figure 5 The glitch removal circuit 10c is Figure 4 The glitch removal circuit 10b is equivalent to Figure 4 The glitch removal circuit 10b similarly removes high-level glitches included in the low-level original signal.

[0115] When the selection signal input from the first selection terminal 138 to the first switch 133 is low level, and the selection signal input from the second selection terminal 139 to the second switch 134 is low level, the logical sum of the output generation OR circuit 131 and the logical sum of the output generation AND circuit 132 are both invalid. Figure 5 The glitch removal circuit 10c always outputs the original signal as an output signal without any change.

[0116] Like above, Figure 5 The electronic device 1 c can select four operation modes by setting the first switch 133 and the second switch 134 for one glitch removal circuit 10 a.

[0117] The counting section 20c includes: an n-stage output signal delay element 21 to which an output signal is input; a determination signal generating section 22c that generates a determination signal indicating whether the glitch removal circuit 10 has removed the glitch; and an incrementing section 23 that counts the number of times the glitch has been removed based on the determination signal generating section 22c. In addition, the output latch delay element 136 may also be used as the first stage of the output signal delay element 21.

[0118] The determination signal generating section 22c includes a determination AND circuit 224 which receives the current output signal and the signals output from all the output signal delay elements 21 and outputs a logical AND; a NOR circuit 225 which receives the current output signal and the signals output from all the output signal delay elements 21 and outputs a logical NOT; and a selector 226 which selects and outputs the output of the determination AND circuit 224 or the output of the NOR circuit 225. The output of the original signal delay element 12 at the final stage of the burr removal circuit 10c is input to the selector 226 as a selection signal. When the selection signal is at a high level, the output of the NOR circuit is output to the incrementing section 23, and when the selection signal is at a low level, the output of the AND circuit is output to the incrementing section 23.

[0119] Thus, when the current output signal is equal to the signals output from all the output signal delay elements 21 and different from the signal output from the final stage of the original signal delay element 12, the determination signal generating unit 22c generates a determination signal having a value indicating that the burr has been removed.

[0120] According to the electronic device 1 c of the fourth embodiment described above, in addition to the effects of the first embodiment described above, the following effects are achieved.

[0121] In the electronic device 1c, when the current output signal is equal to the signals output from all the output signal delay elements 21 and the current output signal is different from the signal output from the final stage of the original signal delay element 12, the determination signal generating unit 22c generates a determination signal having a value indicating that the burr has been removed. Thus, the number of times the burr has been removed can be accurately counted.

[0122] In the electronic device 1c, the original signal delay element 12 is input with a signal that may contain glitch noise in the low-level direction when the original signal is at a high level and may contain glitch noise in the high-level direction when the original signal is at a low level, and the output signal generation unit 13 generates an output signal based on the logical OR and logical AND of the signal output from each original signal delay element 12 and the original signal. Thus, even if the original signal is a high-level signal, the glitch can be removed. In addition, by comparing the signal output to the signal output terminal 14 with the output of the last stage of the original signal delay element 12, the number of times the glitch is removed can be counted. Therefore, the electronic device 1c has a relatively high versatility.

[0123] In the electronic device 1c, the output signal generating unit 13c further includes a first switch 133 for validating a logical OR and a second switch 134 for validating a logical AND. This makes it possible to selectively remove glitches in the original signal. Therefore, the electronic device 1c has relatively high versatility.

[0124] [Fifth Embodiment]

[0125] Figure 6 1 is a circuit diagram showing an electronic device 1d according to a fifth embodiment of the present disclosure. The electronic device 1d according to this embodiment is a device for removing high-level glitches appearing in low-level input signals and removing low-level glitches appearing in high-level input signals.

[0126] The electronic device 1d includes a glitch removal circuit 10d for removing glitches from an input signal, a counting unit 20d for counting the number of times the glitch removal circuit 10d removes glitches, and an electronic device control unit 30 for performing control based on the count value of the counting unit 20d.

[0127] The electronic device control unit 30 of the electronic device 1 d of the fifth embodiment is the same as the electronic device control unit 30 of the electronic device 1 of the first embodiment.

[0128] The glitch removal circuit 10d includes a signal input terminal 11, n-stage (n is an integer greater than or equal to 1) original signal delay elements 12, an output signal generation unit 13d for generating an output signal, and a signal output terminal 14 for outputting the output signal.

[0129] The output signal generating unit 13d comprises: an output generating OR circuit 131, which outputs the logical sum of the output signals of all the original signal delay elements 12 and the original signal; an output generating AND circuit 132, which outputs the logical sum of the output signals of all the original signal delay elements 12 and the original signal; a first selection terminal 138, which inputs a selection signal for selecting whether to remove the glitches in the low-level direction contained in the high-level original signal; a second selection terminal 139, which inputs a selection signal for selecting whether to remove the glitches in the high-level direction contained in the low-level original signal; a first selection AND circuit 140, which outputs the logical sum of the selection signal input from the first selection terminal 138 and the output of the output generating OR circuit 131; a first selection OR circuit 141, which outputs the first selection terminal 138. A selection AND circuit 140 is a logical OR of the output of the original signal; a selection signal inverter 142 is selected, which inverts the selection signal input from the first selection terminal 138; a second selection OR circuit 143, which outputs the logical OR of the output of the selection signal inverter 142 and the output generation AND circuit 132; a second selection AND circuit 144, which outputs the logical AND of the output of the second selection OR circuit 143 and the original signal; an output latch delay element 136, which latches the output signal; an output OR circuit 145, which outputs the logical OR of the output of the second selection OR circuit 143 and the output of the output latch delay element 136; and an output AND circuit 146, which outputs the logical AND of the output of the first selection OR circuit 141 and the output of the output OR circuit 145.

[0130] When the selection signal input from the first selection terminal 138 is at a high level, the first selection AND circuit 140 outputs the output of the output generation OR circuit 131 as it is, and when the selection signal input from the first selection terminal 138 is at a low level, the first selection AND circuit 140 outputs a low level signal regardless of the output of the output generation OR circuit 131. When the original signal is at a high level, the output of the output generation OR circuit 131 is always at a high level. Therefore, the output of the first selection OR circuit 141 is the original signal (the output when the logical OR of the output generation OR circuit 131 is invalid) or the output of the output generation OR circuit 131 (the output when the logical OR of the output generation OR circuit 131 is valid).

[0131] When the selection signal input from the second selection terminal 139 is at a high level, the second selection OR circuit 143 outputs the output of the output generation AND circuit 132 as it is, and when the selection signal input from the second selection terminal 139 is at a low level, the second selection OR circuit 143 outputs a high level signal regardless of the output of the output generation AND circuit 132. When the original signal is at a low level, the output of the output generation AND circuit 132 is necessarily at a low level. Therefore, the output of the second selection AND circuit 144 is the original signal (the output when the logical AND of the output generation AND circuit 132 is invalid) or the output of the output generation AND circuit 132 (the output when the logical AND of the output generation AND circuit 132 is valid).

[0132] The output latch delay element 136 stores the output signal of 1 clock cycle ago. When the previous output signal is high and the output of the second selection AND circuit 144 is high, the output of the output OR circuit 145 is high. When the output of the output OR circuit 145 and the output of the first selection OR circuit 141 are both high, the output of the output AND circuit 146 is high. When the output of the first selection OR circuit 141 (the output of the output generation OR circuit 131) and the output of the second selection AND circuit 144 (the output of the output generation AND circuit 132) are directly input to the output AND circuit 146, the output signal of the high level includes a signal of a glitch in the low level direction. However, the output signal generating unit 13 has the output latch delay element 136 and the output OR circuit 145, so once the output signal is high, even if the output of the second selection AND circuit 144 is low, the output OR circuit 145 outputs a high level signal the next time the output of the first selection OR circuit 141 is high. Thus, the output of the output AND circuit 146 is a signal obtained by removing the glitches in the low-level direction and the glitches in the high-level direction from the original signal.

[0133] The counting unit 20d includes: an n-stage output signal delay element 21 to which an output signal is input; a determination signal generating unit 22d that generates a determination signal indicating whether the glitch removal circuit 10 has removed the glitch; and an incrementing unit 23 that counts the number of times the glitch has been removed based on the determination signal generating unit 22d.

[0134] The determination signal generating unit 22d comprises: a delayed signal inverter 221, which inverts the signal output from the final stage of the original signal delay element 12; a determination AND circuit 222, which receives the output of the delayed signal inverter 221, the current output signal and the signals output from all the output signal delay elements 21 as input, and outputs the logical AND of these signals; a determination NOR circuit 223, which receives the output of the delayed signal inverter 221, the current output signal and the signals output from all the output signal delay elements 21 as input, and outputs the logical NOR of these signals; and a determination OR circuit 227, which outputs the logical OR of the output of the determination AND circuit 222 and the output of the determination NOR circuit 223.

[0135] When the glitch removal circuit 10d removes the glitch in the low-level direction from the high-level original signal, the output of the AND circuit 222 is determined to be high. When the glitch removal circuit 10d removes the glitch in the high-level direction from the low-level original signal, the output of the NOR circuit 223 is determined to be high. Therefore, when the glitch removal circuit 10d removes the glitch in either direction, the output of the NOR circuit 223 is determined to be high.

[0136] The electronic device 1 d according to the fifth embodiment described above also achieves the same effects as the electronic device 1 c according to the fourth embodiment described above.

[0137] [Sixth Embodiment]

[0138] Figure 7 1 is a circuit diagram showing an electronic device 1e according to a sixth embodiment of the present disclosure. The electronic device 1e of this embodiment is a device for removing high-level glitches appearing in low-level input signals and removing low-level glitches appearing in high-level input signals.

[0139] The electronic device 1e includes a glitch removal circuit 10c for removing glitches from an input signal, a counting unit 20e for counting the number of times the glitch removal circuit 10c removes glitches, and an electronic device control unit 30 for performing control based on the count value of the counting unit 20e.

[0140] The glitch removal circuit 10c of the electronic device 1e of the sixth embodiment is the same as the glitch removal circuit 10c of the electronic device 1c of the fourth embodiment. The electronic device control unit 30 of the electronic device 1e of the sixth embodiment is the same as the electronic device control unit 30 of the electronic device 1 of the first embodiment.

[0141] The counting unit 20e includes: an n-stage output signal delay element 21 to which an output signal is input; a determination signal generating unit 22e, which generates a determination signal indicating whether the burr removal circuit 10 has removed the burr; and an incrementing unit 23e, which counts the number of times the burr has been removed based on the determination signal generating unit 22e.

[0142] The determination signal generating section 22e includes: a delayed signal inverter 221 that inverts the signal output from the final stage of the original signal delay element 12; a determination AND circuit 222 that receives the output of the delayed signal inverter 221, the current output signal, and the signals output from all the output signal delay elements 21, and outputs the logical AND of these; and a determination NOR circuit 223 that receives the output of the delayed signal inverter 221, the current output signal, and the signals output from all the output signal delay elements 21, and outputs the logical NOR of these. The determination signal generating section 22e outputs the output of the determination AND circuit 222 as a first determination signal to the incrementing section 23e, and outputs the output of the determination NOR circuit 223 as a second determination signal to the incrementing section 23e.

[0143] The incrementing unit 23e includes: a first incrementer 232, which increments the number of times the glitch is removed every time the first determination signal outputted by the AND circuit 222 is determined to be at a high level; and a second incrementer 233, which increments the number of times the glitch is removed every time the second determination signal outputted by the NOR circuit 223 is determined to be at a high level. That is, the incrementing unit 23e uses the first incrementer 232 to count the number of times the glitch in the low-level direction of the high-level original signal is removed by the glitch removal circuit 10c, and uses the second incrementer 233 to count the number of times the glitch in the high-level direction of the low-level original signal is removed by the glitch removal circuit 10c.

[0144] The electronic device 1 e of the sixth embodiment described above counts the number of times the low-level glitch is removed and the number of times the high-level glitch is removed respectively by the incrementing unit 23 e , so that the occurrence of the glitch can be understood in more detail.

[0145] [Seventh Embodiment]

[0146] Figure 81 is a circuit diagram showing an electronic device 1f according to a seventh embodiment of the present disclosure. The electronic device 1f of this embodiment is a device for removing high-level glitches appearing in low-level input signals and removing low-level glitches appearing in high-level input signals.

[0147] The electronic device 1f includes a glitch removal circuit 10d for removing glitches from an input signal, a counting unit 20e for counting the number of times the glitch removal circuit 10d removes glitches, and an electronic device control unit 30 for performing control based on the count value of the counting unit 20e.

[0148] The glitch removal circuit 10d in the electronic device 1f of this embodiment is the same as the glitch removal circuit 10d in the electronic device 1d of the fifth embodiment. Also, the counting unit 20e in the electronic device 1f of this embodiment is the same as the counting unit 20e in the electronic device 1e of the sixth embodiment.

[0149] The electronic device 1f of the seventh embodiment also counts the number of times the glitch in the low-level direction is removed and the number of times the glitch in the high-level direction is removed by the incrementing unit 23e, and thus the occurrence of the glitch can be understood in more detail.

[0150] [Initialize Circuit]

[0151] Fig. 9 1 is a circuit diagram showing an initialization circuit 80 that can be added to the electronic devices 1a to 1f of the first to seventh embodiments of the present disclosure. The electronic device in which the initialization circuit 80 is added to the electronic devices 1a to 1f of the first to seventh embodiments is another embodiment of the present disclosure.

[0152] The initialization circuit 80 comprises: a reset terminal 81, to which a reset signal is input, and the reset signal is usually a negative logic signal, that is, it becomes a low level only when the count of the number of times the burr is removed from the high level is initialized; an original signal inverter 82, which inverts the original signal; a first initialization OR circuit 83, which outputs the logical OR of the output of the original signal inverter 82 and the reset signal input from the reset terminal 81; and a second initialization OR circuit 84, which outputs the logical OR of the original signal and the reset signal input from the reset terminal 81.

[0153] The reset signal input to the reset terminal 81 is input to the clear terminal of the incrementer 231 in addition to being input to the first initialization OR circuit 83 and the second initialization OR circuit 84. The output of the first initialization OR circuit 83 is input to the preset terminal for setting the hold value of each output signal delay element 21 to a high level. On the other hand, the output of the second initialization OR circuit 84 is input to the clear terminal for setting the hold value of each output signal delay element 21 to a low level. These clear terminals and preset terminals are all set to negative logic. Therefore, when the reset signal input to the reset terminal 81 is at a low level, the incrementer 231 resets the count to zero (initial setting). When the output of the first initialization OR circuit 83 is at a low level, the hold value of the output signal delay element 21 is set to a high level, and when the output of the second initialization OR circuit 84 is at a low level, the hold value of the output signal delay element 21 is set to a low level.

[0154] The output of the first initialization OR circuit 83 is low only when the original signal is high and the reset signal input from the reset terminal 81 is low. The output of the second initialization OR circuit 84 is low only when the original signal is low and the reset signal input from the reset terminal 81 is low. Therefore, when the original signal is high when the reset signal becomes low, the hold value of each output signal delay element 21 is initially set to a high level. In addition, when the original signal is low when the reset signal becomes low, the hold value of each output signal delay element 21 is initially set to a low level.

[0155] [Eighth Embodiment]

[0156] Fig.10 1 is a circuit diagram showing an electronic device 1g according to an eighth embodiment of the present disclosure. The electronic device 1g of this embodiment is an electronic device 1e of the sixth embodiment of the present disclosure with the addition of Fig. 9 The initialization circuit 80 is provided.

[0157] In the electronic device 1g, the reset signal input to the reset terminal 81 is input to the first initialization OR circuit 83 and the second initialization OR circuit 84, and is inverted and input to the clear terminals of the first incrementer 232 and the second incrementer 233. The output of the first initialization OR circuit 83 is inverted and input to the preset terminal of each output signal delay element 21, the preset terminal of each original signal delay element 12, and the preset terminal of the output latch delay element 136. The output of the second initialization OR circuit 84 is inverted and input to the clear terminal of each output signal delay element 21, the clear terminal of each original signal delay element 12, and the clear terminal of the output latch delay element 136.

[0158] According to the electronic device 1g of the eighth embodiment described above, in addition to the effects of the first and sixth embodiments described above, the following effects are achieved.

[0159] The electronic device 1g includes an initialization circuit 80. When a reset signal is input, the initialization circuit 80 initializes the original signal delay element 12, the output signal delay element 21, and the incrementing section 23e (incrementers 231, 232). Thus, the electronic device 1g can initialize the glitch removal circuit 10c and the counting section 20e. Therefore, the occurrence of glitches can be understood in more detail.

[0160] [Ninth Embodiment]

[0161] Fig.11 1 is a circuit diagram showing an electronic device 1h according to a ninth embodiment of the present disclosure. The electronic device 1h of this embodiment is an electronic device 1f according to the seventh embodiment of the present disclosure. Fig. 9 The initialization circuit 80 is provided.

[0162] In the electronic device 1h, the reset signal input to the reset terminal 81 is input to the first initialization OR circuit 83 and the second initialization OR circuit 84, and is inverted and input to the clear terminals of the first incrementer 232 and the second incrementer 233. The output of the first initialization OR circuit 83 is inverted and input to the preset terminal of each output signal delay element 21, the preset terminal of each original signal delay element 12, and the preset terminal of the output latch delay element 136. The output of the second initialization OR circuit 84 is inverted and input to the clear terminal of each output signal delay element 21, the clear terminal of each original signal delay element 12, and the clear terminal of the output latch delay element 136.

[0163] According to the electronic device 1h of the ninth embodiment described above, the electronic device 1h can also initialize the glitch removal circuit 10d and the counting unit 20e. Therefore, the occurrence of glitch can be understood in more detail.

[0164] [Tenth embodiment]

[0165] Fig.12 1 is a circuit diagram showing an electronic device 1i according to a tenth embodiment of the present disclosure. The electronic device 1i of the present embodiment is a device for removing a low-level glitch that appears in a high-level input signal.

[0166] The electronic device 1i of this embodiment includes: a glitch removal circuit 10a that removes glitch from an input signal; a counting unit 20i that counts the number of times the glitch removal circuit 10a removes glitch; and an electronic device control unit 30 that performs control based on the count value of the counting unit 20i.

[0167] The glitch removal circuit 10a in the electronic device 1i of this embodiment is the same as the glitch removal circuit 10a in the electronic device 1a of the second embodiment. The electronic device control unit 30 of the electronic device 1i of this embodiment is the same as the electronic device control unit 30 of the electronic device 1 of the first embodiment.

[0168] The counting unit 20i includes: an n-stage output signal delay element 21 to which an output signal is input; a determination signal generating unit 22a that generates a determination signal indicating whether the glitch removal circuit 10 has removed the glitch; and an incrementing unit 23i that counts the number of times the glitch has been removed based on the determination signal generating unit 22. The electronic device 1i of this embodiment differs from the electronic device 1a of the second embodiment only in the structure of the incrementing unit 23i.

[0169] The incrementing unit 23i includes: a determination signal delay element 234, which latches the determination signal output by the determination signal generating unit 22a; a determination signal inverting element 235, which inverts the output of the determination signal delay element 234; an incrementing AND circuit 236, which outputs a logical AND of the determination signal output by the determination signal generating unit 22a and the output of the determination signal inverting element 235; and an incrementer 231, which increments the count each time the output of the incrementing AND circuit 236 is at a high level.

[0170] The incrementing section 23i increments the incrementer 231 only when the current determination signal is at a high level and the previous determination signal is at a low level. Therefore, when the glitch removal circuit 10a continuously removes glitches in a plurality of clock cycles, the incrementing section 23i increments the incrementer only once. In other words, the counting section 20i counts the edges for determining the glitches removed by the glitch removal circuit 10a.

[0171] According to the electronic device 1i of the tenth embodiment described above, in addition to the effects of the first embodiment described above, the following effects are achieved.

[0172] When the duration of the glitch removed by the glitch removal circuit 10a is two clock cycles or longer, the electronic device 1i uses the counting unit 20i to count the number of times the glitch is removed as 1. This makes it possible to accurately grasp the occurrence of the glitch.

[0173] [Eleventh Embodiment]

[0174] Fig.13 1 is a circuit diagram showing an electronic device 1 j according to an eleventh embodiment of the present disclosure. The electronic device 1 j of this embodiment is a device for removing a high-level glitch that appears in a low-level input signal.

[0175] The electronic device 1j of this embodiment includes: a glitch removal circuit 10b that removes glitch from an input signal; a counting unit 20j that counts the number of times the glitch removal circuit 10b removes glitch; and an electronic device control unit 30 that performs control based on the count value of the counting unit 20j.

[0176] The counting unit 20j includes: an n-stage output signal delay element 21 to which an output signal is input; a determination signal generating unit 22a that generates a determination signal indicating whether the burr removal circuit 10 has removed the burr; and an incrementing unit 23i that counts the number of times the burr has been removed based on the determination signal generating unit 22. The electronic device 1j of this embodiment is a device in which the incrementing unit 23 of the electronic device 1b of the third embodiment is replaced by the incrementing unit 23i of the electronic device 1i of the tenth embodiment.

[0177] According to the electronic device 1j of the eleventh embodiment, the edges for determining the removed high-level glitch are counted, and the occurrence of the high-level glitch can be accurately grasped.

[0178] [Initialize Circuit]

[0179] Fig.14 The electronic device 1 of the tenth embodiment or the electronic device 1j of the eleventh embodiment is added with Fig. 9 A circuit diagram of the wiring when initializing the circuit 80.

[0180] When the initialization circuit 80 is added to the electronic device 1i, 1j having the incrementing section 23i, the reset signal input to the reset terminal 81 is also input to the clear terminal of the determination signal delay element 234. Therefore, when the reset signal input from the reset terminal 81 is at a low level, the determination signal delay element is initialized to a low level.

[0181] [Twelfth Embodiment]

[0182] Fig.15 1 is a circuit diagram showing an electronic device 1k according to a twelfth embodiment of the present disclosure. The electronic device 1k of this embodiment is a device for removing high-level glitches appearing in low-level input signals and removing low-level glitches appearing in high-level input signals.

[0183] The electronic device 1k includes a glitch removal circuit 10d for removing glitches from an input signal, a counting unit 20k for counting the number of times the glitch removal circuit 10d removes glitches, and an electronic device control unit 30 for performing control based on the count value of the counting unit 20k.

[0184] The glitch removal circuit 10d of the electronic device 1k of the twelfth embodiment is the same as the glitch removal circuit 10d of the electronic device 1d of the fifth embodiment. The electronic device control unit 30 of the electronic device 1k of the twelfth embodiment is the same as the electronic device control unit 30 of the electronic device 1 of the first embodiment.

[0185] The counting unit 20k includes: an n-stage output signal delay element 21 to which an output signal is input; a determination signal generating unit 22e, which generates a determination signal indicating whether the glitch removal circuit 10d has removed the glitch; and an incrementing unit 23k, which counts the number of times the glitch has been removed based on the determination signal generating unit 22e.

[0186] The determination signal generating unit 22e of the counting unit 20k of the present embodiment is the same as the determination signal generating unit 22e of the counting unit 20e of the sixth embodiment.

[0187] The incrementing section 23k includes: a first determination signal delay element 237 that latches the first determination signal output from the determination AND circuit 222 of the determination signal generating section 22e; a first determination signal inverting element 238 that inverts the output of the first determination signal delay element 237; a first incrementing AND circuit 239 that outputs a logical AND of the first determination signal output from the determination AND circuit 222 and the output of the first determination signal inverting element 238; and a first incrementer 232 that increments the counter whenever the output of the first incrementing AND circuit 239 is at a high level. The count is incremented; a second determination signal delay element 240, which latches the second determination signal output from the determination NOR circuit 223 of the determination signal generating unit 22e; a second determination signal inverting element 241, which inverts the output of the second determination signal delay element 240; a second incrementing AND circuit 242, which outputs the logical AND of the second determination signal output from the determination AND circuit 222 and the output of the second determination signal inverting element 241; and a second incrementer 233, which increments the count each time the output of the second incrementing AND circuit 242 is at a high level.

[0188] The first incrementer 232 counts the number of edges for determining the glitch in the low level direction removed by the glitch removal circuit 10d. The second incrementer 233 counts the number of edges for determining the glitch in the high level direction removed by the glitch removal circuit 10d.

[0189] The electronic device 1k of the twelfth embodiment described above counts the number of edges for determining the removed low-level glitches and the number of edges for determining the removed high-level glitches respectively by the incrementing unit 23k, thereby being able to grasp the occurrence of glitches in more detail.

[0190] [Noise Removal System]

[0191] Below, refer to Fig.16 An embodiment of the noise removal system according to the present disclosure will be described. Fig.16 It is a block diagram showing the structure of one embodiment of the noise removal system according to the present disclosure.

[0192] The noise removal system includes a plurality of electronic devices 1 and an information processing device 2 that communicates with one or more of the electronic devices 1 .

[0193] The electronic device 1 in the noise removal system of the present embodiment is the same as the electronic device 1 of the first embodiment.

[0194] The information processing device 2 includes: an information processing device communication unit 91, which receives the number of times the burrs are removed (count value) by communicating with the electronic device communication unit 60 of the electronic device 1; an information processing device control unit 92, which controls the information processing device communication unit 91; and an information processing device storage unit 93, which records the count value received by the information processing device communication unit 91.

[0195] The information processing device communication unit 91 can be configured similarly to the electronic device communication unit 60 and include, for example, an Ethernet communication module, a wireless communication module, and the like.

[0196] The information processing device control unit 92 can be configured to include a processor (CPU) that performs operations instructed by a program.

[0197] The information processing device storage unit 93 can be configured to include a storage device such as a memory or a hard disk drive.

[0198] In the information processing device 2, the information processing device control unit 92 obtains the number of times the burrs are removed obtained by counting each electronic device 1 via the information processing device communication unit 91. The information processing device control unit 92 stores the number of the electronic device 1 in association with the count value of the electronic device 1 in the information processing device storage unit 93. The information processing device 2 can also obtain the location information of the electronic device 1. The location information can be obtained using a location information acquisition system such as GPS, or can be obtained based on the number of the electronic device 1 based on the configuration of the electronic device 1 set in advance.

[0199] It is preferable that the count value is obtained from each electronic device 1 and recorded in the information processing device storage unit 93 periodically or when a predetermined event such as a fatal error occurs.

[0200] The information processing device control unit 92 may analyze the number of burr removals acquired from the electronic device 1. In the analysis of the number of burr removals, the number of burr removals of each electronic device 1 may be used as time series data, or the position information of the electronic device 1 may be used.

[0201] The information processing device 2 may further include an analysis result notification unit such as a monitor for notifying the analysis result of the glitch removal frequency. The information processing device may also transmit the analysis result of the glitch removal frequency to the electronic device 1 or other devices via the information processing device communication unit 91 .

[0202] According to the noise removal system according to one embodiment of the present disclosure described above, the following effects are achieved.

[0203] The noise removal system of one embodiment of the present disclosure described above comprises an electronic device 1 and an information processing device 2, wherein the information processing device 2 receives a count value from the electronic device 1 and records the received count value. Thus, the number of times that one or more electronic devices 1 remove glitch noise can be obtained, and the generation status of glitch can be comprehensively grasped.

[0204] As mentioned above, each preferred embodiment of the electronic device of the present disclosure has been described, but the present disclosure is not limited to the above-mentioned embodiments, and appropriate changes can be made.

[0205] For example, in the above embodiment, the original signal delay element 12 is described as a D flip-flop, but the present invention is not limited thereto and the original signal delay element 12 may also be a JK flip-flop.

Claims

1. An electronic device having the function of removing burrs contained in a signal, the electronic device comprising: a glitch removal circuit that removes glitch from an input signal; and a counting unit that counts the number of times the glitch is removed by confirming whether the glitch is removed in each clock cycle, in, The burr removal circuit has: an n-stage original signal delay element to which the original signal is input, wherein n is an integer greater than 1; and an output signal generating unit for generating an output signal based on the signal output from the original signal delay element and the original signal, The counting unit comprises: an n-stage output signal delay element to which the output signal is input; and A determination signal generating unit generates a determination signal indicating whether the glitch is removed based on a current output signal, a signal output from the output signal delay element, and a signal output from the final stage of the original signal delay element.

2. The electronic device according to claim 1, wherein: The counting unit further includes an incrementing unit having an incrementer for incrementing the number of times the burr is removed and holding the incremented number, and the incrementer is incremented based on the determination signal.

3. The electronic device according to claim 2, wherein: When the current output signal is equal to the signals output from all the output signal delay elements and the current output signal is different from the signal output from the final stage of the original signal delay element, the determination signal generating unit generates a determination signal indicating a value from which the glitch has been removed.

4. The electronic device according to claim 2 or 3, wherein: The incrementing unit increments the number of times the burr has been removed, when the determination signal has a value indicating that the burr has been removed and is different from the value of the previous determination signal.

5. The electronic device according to claim 2, An initialization circuit is further provided for initializing the original signal delay element, the output signal delay element, and the incrementing unit when a reset signal is input.

6. The electronic device according to claim 2, wherein: The output signal generating unit outputs a logical sum of the signal output from each of the original signal delay elements and the original signal.

7. The electronic device according to claim 2, wherein: The output signal generating unit outputs a logical product of the signal output from each of the original signal delay elements and the original signal.

8. The electronic device according to claim 2, wherein: The output signal generating unit generates an output signal based on a logical exclusive OR of a logical OR and a logical AND of a signal output from each of the n-stage original signal delay elements and an original signal.

9. The electronic device according to claim 8, wherein: The output signal generating unit further includes a first switch for activating a logical OR and a second switch for activating a logical AND.

10. The electronic device according to claim 1 or 2, further comprising: a determination unit configured to determine whether the count value of the counting unit exceeds a predetermined threshold value; and A notifying unit notifies the counting unit that the count value exceeds a predetermined threshold value.

11. The electronic device according to claim 10, wherein: The notification unit displays on a screen that the count value of the counting unit exceeds a predetermined threshold value.

12. The electronic device according to claim 10, wherein: The notification unit transmits information indicating that the count value of the counting unit exceeds a predetermined threshold value to the outside.

13. The electronic device according to claim 1 or 2, The device further includes a recording unit that records the count value of the counting unit in a log periodically or when a predetermined event occurs.

14. The electronic device according to claim 1 or 2, The device further includes a count transmission unit that transmits the count value of the count unit to the outside.

15. A noise removal system comprising: The electronic device according to claim 14; and The information processing device receives the count value from the electronic device and records the received count value.

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